riscv/rocket-chip
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Author SHA1 Message Date
Howard Mao 0b15b19381 add arbiter for FPU 2015-12-01 10:22:31 -08:00
Howard Mao 1db2da00f3 Merge branch 'master' into rocc-fpu-port 2015-11-30 19:18:58 -08:00
Howard Mao e4043570bd bump groundtest and hardfloat 2015-11-30 18:06:15 -08:00
Howard Mao 40d68406d6 use xlen parameter for ALU 2015-11-30 18:04:44 -08:00
Howard Mao e80340198a use implicit parameters for ALU 2015-11-30 17:35:33 -08:00
Colin Schmidt ec4ade988b [travis] add multiple configs including rocc 2015-11-28 07:17:49 -08:00
Colin Schmidt 7259239ba4 Merge pull request #31 from ucb-bar/multirocc 
implement support for multiple RoCC accelerators
 2015-11-28 08:56:07 -05:00
Colin Schmidt 90991014a0 Merge pull request #19 from ucb-bar/multirocc 
Add support for multiple RoCC accelerators
 2015-11-28 08:56:04 -05:00
Howard Mao 7083576156 fix typo in NastiErrorSlave 2015-11-26 12:57:04 -08:00
Howard Mao 23f0756978 implement support for multiple RoCC accelerators 2015-11-26 12:49:04 -08:00
Howard Mao 9256239206 implement support for multiple RoCC accelerators 2015-11-26 12:46:01 -08:00
Howard Mao 58b0a86834 some modifications to AccumulatorExample 2015-11-26 08:48:19 -08:00
Andrew Waterman e25a020e60 Construct device tree ROM in MMIO region 
Rebuild riscv-tools for this to work!
 2015-11-25 21:23:37 -08:00
Andrew Waterman e52685f2e9 Fix LoadGen zero flag 2015-11-25 20:52:30 -08:00
Andrew Waterman 27df04354f Add ROM with NASTI interface 2015-11-25 20:04:31 -08:00
Andrew Waterman 49d93da87e Factor out more common zscale code 2015-11-24 19:17:21 -08:00
Andrew Waterman e203b8b378 Make ALU generic for zscale 2015-11-24 19:17:07 -08:00
Andrew Waterman 52b25c3da0 Factor out more common zscale code 2015-11-24 18:34:03 -08:00
Andrew Waterman 5294e94794 Remove CSR back pressure ability 
We were using it for IPIs, but no longer need it.
 2015-11-24 18:28:14 -08:00
Andrew Waterman 4616db4695 Make RegFile/ImmGen usable by zscale 2015-11-24 18:27:07 -08:00
Andrew Waterman 1761db3272 Factor out some common code from zscale 2015-11-24 18:14:06 -08:00
Andrew Waterman 6d1bf5c014 Use generic LoadGen/StoreGen 2015-11-24 18:13:33 -08:00
Andrew Waterman 57e82442a1 Make LoadGen and StoreGen generic 2015-11-24 18:12:42 -08:00
Howard Mao ec6bfde9a3 fix WritebackUnit issue in uncore 2015-11-21 16:11:22 -08:00
Howard Mao ee6514e4f4 make sure WritebackUnit sends correct probe addresses 2015-11-21 15:55:11 -08:00
Howard Mao 04383a31f5 Revert "make sure L2MetadataArray assigns unoccupied way if available" 
This reverts commit 1857f36c1e6f2b2859c724eea6ae3cfb2618f81b.
 2015-11-21 10:35:40 -08:00
Howard Mao 158d1d870c do all the writes before doing the gets in GeneratorTest 2015-11-21 09:42:00 -08:00
Sagar Karandikar 65632c875a Merge branch 'master' into rocc-fpu-port 2015-11-21 02:24:38 -08:00
Howard Mao 9d50f37289 fix unused set issue for multiple L2 cache banks 2015-11-20 23:26:28 -08:00
Howard Mao 3c95afebc6 Shift set index for multi-bank configurations 
Prior to this commit, the L2 cache banks used the lower bits of the
block address as the set index. However, the lower bits are also used to
route addresses to different banks. As a result, in multi-bank
configurations, only a fraction of the sets in each bank could be
accessed. This commit fixes that problem by using the bits ahead of the
bank index as the set index, so that all sets in the cache can be
accessed.
 2015-11-20 23:24:57 -08:00
Howard Mao 55a85cc67a make sure wmask is passed for PutBlock in broadcast hub 2015-11-20 14:09:24 -08:00
Howard Mao 941b64cd62 make partial write-masking PutBlock constructor always set alloc bit 2015-11-20 13:34:07 -08:00
Howard Mao b0a06a77db fix a few Chisel3 compat issues 2015-11-20 13:33:15 -08:00
Howard Mao ad3b7fd0e1 adjust CacheFillTest configuration 2015-11-19 10:52:14 -08:00
Howard Mao 24f7b9f472 make sure L2MetadataArray assigns unoccupied way if available 2015-11-19 10:45:54 -08:00
Howard Mao 4806f72b08 add CacheFillTest to check L2 conflict misses 2015-11-19 00:16:28 -08:00
Howard Mao 49c6b1ad1c add CacheFillTest 2015-11-19 00:15:36 -08:00
Howard Mao 640544ea5a generalize test harness 2015-11-18 22:54:05 -08:00
Howard Mao f325874420 make sure timeout doesn't trigger spuriously on reset 2015-11-18 22:53:50 -08:00
Howard Mao 3514b6eb87 add some more useful configurations 2015-11-18 22:11:17 -08:00
Howard Mao 379d43d5f4 make MultiChannel routing more performant 2015-11-18 22:11:17 -08:00
Yunsup Lee ea8ba49805 improve memory system: specialize MultiChannel routing 2015-11-18 21:58:22 -08:00
Howard Mao 8bc90ab9bd separate out common functionality 2015-11-18 20:53:19 -08:00
Howard Mao e50c7ad306 add NASTI error assertions back in 2015-11-18 17:05:54 -08:00
Howard Mao e7e281275a implement MultiChannel routing in a specialized (and more performant) way 2015-11-18 17:01:52 -08:00
Yunsup Lee 94d2dd3053 Merge remote-tracking branch 'origin/master' into rocc-fpu-port 2015-11-16 23:29:25 -08:00
Henry Cook 2b977325e3 Make prefetch type available in a_type, issue probeInvalidates for putPrefetches 2015-11-16 23:26:13 -08:00
Andrew Waterman 5195a5b891 Remove IPI network 
This is now provided via MMIO.
 2015-11-16 21:53:14 -08:00
Andrew Waterman d426ecee78 Remove IPI network 
This is now provided via MMIO.
 2015-11-16 21:52:24 -08:00
Andrew Waterman 0f092b9b59 Remove IPI network 
This is now provided via MMIO.
 2015-11-16 21:51:43 -08:00