riscv/rocket-chip
1
0
Fork 0
Code Releases Activity
811 Commits 1 Branch 0 Tags 13 MiB
b64998ec05
Commit Graph

811 Commits

This Branch
This Branch
All Branches
Author SHA1 Message Date
Colin Schmidt
ba35712f08 Merge pull request #140 from ucb-bar/verilator 
Default to Chisel 3
 2016-06-15 16:25:07 -07:00
Palmer Dabbelt
68ba33369b Default to Chisel 3 
Now that we can test Chisel 3 on Travis, I think it's time to turn it on
for everyone else.
 2016-06-15 14:01:43 -07:00
Palmer Dabbelt
e617bb8aa8 Start testing Chisel 3 in Travis 
Now that we have verilator support we can start testing the Chisel 3
Verilog on Travis.  This disables Chisel 2 Travis tests because they're
too slow.
 2016-06-15 14:01:22 -07:00
Palmer Dabbelt
f6432395cb Allow the regressions to run more than once 2016-06-14 21:21:44 -07:00
Palmer Dabbelt
1525b4717e Install Verilator when building the emulator 
We need a fairly new version of Verilator, so I just added a rule to
download and install it on all systems.
 2016-06-14 21:21:43 -07:00
Colin Schmidt
1c2c9f8ed1 bump rocket to fix RoccExampleConfig 2016-06-14 21:21:06 -07:00
Palmer Dabbelt
571b5b2093 Prevent sbt from running multiple times in emulator 
If you have multi-target rules that don't have %s in them, make
interprets that as "run this recipe multiple times, once to produce each
target".  If you have %s in the rules, then make interprets it as "run
this recipe once to produce all targets".  We want the second one.
 2016-06-14 11:59:20 -07:00
Yunsup Lee
3ce8dbb6e5 fix make error mixing implicit and normal rules 2016-06-14 11:59:20 -07:00
Palmer Dabbelt
82cef6fa7b Make a TileLink to Smi converter availiable to users (#136) 
See the cooresponding uncore commit for details.
 2016-06-10 18:49:17 -07:00
Andrew Waterman
b79db89c03 Update breakpoint spec 2016-06-09 19:13:55 -07:00
Wesley W. Terpstra
70d92995df TestConfigs: add comparator config 2016-06-09 15:43:13 -07:00
Wesley W. Terpstra
3e51a8bb7a submodules: include new ComparatorTile 2016-06-09 15:43:13 -07:00
Howard Mao
1679cf4764 fix groundtest tilelink xacts 2016-06-09 15:42:44 -07:00
Andrew Waterman
9e86b9efc9 Add provisional breakpoint support 2016-06-08 22:34:19 -07:00
Scott Johnson
73ed4ea07b grammar 
English major I'm not, but my sister was and she says 'who' is correct here
 2016-06-08 22:34:14 -07:00
Howard Mao
65b62a9e5f unbreak the emulator 2016-06-08 15:38:39 -07:00
Howard Mao
40ab0a7960 fix TL width adapter and make it easier to switch inner data width 2016-06-08 15:38:39 -07:00
Howard Mao
a809a1712a make sure clocks and reset signals get intialized properly 2016-06-08 15:38:39 -07:00
Donggyu Kim
99b257316e replace emulator with verilator for chisel3 2016-06-08 02:43:54 -07:00
Howard Mao
08e53a00f0 bump cde for better match failure stack trace 2016-06-07 16:15:10 -07:00
Howard Mao
2cd897e240 Revert "include the unmatched field in CDEMatchError" 
This reverts commit ff2937a788.
 2016-06-07 16:13:01 -07:00
Howard Mao
8db27a36c4 fix Tile reset power on behavior 2016-06-07 11:06:38 -07:00
Palmer Dabbelt
e6c4372332 Fix "make run-asm-tests" for Chisel 3 
This was just a missing Makefrag-verilog dependency (the .d file).
 2016-06-06 21:36:55 -07:00
Andrew Waterman
2c17f828b6 bump chisel and rocket 2016-06-06 21:36:51 -07:00
Wesley W. Terpstra
5495705acf Configs: enable AHB for FPGAs 2016-06-06 21:36:09 -07:00
Wesley W. Terpstra
ef27cc3a33 RocketChip: handle atomics only if needed 2016-06-06 21:36:03 -07:00
Wesley W. Terpstra
3e0ec855cf RocketChip: add ahb mem interface 2016-06-06 21:35:59 -07:00
Wesley W. Terpstra
d2b505f2d2 RocketChip: rename mem to mem_axi in preparation for new bus type 2016-06-06 21:35:55 -07:00
Wesley W. Terpstra
2086c0d603 Configs: add a parameter to control the memory subsystem interface 2016-06-06 21:35:43 -07:00
Wesley W. Terpstra
2ddada1732 ahb: add mmio_ahb option 2016-06-06 21:35:39 -07:00
Wesley W. Terpstra
31f1dcaf84 ahb: rename mmio outputs to mmio_axi 2016-06-06 21:35:34 -07:00
Wesley W. Terpstra
7a24527448 ahb: make MMIO channels specifiy bus type (we will have more than one bridge) 2016-06-06 21:35:30 -07:00
Wesley W. Terpstra
f3a557b67b ahb: AHB parameters should be site specific 
Conflicts:
	src/main/scala/Configs.scala
 2016-06-06 21:35:24 -07:00
Howard Mao
172c4f25f4 bump groundtest and uncore 2016-06-06 17:45:30 -07:00
Howard Mao
ff2937a788 include the unmatched field in CDEMatchError 2016-06-06 11:23:20 -07:00
Andrew Waterman
d24c87f8ba Update PLIC/PRCI address map (#124) 2016-06-06 04:51:55 -07:00
Andrew Waterman
ece3ab9c3d Refactor AddrMap and its usage (#122) 2016-06-03 17:29:05 -07:00
Andrew Waterman
c8338ad809 Instantiate Debug Module (#119) 2016-06-02 10:53:41 -07:00
Andrew Waterman
1311e78d3f Add blocking D$ flush support 2016-05-31 19:28:41 -07:00
Howard Mao
50e3caef36 get rid of Zscale file I missed last time 2016-05-31 14:33:38 -07:00
Andrew Waterman
44a216038f Use more generic TileLinkWidthAdapter 2016-05-27 13:38:13 -07:00
Andrew Waterman
10f0e13c25 Use more parsimonious queue depths 2016-05-26 18:04:22 -07:00
Andrew Waterman
3cc236e9c4 By default, use same TileLink width everywhere 
When there's no L2 with a wide interface, having wider TileLink
is only disadvantageous.
 2016-05-26 18:04:01 -07:00
Wesley W. Terpstra
976d4d3184 ahb: AHB parameters should match TileLink parameters by default 
Closes #116
 2016-05-25 18:01:25 -07:00
Andrew Waterman
ec0d178010 Support M-mode-only implementations 2016-05-25 15:40:53 -07:00
Andrew Waterman
da105a5944 Don't allow travis to recurse through submodules 2016-05-25 13:27:49 -07:00
Wesley W. Terpstra
da566e7d6a build: use local sbt when building firrtl 2016-05-25 11:48:03 -07:00
Andrew Waterman
e82c080c3c Add blocking D$ 2016-05-25 11:09:50 -07:00
Andrew Waterman
a8462d3cfc bump chisel 2016-05-25 11:09:50 -07:00
Howard Mao
f52fc655a5 remove zscale 2016-05-19 09:43:15 -07:00