Andrew Waterman
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2b26082132
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use 1r1w ram for tags; merge tags & permissions
setting the dirty bit now allocates an MSHR (to reuse the existing datapath)
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2012-11-20 04:09:26 -08:00 |
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Andrew Waterman
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30038bda8a
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bypass stores to subsequent loads
since we handle subword stores as RMW operations, this occurs frequently
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2012-11-20 01:33:32 -08:00 |
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Yunsup Lee
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395e4e3dd6
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andrew'x fix for D$ corner case in writeback->abort->probe
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2012-11-18 03:11:06 -08:00 |
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Yunsup Lee
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81d711e892
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fix D$ bug; now D$ doesn't respond to prefetches
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2012-11-17 20:06:13 -08:00 |
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Andrew Waterman
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29bc361d6c
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remove global constants; disentangle hwacha a bit
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2012-11-17 17:24:08 -08:00 |
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Andrew Waterman
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e68b039133
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fix misc. D$ control bugs
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2012-11-17 06:47:27 -08:00 |
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Andrew Waterman
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dad7b71062
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provide cmd/addr with cache response
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2012-11-16 21:26:12 -08:00 |
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Andrew Waterman
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cb8ac73045
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provide store data with cache response
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2012-11-16 21:15:13 -08:00 |
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Andrew Waterman
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9e010beffe
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fix D$ refill bug
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2012-11-16 21:05:29 -08:00 |
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Andrew Waterman
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8dce89703a
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new D$ with better QoR and AMO pipelining
Vector unit is disabled because nack handling needs to be fixed.
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2012-11-16 02:39:33 -08:00 |
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Andrew Waterman
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6d10115b19
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fix D$ tag width
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2012-11-15 16:46:39 -08:00 |
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Yunsup Lee
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9a02298f6f
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andrew's fix for tlb lockup
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2012-11-06 23:52:58 -08:00 |
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Andrew Waterman
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4d1ca8ba3a
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remove more global consts; refactor DTLBs
D$ now contains DTLB. provide full VAddr with initial request.
VU now has its own DTLBs.
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2012-11-06 08:13:44 -08:00 |
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Andrew Waterman
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c5b93798fb
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factor out more global constants
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2012-11-05 23:52:32 -08:00 |
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Henry Cook
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88ac5af181
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Merged consts-as-traits
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2012-10-16 16:32:35 -07:00 |
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Andrew Waterman
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fc648d13a1
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remove old Mux1H; add implicit conversions
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2012-10-16 02:24:37 -07:00 |
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Henry Cook
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8970b635b2
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improvements to implicit RocketConfiguration parameter
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2012-10-15 16:29:49 -07:00 |
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Henry Cook
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9025d0610c
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first pass at configuration object passed as implicit parameter
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2012-10-07 22:37:29 -07:00 |
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Andrew Waterman
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ed8cc4a1cf
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eliminate D$ probe->WB critical path
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2012-10-04 09:05:14 -07:00 |
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Huy Vo
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e909093f37
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factoring out uncore into separate uncore repo
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2012-10-01 16:08:41 -07:00 |
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Henry Cook
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b9a9664de5
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uncore and rocket changes for new xact types
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2012-10-01 10:47:36 -07:00 |
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Andrew Waterman
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0f20771664
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rename queue to Queue
fixes build with case-insensitive file system
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2012-08-08 22:11:59 -07:00 |
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Andrew Waterman
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938effc053
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don't dequeue probe queue during reset
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2012-07-22 21:05:52 -07:00 |
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Yunsup Lee
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f633a55722
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fix dcache tag array size
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2012-07-16 22:19:03 -07:00 |
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Huy Vo
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fd95159837
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INPUT/OUTPUT orderring swapped
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2012-07-12 18:16:57 -07:00 |
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Andrew Waterman
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bac82762d3
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use only one (wide) tag ram for set assoc. caches
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2012-07-12 14:50:12 -07:00 |
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Andrew Waterman
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4e5f874266
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update to new chisel/hwacha
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2012-06-08 00:13:14 -07:00 |
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Huy Vo
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a99cebb483
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ioDecoupled -> FIFOIO, ioPipe -> PipeIO
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2012-06-06 18:22:56 -07:00 |
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Huy Vo
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04304fe788
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moving util out into Chisel standard library
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2012-06-06 12:51:26 -07:00 |
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Andrew Waterman
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7f6319047e
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update to new scala/chisel/Mem
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2012-06-06 02:47:22 -07:00 |
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Huy Vo
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7408c9ab69
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removing wires
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2012-05-24 10:42:39 -07:00 |
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Henry Cook
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87cbae2c8a
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Removed defunct ioDmem
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2012-05-07 17:31:39 -07:00 |
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Henry Cook
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622a801bb1
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Refactored cpu/cache interface to use nested bundles
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2012-05-02 11:54:28 -07:00 |
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Andrew Waterman
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c13d3e6f88
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fix probe tag read-modify-write atomicity violation
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2012-04-26 02:29:31 -07:00 |
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Henry Cook
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1ed89f1cab
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Fixed abort bug: removed uneeded state, added mshr guard on xact_abort.valid and xact_init.ready on same cycle
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2012-04-24 17:17:42 -07:00 |
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Henry Cook
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a39080d0b1
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Fixed abort bug: xact_abort.ready was not pinned high
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2012-04-24 17:16:40 -07:00 |
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Andrew Waterman
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fb4408b150
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fix AMO replay/coherence deadlock
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2012-04-15 22:56:02 -07:00 |
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Andrew Waterman
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724735f13f
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fix writeback bug
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2012-04-13 03:16:48 -07:00 |
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Andrew Waterman
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00d934cfac
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fix coherence bugs in cache
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2012-04-12 21:57:37 -07:00 |
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Andrew Waterman
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c0ec3794bf
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coherence mostly works now
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2012-04-10 02:22:45 -07:00 |
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Henry Cook
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3cdd166153
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Refactored coherence as member rather than trait. MI and MEI protocols.
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2012-04-10 00:09:58 -07:00 |
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Henry Cook
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0b4937f70f
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changed coherence message type names
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2012-04-09 23:29:31 -07:00 |
|
Henry Cook
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ed79ec98f7
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Refactored coherence better from uncore hub, better coherence function names
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2012-04-09 23:29:31 -07:00 |
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Yunsup Lee
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1cddd5de56
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fix amo locking up problem
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2012-03-20 02:16:28 -07:00 |
|
Yunsup Lee
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264732556f
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fixes to match verilog X semantics
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2012-03-19 03:10:00 -07:00 |
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Andrew Waterman
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cfca2d1411
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clean up cache interfaces; avoid reserved keywords
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2012-03-16 00:44:16 -07:00 |
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Andrew Waterman
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820884c7e6
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fix probes for smaller cache sizes
address bits (pgidx_bits-1,taglsb) were omitted from tag checks.
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2012-03-15 23:08:30 -07:00 |
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Andrew Waterman
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4684171ac6
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fix fence.i for associative caches
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2012-03-15 21:23:21 -07:00 |
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Andrew Waterman
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7dde7099d2
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use broadcast hub and coherent HTIF
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2012-03-14 16:44:35 -07:00 |
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Andrew Waterman
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1492457df5
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add probe replies to HTIF
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2012-03-13 16:56:47 -07:00 |
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