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Commit Graph

4747 Commits

Author SHA1 Message Date
Andrew Waterman
9f89c812b7 fix HTIF memory size reporting 2013-01-29 23:08:25 -08:00
Yunsup Lee
a0bd0adeb2 change write/read port ordering for vlsi_mem_gen script 2013-01-29 21:32:42 -08:00
Andrew Waterman
66eb3720a4 fix SRAM semantics bug in HellaFlowQueue 2013-01-29 21:16:42 -08:00
Yunsup Lee
60bd3a6413 Revert "shuffled FPU control logic around to make functional unit retiming work better"
This reverts commit 20dd308067b143adff4913fc7ac710a393ca1d86.
2013-01-29 19:34:55 -08:00
Andrew Waterman
6275e009f8 fix HellaQueue deq.valid signal 2013-01-28 20:57:43 -08:00
Andrew Waterman
45d8066f45 add HellaQueue, an SRAM-based queue 2013-01-28 20:54:25 -08:00
Andrew Waterman
37c67f1d87 pipeline reset to the vector unit 2013-01-28 17:56:32 -08:00
Rimas Avizienis
f2df6147df shuffled FPU control logic around to make functional unit retiming work better 2013-01-28 17:17:09 -08:00
Henry Cook
f5729c9f25 removed ack_required field from grant messages 2013-01-28 16:44:17 -08:00
Henry Cook
47a632cc59 added support for voluntary wbs over the release network 2013-01-28 16:39:45 -08:00
Henry Cook
8cbd316b5e Merge branch 'ready-sig-fix' into pin-cleanup 2013-01-27 23:04:58 -08:00
Henry Cook
931cffa749 ready signal fix 2013-01-27 23:04:35 -08:00
Henry Cook
83c207c852 pin cleanup in htif 2013-01-27 12:00:28 -08:00
Henry Cook
1134bbf1a4 cleanup disconnected io pins (overwritten network headers) 2013-01-27 11:59:17 -08:00
Henry Cook
409b549d3c actually cleared up tile ios 2013-01-27 11:27:09 -08:00
Henry Cook
696dd102eb cleans up unconnected tile io pins (networking headers overwritten at top level) 2013-01-27 10:59:41 -08:00
Andrew Waterman
dbb61306f0 randomize coreid mapping 2013-01-26 16:13:14 -08:00
Andrew Waterman
4077b22929 include fesvr as a library; improve harnesses 2013-01-24 23:57:23 -08:00
Andrew Waterman
c890099e09 add System Control Register space to HTIF 2013-01-24 23:41:24 -08:00
Andrew Waterman
1945fa898b make external clock divider programmable 2013-01-24 23:40:47 -08:00
Andrew Waterman
575bd3445a re-generalize scoreboard 2013-01-24 18:00:39 -08:00
Andrew Waterman
1fbc20450e don't allow simultaneous reads and writes to the tag ram 2013-01-24 17:55:00 -08:00
Andrew Waterman
37ee843b2c don't use reset combinationally 2013-01-24 17:55:00 -08:00
Andrew Waterman
bb6fbddf1f don't probe the mshr file to inquire about refills 2013-01-24 17:54:59 -08:00
Andrew Waterman
5b9f938263 correctly sign-extend badvaddr, epc, and ebase 2013-01-24 17:54:59 -08:00
Rimas Avizienis
63060bc0a8 minor tweaks for eos18 tapeout (SRAM r/w port ordering, etc) 2013-01-23 19:27:53 -08:00
Yunsup Lee
f37b9d9a7d fix dramsim2 memory model to wrap around
- there was a problem when the I$ speculatively fetched an instruction from an illegal address
2013-01-23 01:40:15 -08:00
Yunsup Lee
217898c7d0 emulator depends on source files in src directory 2013-01-23 01:39:47 -08:00
Yunsup Lee
516a64f576 commit vec=true 2013-01-22 20:24:33 -08:00
Henry Cook
b5ccdab514 changed val names in hub to match new tilelink names 2013-01-22 20:09:21 -08:00
Henry Cook
bb5c465bb3 Switched back to old, better-tested hub on master 2013-01-22 19:57:31 -08:00
Henry Cook
5b82d72eb7 New TileLink bundle names 2013-01-21 17:19:07 -08:00
Henry Cook
6b00e7ff74 New TileLink bundle names 2013-01-21 17:18:23 -08:00
Henry Cook
c211d74e95 New TileLink names 2013-01-21 17:17:26 -08:00
Henry Cook
72bba81a76 now using single-ported coherence master 2013-01-16 23:58:24 -08:00
Henry Cook
fb2644760f single-ported coherence master 2013-01-16 23:57:35 -08:00
Henry Cook
e33648532b Refactored packet headers/payloads 2013-01-15 15:57:06 -08:00
Henry Cook
f7c0152409 Refactored packet headers/payloads 2013-01-15 15:52:47 -08:00
Henry Cook
a2fa3fd04d Refactored packet headers/payloads 2013-01-15 15:50:37 -08:00
Henry Cook
a922b60152 Merge branch 'master' of github.com:ucb-bar/reference-chip into network-refactor 2013-01-07 14:23:49 -08:00
Henry Cook
f2cef8d8d2 new IO names, set val/rdy low for unused network inputs, add src/dst setting for tiles, incoherent sig out of tilelink, bump chisel/rocket/uncore 2013-01-07 14:19:55 -08:00
Henry Cook
f836bd93e1 Bugfix in crossbar ready sigs, added adapter for old hub, removed incoherent sig from tilelink 2013-01-07 14:01:39 -08:00
Henry Cook
418e3fdf50 Bugfix in crossbar ready sigs, added adapter for old hub, removed incoherent sig from tilelink 2013-01-07 13:57:48 -08:00
Henry Cook
e1225c5114 standardize IO naming convention 2013-01-07 13:41:36 -08:00
Henry Cook
261e14f831 Refactored uncore conf 2013-01-07 13:41:36 -08:00
Andrew Waterman
bbd010750f add missing #include 2013-01-06 04:53:40 -08:00
Andrew Waterman
fd727bf8aa add some of the zedboard fpga infrastructure
you can elaborate the RTL in fpga/build/vcs-sim-rtl, but there's no harness
for VCS simulation yet.
2013-01-06 03:58:10 -08:00
Andrew Waterman
03df2c3766 update .gitignores 2013-01-06 03:58:10 -08:00
Andrew Waterman
78868f6075 add config option to trade mul/div area for speed 2013-01-06 03:47:17 -08:00
Andrew Waterman
ce9f4881d2 remove broken multiplier early out 2013-01-06 03:47:00 -08:00