Andrew Waterman
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9f89c812b7
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fix HTIF memory size reporting
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2013-01-29 23:08:25 -08:00 |
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Yunsup Lee
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a0bd0adeb2
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change write/read port ordering for vlsi_mem_gen script
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2013-01-29 21:32:42 -08:00 |
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Andrew Waterman
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66eb3720a4
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fix SRAM semantics bug in HellaFlowQueue
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2013-01-29 21:16:42 -08:00 |
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Yunsup Lee
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60bd3a6413
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Revert "shuffled FPU control logic around to make functional unit retiming work better"
This reverts commit 20dd308067b143adff4913fc7ac710a393ca1d86.
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2013-01-29 19:34:55 -08:00 |
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Andrew Waterman
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6275e009f8
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fix HellaQueue deq.valid signal
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2013-01-28 20:57:43 -08:00 |
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Andrew Waterman
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45d8066f45
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add HellaQueue, an SRAM-based queue
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2013-01-28 20:54:25 -08:00 |
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Andrew Waterman
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37c67f1d87
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pipeline reset to the vector unit
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2013-01-28 17:56:32 -08:00 |
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Rimas Avizienis
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f2df6147df
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shuffled FPU control logic around to make functional unit retiming work better
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2013-01-28 17:17:09 -08:00 |
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Henry Cook
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f5729c9f25
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removed ack_required field from grant messages
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2013-01-28 16:44:17 -08:00 |
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Henry Cook
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47a632cc59
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added support for voluntary wbs over the release network
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2013-01-28 16:39:45 -08:00 |
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Henry Cook
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8cbd316b5e
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Merge branch 'ready-sig-fix' into pin-cleanup
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2013-01-27 23:04:58 -08:00 |
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Henry Cook
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931cffa749
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ready signal fix
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2013-01-27 23:04:35 -08:00 |
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Henry Cook
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83c207c852
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pin cleanup in htif
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2013-01-27 12:00:28 -08:00 |
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Henry Cook
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1134bbf1a4
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cleanup disconnected io pins (overwritten network headers)
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2013-01-27 11:59:17 -08:00 |
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Henry Cook
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409b549d3c
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actually cleared up tile ios
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2013-01-27 11:27:09 -08:00 |
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Henry Cook
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696dd102eb
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cleans up unconnected tile io pins (networking headers overwritten at top level)
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2013-01-27 10:59:41 -08:00 |
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Andrew Waterman
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dbb61306f0
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randomize coreid mapping
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2013-01-26 16:13:14 -08:00 |
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Andrew Waterman
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4077b22929
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include fesvr as a library; improve harnesses
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2013-01-24 23:57:23 -08:00 |
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Andrew Waterman
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c890099e09
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add System Control Register space to HTIF
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2013-01-24 23:41:24 -08:00 |
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Andrew Waterman
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1945fa898b
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make external clock divider programmable
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2013-01-24 23:40:47 -08:00 |
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Andrew Waterman
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575bd3445a
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re-generalize scoreboard
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2013-01-24 18:00:39 -08:00 |
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Andrew Waterman
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1fbc20450e
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don't allow simultaneous reads and writes to the tag ram
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2013-01-24 17:55:00 -08:00 |
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Andrew Waterman
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37ee843b2c
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don't use reset combinationally
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2013-01-24 17:55:00 -08:00 |
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Andrew Waterman
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bb6fbddf1f
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don't probe the mshr file to inquire about refills
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2013-01-24 17:54:59 -08:00 |
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Andrew Waterman
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5b9f938263
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correctly sign-extend badvaddr, epc, and ebase
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2013-01-24 17:54:59 -08:00 |
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Rimas Avizienis
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63060bc0a8
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minor tweaks for eos18 tapeout (SRAM r/w port ordering, etc)
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2013-01-23 19:27:53 -08:00 |
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Yunsup Lee
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f37b9d9a7d
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fix dramsim2 memory model to wrap around
- there was a problem when the I$ speculatively fetched an instruction from an illegal address
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2013-01-23 01:40:15 -08:00 |
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Yunsup Lee
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217898c7d0
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emulator depends on source files in src directory
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2013-01-23 01:39:47 -08:00 |
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Yunsup Lee
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516a64f576
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commit vec=true
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2013-01-22 20:24:33 -08:00 |
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Henry Cook
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b5ccdab514
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changed val names in hub to match new tilelink names
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2013-01-22 20:09:21 -08:00 |
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Henry Cook
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bb5c465bb3
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Switched back to old, better-tested hub on master
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2013-01-22 19:57:31 -08:00 |
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Henry Cook
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5b82d72eb7
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New TileLink bundle names
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2013-01-21 17:19:07 -08:00 |
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Henry Cook
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6b00e7ff74
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New TileLink bundle names
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2013-01-21 17:18:23 -08:00 |
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Henry Cook
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c211d74e95
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New TileLink names
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2013-01-21 17:17:26 -08:00 |
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Henry Cook
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72bba81a76
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now using single-ported coherence master
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2013-01-16 23:58:24 -08:00 |
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Henry Cook
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fb2644760f
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single-ported coherence master
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2013-01-16 23:57:35 -08:00 |
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Henry Cook
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e33648532b
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Refactored packet headers/payloads
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2013-01-15 15:57:06 -08:00 |
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Henry Cook
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f7c0152409
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Refactored packet headers/payloads
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2013-01-15 15:52:47 -08:00 |
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Henry Cook
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a2fa3fd04d
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Refactored packet headers/payloads
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2013-01-15 15:50:37 -08:00 |
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Henry Cook
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a922b60152
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Merge branch 'master' of github.com:ucb-bar/reference-chip into network-refactor
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2013-01-07 14:23:49 -08:00 |
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Henry Cook
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f2cef8d8d2
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new IO names, set val/rdy low for unused network inputs, add src/dst setting for tiles, incoherent sig out of tilelink, bump chisel/rocket/uncore
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2013-01-07 14:19:55 -08:00 |
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Henry Cook
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f836bd93e1
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Bugfix in crossbar ready sigs, added adapter for old hub, removed incoherent sig from tilelink
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2013-01-07 14:01:39 -08:00 |
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Henry Cook
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418e3fdf50
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Bugfix in crossbar ready sigs, added adapter for old hub, removed incoherent sig from tilelink
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2013-01-07 13:57:48 -08:00 |
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Henry Cook
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e1225c5114
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standardize IO naming convention
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2013-01-07 13:41:36 -08:00 |
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Henry Cook
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261e14f831
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Refactored uncore conf
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2013-01-07 13:41:36 -08:00 |
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Andrew Waterman
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bbd010750f
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add missing #include
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2013-01-06 04:53:40 -08:00 |
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Andrew Waterman
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fd727bf8aa
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add some of the zedboard fpga infrastructure
you can elaborate the RTL in fpga/build/vcs-sim-rtl, but there's no harness
for VCS simulation yet.
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2013-01-06 03:58:10 -08:00 |
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Andrew Waterman
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03df2c3766
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update .gitignores
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2013-01-06 03:58:10 -08:00 |
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Andrew Waterman
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78868f6075
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add config option to trade mul/div area for speed
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2013-01-06 03:47:17 -08:00 |
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Andrew Waterman
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ce9f4881d2
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remove broken multiplier early out
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2013-01-06 03:47:00 -08:00 |
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