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Commit Graph

5474 Commits

Author SHA1 Message Date
a749326deb Add cover points to registers (#1208) 2018-01-24 21:37:24 -08:00
94d2edceb9 Merge pull request #1205 from freechipsproject/fpu-cover
Add some covers for VM and FPU
2018-01-23 18:49:45 -08:00
7a0252fdfc Add some covers for FPU structural hazards 2018-01-23 16:32:03 -08:00
a2ca82f92c Add VM covers 2018-01-23 16:13:35 -08:00
dcda98dcaf Disable coverage collection for testbench related verilog files (#1204) 2018-01-22 16:40:38 -08:00
c32150b994 ResetCatchAndSync: work also in the context of a RawModule (#1202) 2018-01-19 19:45:52 -08:00
f6f5606f8e diplomacy: run user instantiate() method after nodes are initialized (#1198) 2018-01-18 14:57:47 -08:00
5cc1411e14 Merge pull request #1199 from freechipsproject/require-messages
rocket: add address to tlb permissions require msgs
2018-01-18 14:53:25 -08:00
bf5dd6dac3 Replace Parameters in cover with globally setable implementation (#1200)
This change is made in anticipation of a proper coverage library
2018-01-18 14:45:36 -08:00
24c1235500 rocket: add address to tlb permissions require msgs 2018-01-18 10:31:51 -08:00
5854fb5f7c SourceShrinker improvements (#1197)
* SourceShrinker: preserve FIFO guarantees of slaves

* tilelink: document that Releases can use TtoT, BtoB, and NtoN

TtoT is needed for write-through caches.
2018-01-17 18:02:19 -08:00
338e453a91 JTAG: Use new withClock way of overriding clocks (#1072)
* JTAG: Use new withClock way of overriding clocks

the override clock way is deprecated

* JTAG: use withClock instead of override clock

* JTAG:  extend Module for ClockedCounter

* JTAG: Don't use deprecated clock constructs

* JTAG: Remove another override_clock

* Rename "NegativeEdgeLatch"

because it's not a latch, it's just a register on the negative edge of the clock.

* Use the appropriately named NegEdgeReg

* JTAG: Rename another NegativeEdgeLatch
2018-01-17 13:59:05 -08:00
80ca018e3a Add cover points for BusErrorUnit (#1193) 2018-01-15 18:00:29 -08:00
6c6afc5bc9 Merge pull request #1191 from edcote/patch-2
remove string type ambiguity in header
2018-01-15 13:33:27 -08:00
ff11673a9c remove string type ambiguity in header
I ran into a compilation issue.

This link explains the problem well: https://stackoverflow.com/a/5499222/3736700

For example, in a header file, it is generally not considered a good idea to put the line using namespace std; (or to use any namespace, for that matter) because it can cause names in files that include that header to become ambiguous. In this setup, you would just #include <string> in the header, then use std::string to refer to the string type.
2018-01-13 13:29:22 -08:00
8799508b1f Merge pull request #1179 from freechipsproject/refactored_rbb
Add Debug tests to Regressions
2018-01-12 10:34:48 -08:00
b8219425d8 Fix spelling and capitalization in README.md (#1182) 2018-01-10 15:52:07 -08:00
5fe0bb0d6a Merge remote-tracking branch 'origin/master' into refactored_rbb 2018-01-09 21:34:14 -08:00
f5211765e9 Merge pull request #1177 from freechipsproject/dont-touch-2
Make more use of chisel3.experimental.DontTouch
2018-01-09 15:13:55 -08:00
c152962642 Dual-port RAM replaced with single-port RAM for tag_array in HellaCache (#1181)
In accordance with https://github.com/freechipsproject/chisel3/issues/752
2018-01-09 13:06:43 -08:00
15c54b1c5a tile: intSinkNode belongs in HasExternalInterrupts 2018-01-08 19:38:10 -08:00
11e5b620f8 tile: disable more monitors on slave port 2018-01-08 18:42:25 -08:00
5075a93e6c util: dontTouch work-around for zero width aggregates 2018-01-08 15:58:28 -08:00
7fc8337cdb Merge pull request #1180 from freechipsproject/addrwregdesc
Allow rwReg to pass name and description to RegField for documentation.
2018-01-08 09:44:44 -08:00
a530646d15 Merge remote-tracking branch 'origin/master' into refactored_rbb 2018-01-08 09:11:27 -08:00
4fd4ae38e3 Merge pull request #1176 from freechipsproject/fix-tl-port
Fix TL MMIO port
2018-01-05 20:37:44 -08:00
3525489fff Merge pull request #1174 from freechipsproject/error-device-tracked
Claim that ErrorDevice is TRACKED
2018-01-05 17:17:22 -08:00
427b6c9ab8 Emulator: Update it to allow some hard-coded Verilog PlusArgs 2018-01-05 17:08:21 -08:00
76c5fd0c0c travis: Use newer infrastructure, but require sudo for additional disk space.
This is because as of Dec 12, 2017, Travis changed their container images and seem
to give slightly less disk space. Using a sudo image gives more disk space.
2018-01-05 17:08:21 -08:00
e6661a6982 Debug regressions: use a plusarg to enable remote bitbang. 2018-01-05 17:08:21 -08:00
b643f3dca6 debug regressions: some whitespace and null ptr cleanup 2018-01-05 17:08:21 -08:00
96dd5d8c38 Emulator example clarifications
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@gmail.com>
2018-01-05 17:08:21 -08:00
7ae6bf7611 Arguments clarification, add examples
This clarifies and provides consistent for the command line arguments
usage text.

This adds a set of examples for running the rocket-chip emulator.

Signed-off-by: Schuyler Eldridge <schuyler.eldridge@gmail.com>
2018-01-05 17:08:21 -08:00
1aa87f6578 Make emulator.cc understand HTIF arguments
This, with riscv-fesvr modifications, enables the rocket-chip emulator
to understand (and error out) if a command line argument that will
eventually be consumed by HTIF looks bad and can error out quickly.
This relies on modifications to risc-fesvr to support getopt and the
exposure of what HTIF arguments exist via the `htif.h` header.
2018-01-05 17:08:21 -08:00
3ead9a5d2d Move check on VCS inside riscv-fesvr
This removes the necessary preprocessing of riscv-fesvr arguments to
avoid situations where riscv-fesvr thinks that an argument is the
binary. Support for this is rolled into riscv-fesvr.
2018-01-05 17:08:21 -08:00
a97add954a Async Reg: Doesn't properly reset for Verilator. 2018-01-05 17:08:21 -08:00
9df3604007 emulator: No reason not to emit waveforms during reset 2018-01-05 17:08:21 -08:00
024cd52c44 debug: attempt to make the simulation deterministic by not returning until connection is made and command is receieved 2018-01-05 17:08:21 -08:00
1d3fa07c44 debug: print failures when debug tests fail, so we can see why it is failing on Travis
Cleanups, and print out log names ASAP.

Factor out gdbserver common invocation into GDBSERVER (fixing
--print-failtures).
Add --print-log-names to that command so the logfiles can be inspected
while the simulation is still running.
`RISCV=... cmd` is more idiomatic than `export RISCV=... && cmd`
2018-01-05 17:08:15 -08:00
8425086f98 Allow rwReg to pass name and description to RegField for documentation. 2018-01-05 16:59:58 -08:00
9b234216f0 debug: Install pexpect package for travis regressions 2018-01-05 16:13:19 -08:00
1549ecfb3f debug: explicitly clone riscv-tests to get to gdbserver.py 2018-01-05 16:13:11 -08:00
3de9a04272 debug regression: until XLEN fix is merged into riscv-tests, have to explicitly state the XLEN 2018-01-05 16:10:13 -08:00
bd5fe5d22e Debug regression: have to say something about memory in order to run a simple test 2018-01-05 16:10:13 -08:00
5df55d7911 debug regression: bump riscv-tools for riscv-tests fixes 2018-01-05 16:10:13 -08:00
593839e0d5 Debug: add Debug regression to Travis regressions. 2018-01-05 16:10:00 -08:00
4449dd0baa Debug regressions: Add necessary config scripts 2018-01-05 16:03:59 -08:00
e82328336e Add in a SimJTAG to connect to OpenOCD's remote-bitbang interface.
This is simpler than JTAGVPI and is supported better by Verilor.
It is also the same thing Spike uses.
2018-01-05 16:02:52 -08:00
b77b93b0b4 util: dontTouchPortsExcept 2018-01-05 14:06:00 -08:00
000cde2f8a Make ErrorDevice UNCACHEABLE instead of UNCACHED
...even though it still supports Acquire.  This avoids needing to flush
the D$ on FENCE.I because of the presence of the ErrorDevice.
2018-01-05 14:00:42 -08:00