riscv/rocket-chip
1
0
Fork 0
Code Releases Activity
5,474 Commits 1 Branch 0 Tags 13 MiB
a749326deb
Commit Graph

5474 Commits

This Branch
This Branch
All Branches
Author SHA1 Message Date
Wesley W. Terpstra
1902ba063a Filter: can claim to be out-of-order when you are not 2017-11-14 15:09:09 -08:00
Wesley W. Terpstra
58a93e2100 AXI4SRAM: handy helper object 2017-11-14 15:09:09 -08:00
Wesley W. Terpstra
353ddffc11 RAMModel: add a convenience object 2017-11-14 15:09:09 -08:00
Wesley W. Terpstra
7cfb69e2d5 Queue: silence some warnings 2017-11-14 15:09:09 -08:00
Wesley W. Terpstra
147fad6387
Fix AXI4 FIFO ordering for masters with early source reuse (#1108) 
* TLToAXI4: fix WaR for single-source FIFO masters
* TLToAXI4: fix potential counter overflow => WaR hazard

If you have a FIFO master with 2^n-1 sources that performs early
source re-use, the old code could potentially break FIFO order.
 2017-11-13 20:32:09 -08:00
Henry Cook
7098ebf439
rocket: fix itim GetPropertyByHartId (#1109) 
needs to use RocketTileParams.hartid instead of zipWithIndex
 2017-11-13 19:25:20 -08:00
Andrew Waterman
b317735319
Merge pull request #1106 from freechipsproject/bump-tools 
bump tools for .align 2 fix in riscv-tests
 2017-11-11 23:36:28 -08:00
Andrew Waterman
f0a0687589 bump tools for .align 2 fix in riscv-tests 2017-11-11 19:13:59 -08:00
Wesley W. Terpstra
0cfa801bfc
coreplex: allow MMIO to be misaligned (#1103) 2017-11-10 15:12:28 -08:00
Wesley W. Terpstra
a061b16ee3
coreplex: fix typo (#1104) 2017-11-10 15:11:56 -08:00
Andrew Waterman
35d377d122
Merge pull request #1100 from freechipsproject/disable-local-amos 
Provide option to support AMOs only on I/O, not DTIM/D$
 2017-11-09 21:20:55 -08:00
Andrew Waterman
4ebca73d59 Provide option to support AMOs only on I/O, not DTIM/D$ 2017-11-09 17:45:53 -08:00
Andrew Waterman
efdb418559
Merge pull request #1098 from freechipsproject/frontend 
Frontend improvements
 2017-11-09 17:44:38 -08:00
Wesley W. Terpstra
50ce3f5086
Merge pull request #1097 from freechipsproject/itim-error 
More ITIM error-handling improvements
 2017-11-09 00:17:48 -08:00
Andrew Waterman
d0c6cbba6b Improve frontend branch prediction 
- Put correctness responsibility on Frontend, not IBuf, for improved
  separation of concerns.  Frontend must detect case that the BTB
  predicts a taken branch in the middle of an instruction.

- Pass BTB information down pipeline unconditionally, fixing case that
  screws up the branch history when the BTB misses and the instruction
  is misaligned.

- Remove jumpInFrontend option; it's now unconditional.

- Default to one-bit counters in the BHT.  For tiny BHTs like these, it's
  more resource efficient to have a larger index space than to have
  hysteresis.
 2017-11-09 00:00:56 -08:00
Andrew Waterman
bb9d8264e2 "Correct" ITIM uncorrectable errors 
This permits forward progress when a core wants to handle its own
uncorrectable ITIM errors.  Previously, another core had to do it.
 2017-11-08 22:15:03 -08:00
Andrew Waterman
5c1b34d854 Don't report a TL error if overwriting a whole ITIM word 2017-11-08 22:15:03 -08:00
Andrew Waterman
9b16d25861 Fix reporting of ITIM error addresses on slave-port accesses 2017-11-08 22:15:03 -08:00
Palmer Dabbelt
9441c29d92
Merge pull request #1096 from freechipsproject/tools 
Bump riscv-tools, for a new toolchain release
 2017-11-08 17:20:28 -08:00
Wesley W. Terpstra
b59880fe8e
Fragmenter: add an option for earlyAck only on PutFulls (#1095) 
Fragmenter: add a third case for earlyAck (PutFulls only)

It seems quite common to have a device that is backed by ECC. When
performing a multibeat PutPartial, these devices can exhibit their
first error on the last beat (if it had an incomplete write mask
for that beat, which required read-write-modifying corrupted data).

Generally, these devices have ECC granularity <= the bus width. In
those cases, if you send a PutFull, the first beat carries the
error value for the whole burst. Consider:
  If the PutFull was below the granularity, it was a single beat.
  If the PutFull was multi-beat, it exceeds the granularity.

Therefore, an important variation on the earlyAck optimization is
the case where only PutFulls receive an earlyAck.
 2017-11-08 15:31:19 -08:00
Palmer Dabbelt
8700728a35 Bump riscv-tools, for a new toolchain release 2017-11-08 14:26:55 -08:00
Andrew Waterman
4514adb77c
Merge pull request #1093 from freechipsproject/local-error-interrupt 
generate local interrupts on bus/ecc errors
 2017-11-07 14:19:53 -08:00
Henry Cook
d096fd206b
coreplex: WithStatelessBridge => WithIncoherentTiles (#1092) 2017-11-07 13:47:56 -08:00
Andrew Waterman
34f38b0fb1 Don't permit vectoring of high interrupts 
Send them to the base of the vector to obviate an adder
 2017-11-07 01:59:30 -08:00
Andrew Waterman
6176b348dc Invalidate TL error bit in D$ once progress is made 2017-11-07 00:52:18 -08:00
Andrew Waterman
d8d4504995 Provide separate masks for local & global BusErrorUnit interrupts 2017-11-06 18:03:59 -08:00
Andrew Waterman
be3a3e0187 Generate local interrupt #128 on bus errors 
It doesn't have a correpsonding bit in mip/mie, so it isn't individually
maskable, nor is it delegable.
 2017-11-06 18:03:59 -08:00
Andrew Waterman
ac096a89e7 Make BusErrorUnit support 32-bit stores 
Otherwise it isn't too useful for RV32!
 2017-11-06 18:03:59 -08:00
Andrew Waterman
6357db0b12 Expose BusErrorUnit non-diplomatically for use as local interrupt 2017-11-06 18:03:59 -08:00
Andrew Waterman
bdda2cb145
Merge pull request #1089 from freechipsproject/aswaterman-patch-1 
Don't emit PTW covers when !usingVM
 2017-11-06 18:03:36 -08:00
Wesley W. Terpstra
1f5fb5d643
Merge pull request #1091 from freechipsproject/atomic-automata-errors 
tilelink: AtomicAutomata should OR the Get error with the Put error
 2017-11-06 13:58:02 -08:00
Andrew Waterman
95d00b13cc Report ITIM slave port errors to BusErrorUnit 2017-11-06 12:39:17 -08:00
Andrew Waterman
c84848afa6 Report ITIM uncorrectable errors over D-channel 2017-11-06 12:32:45 -08:00
Wesley W. Terpstra
7cc7cd5992 tilelink: AtomicAutomata; add errors to the unit test 2017-11-06 12:05:44 -08:00
Wesley W. Terpstra
88234ead0d tilelink: generalize ErrorEvaluator to more than just address patterns 2017-11-06 11:53:09 -08:00
Wesley W. Terpstra
25ea7fa852 tilelink: AtomicAutomata should OR the Get error with the Put error 2017-11-06 11:31:23 -08:00
Wesley W. Terpstra
dcf67b49fa
BusBypass: only stall A once the last beat is accepted (#1090) 
When switching ports, the bypass stalls new messages until all
outstanding messages have received their responses. However, this
stall must NOT stop the remaining beats of a partially sent request.
 2017-11-06 11:13:15 -08:00
Andrew Waterman
989eeb78f9 Prevent some unnecessary pipeline replays 2017-11-06 11:04:06 -08:00
Andrew Waterman
c8bc487ab8 Use pseudo-LRU policy in BTB 
FIFO falls on its face if the working set doesn't fit in the BTB.
 2017-11-03 16:27:04 -07:00
Andrew Waterman
f859da85ff Disable covers that don't apply to DTIM 2017-11-03 15:38:13 -07:00
Andrew Waterman
d6ede818ee DTIM doesn't accept grants 2017-11-03 15:37:48 -07:00
Andrew Waterman
7bef935d2a
Don't emit PTW covers when !usingVM 2017-11-03 15:03:27 -07:00
Megan Wachs
7e75d63ba6
debug: Bump riscv-tools for riscv-tests timeout fix (#1086) 
* debug: Bump riscv-tools for riscv-tests timeout fix

* bump riscv-tools now that is merged into master
 2017-11-02 14:05:02 -07:00
Wesley W. Terpstra
16116991e7
Fix stateless caching (#1084) 
* tilelink: ToAXI4 should format it's error message

* WithStatelessBridge: mark the memory bus incoherent and cacheable

... and hope that the user doesn't put more than one master down.
 2017-11-01 11:05:56 -07:00
Wesley W. Terpstra
4ccdbecb63
Async covers (#1085) 
* cover: support covering cross-product of ready-valid

* tilelink: AsyncCrossing now has covers for all flow control logic
 2017-11-01 11:03:45 -07:00
Andrew Waterman
a2b80100e2 Make PseudoLRU policy support non-power-of-2 sizes 2017-11-01 01:47:23 -07:00
Richard Xia
9e77045213
Merge pull request #1083 from freechipsproject/bump-riscv-tools 
Bump riscv-tools.
 2017-10-31 20:55:10 -07:00
Richard Xia
f6ec7b765e Bump riscv-tools. 2017-10-31 17:42:05 -07:00
Wesley W. Terpstra
84145959e1
tilelink: fix error fragmentation from multibeat to multibeat (#1082) 
Unfortunately, dLast is not actually correct for AccessAckData.
dFragnum is 0 for all the subbeats in the multibeat=>multibeat case.
 2017-10-31 17:34:46 -07:00
Wesley W. Terpstra
8ec06151b0
interrupts: Crossing should use asynchronously reset registers (#1080) 
Otherwise you can get interrupts wedged high from a domain that has
not yet been clocked/powered up.
 2017-10-31 16:29:06 -07:00