Colin Schmidt
a43ad522dc
add clock override to tile constructor ( #42 )
...
useful to have upstream so that tape-outs can construct
rocket-chip to have cores on different clocks without
forking rocket
2016-07-21 17:56:52 -07:00
Ben Keller
c069e66056
Modify the RoCC interface to include status in the command queue. ( #41 )
...
This addresses a bug in which changes in mstatus could
propagate to RoCCs before their time. Existing RoCCs that use
the status port will need to be modified to match this change.
This addresses the first half of #40 .
2016-07-18 17:40:50 -07:00
Howard Mao
2723b2f515
fix issues in SimpleHellaCacheIF and document the changes
2016-07-18 17:02:47 -07:00
Howard Mao
40a146f625
HellaCacheArbiter passes through if n == 1
2016-07-18 17:01:29 -07:00
mwachs5
cff8de9814
Use new Mul/Div parameters vs UseFastMulDiv ( #48 )
...
* Use new Mul/Div parameters vs UseFastMulDiv
* Rename MulDivUnroll to MulUnroll
2016-07-15 15:41:20 -07:00
Andrew Waterman
7cf44f9b25
clean up WideCounter implementation
2016-07-15 00:51:01 -07:00
Andrew Waterman
d78f1aacd0
Clean up some zero-width wire cases using UInt.extract
2016-07-14 22:08:01 -07:00
Andrew Waterman
da512d4230
Explicitly discard BTB index LSBs
2016-07-14 17:10:27 -07:00
Andrew Waterman
e6aab368a4
Replace ICacheBufferWays parameter with I$ constructor argument
2016-07-14 12:38:54 -07:00
Andrew Waterman
3d0b92afd7
Misc code cleanup
2016-07-14 12:09:34 -07:00
Andrew Waterman
b8884e8143
Simplify frontend virtual address extension code
2016-07-14 12:05:09 -07:00
Andrew Waterman
1699622730
Don't speculatively refill I$ in uncacheable regions
2016-07-09 01:10:58 -07:00
Howard Mao
f7b392306e
make sure SimpleHellaCacheIF can work with blocking DCache
2016-07-07 18:59:23 -07:00
Andrew Waterman
3d8939d3c3
Set misa.base = 1 for RV32
2016-07-07 15:32:21 -07:00
Andrew Waterman
2455a806af
Make WFI instruction respect mie CSR setting
2016-07-07 15:31:17 -07:00
Andrew Waterman
35a983275e
Guarantee one-hotness of BTB entries
2016-07-06 15:58:01 -07:00
Andrew Waterman
c0e6ecebfc
Fix BTB perf bug
...
In rare cases, it would replace into a different row than it recorded.
2016-07-06 03:16:05 -07:00
Andrew Waterman
f3e22984d5
Remove uarch counters
...
These will be replaced with the indirect TDR scheme used by breakpoints.
2016-07-06 01:41:41 -07:00
Andrew Waterman
25fdabdd59
Don't implicitly create Vecs, since they're heavyweight
2016-07-06 01:41:31 -07:00
Andrew Waterman
8bd7e3932b
Implement priv-1.9 PTE scheme
2016-07-05 19:19:49 -07:00
Andrew Waterman
ebefe57036
simplify BTB fetchWidth=1 special case
2016-07-04 23:43:47 -07:00
Andrew Waterman
2d325df60c
Improve PTW simulation performance
2016-07-02 14:34:18 -07:00
Andrew Waterman
5aa8ef1855
Remove invalidation support from BTB
...
Validating the target PC in the pipeline is cheaper than maintaining
the valid bits and control logic to guarantee the BTB won't ever
mispredict branch targets.
2016-07-02 14:27:29 -07:00
Andrew Waterman
663002ec0c
Improve TLB simulation performance
2016-07-02 14:26:05 -07:00
Howard Mao
a9e0a5e2df
changes to imports after uncore refactor
2016-06-28 14:09:31 -07:00
Andrew Waterman
c10691b616
Don't take interrupts on instructions in branch shadow
...
In situations like
j 1f
nop
1: nop
the interrupt could be taken on the first nop.
2016-06-28 12:47:49 -07:00
Andrew Waterman
a70dee17ea
Make RoCC energy-saving logic mirror same for D$
2016-06-28 12:47:45 -07:00
Andrew Waterman
6f85056494
Remove reliance on HtifKey
2016-06-23 13:18:51 -07:00
Andrew Waterman
6d43c0a945
Mask interrupts during single-step
2016-06-23 00:01:06 -07:00
Andrew Waterman
5644a2703a
Avoid need for FENCE.I in debug programs
...
This is a hack to work around caching the (uncacheable) debug RAM. The
RAM is always entered with a JALR, so flush the I$ on any debug-mode JALR.
2016-06-23 00:01:06 -07:00
Andrew Waterman
7f88a00a38
Always verify BTB result; don't bother flushing it
...
This improves CPI for things like
lbu t0, (t0)
j foo
addi t0, t0, 1
where the addi would stall, causing j's misprediction check to fail,
flushing the pipeline.
2016-06-23 00:01:06 -07:00
Howard Mao
4c31248917
make sure UseAtomics is on when PTW is being used
2016-06-22 16:09:45 -07:00
Howard Mao
d1c83ccda0
change Tile interface to allow arbitrary number of cached and uncached channels
2016-06-20 09:55:30 -07:00
Andrew Waterman
60bddddfe6
Merge sptbr and sasid
2016-06-17 18:29:05 -07:00
Andrew Waterman
0b4c8e9af7
Add D-mode single-step support
2016-06-15 16:21:24 -07:00
Colin Schmidt
e3816d5fc7
set invalidate_lr in other rocc examples ( #47 )
...
This should fix https://travis-ci.org/ucb-bar/rocket-chip/jobs/137607305
2016-06-14 16:59:37 -07:00
Andrew Waterman
e3b4b55836
Refactor breakpoints and support range comparison (currently disabled)
2016-06-10 19:55:58 -07:00
Andrew Waterman
c8c7246cce
Update breakpoint spec
2016-06-09 19:07:21 -07:00
Colin Schmidt
2c325151bf
pass invalidate_lr through simple cache interface ( #45 )
2016-06-09 17:22:36 -07:00
Andrew Waterman
586c1079d0
Fix D$ for set size > page size
2016-06-09 13:02:28 -07:00
Andrew Waterman
dca55a2b35
Respect breakpoint privilege settings
2016-06-09 12:41:52 -07:00
Andrew Waterman
c85ea7b987
Set badaddr on breakpoints
2016-06-09 12:33:43 -07:00
Andrew Waterman
4cd77cef10
Make dcsr.halt writable
2016-06-09 12:30:09 -07:00
Colin Schmidt
8516e38eb2
remove implicit modulo addressing in FPU ( #44 )
2016-06-09 11:33:33 -07:00
Andrew Waterman
e3c17b5f74
Add provisional breakpoint support
2016-06-08 20:19:52 -07:00
Andrew Waterman
4f2e2480a8
When exceptions occur in D-mode, set pc=0x808, not 0x800
...
Closes #43
2016-06-06 20:57:22 -07:00
Andrew Waterman
3b0c1ed0c3
Cope with changes to AddrMap
2016-06-03 13:50:29 -07:00
Andrew Waterman
13386af1d1
Get rid of unused implicit conversion
2016-06-01 19:30:41 -07:00
Andrew Waterman
9949347569
First stab at debug interrupts
2016-06-01 16:57:10 -07:00
Andrew Waterman
51379621d6
Flush blocking D$ on FENCE.I
2016-05-31 19:27:28 -07:00
