Yunsup Lee
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94ba32bbd3
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change package name and sbt project name to rocket
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2012-02-25 17:09:26 -08:00 |
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Yunsup Lee
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946e0c6e4e
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add vector exception infrastructure
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2012-02-25 16:37:56 -08:00 |
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Andrew Waterman
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4121fb178c
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clean up mul/div interface; use VU mul if HAVE_VEC
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2012-02-24 19:22:35 -08:00 |
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Henry Cook
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62837537f4
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Improved TileIO organization, beginnings of hub implementation
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2012-02-22 18:24:52 -08:00 |
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Henry Cook
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24a32c2811
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Refining tilelink interface
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2012-02-22 12:15:47 -08:00 |
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Henry Cook
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18bd0c232b
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Added coherence message type enums
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2012-02-22 12:15:47 -08:00 |
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Andrew Waterman
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7034c9be65
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new htif protocol and implementation
You must update your fesvr and isasim!
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2012-02-19 23:15:45 -08:00 |
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Henry Cook
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619929eba1
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Added coherence tile function defs, with traits and constants
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2012-02-16 00:16:45 -08:00 |
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Andrew Waterman
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fc5ba769da
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disable vector unit by default
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2012-02-15 18:58:41 -08:00 |
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Andrew Waterman
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c13524ad3a
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fix vcmdq full replay logic
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2012-02-15 17:49:12 -08:00 |
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Yunsup Lee
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6bdf9dc513
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hwacha integration: now it compiles correctly!
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2012-02-14 23:34:57 -08:00 |
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Andrew Waterman
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c78c738f60
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minor cleanups
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2012-02-13 03:13:49 -08:00 |
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Yunsup Lee
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f47d888feb
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vvcfgivl and vsetvl works
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2012-02-09 02:35:21 -08:00 |
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Andrew Waterman
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128ec567ed
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make BTB fully associative; don't use it for JALR
JALR created a long path from the ALU in execute stage
to an address comparator to the next-PC mux. the benfit
was close to nil, anyway.
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2012-02-09 01:34:00 -08:00 |
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Yunsup Lee
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fcc8081c4d
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hook up the vector command queue
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2012-02-09 01:28:16 -08:00 |
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Andrew Waterman
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8b6b0f5367
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add external memory request interface for vec unit
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2012-02-08 22:30:45 -08:00 |
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Yunsup Lee
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9285a52f25
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initial vu integration
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2012-02-08 21:43:45 -08:00 |
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Andrew Waterman
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e9da2cf66a
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improve id/ex datapath
move operand selection into decode stage; simplify bypassing
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2012-02-08 06:47:26 -08:00 |
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Andrew Waterman
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5403d069e9
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add fp loads/stores
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2012-02-07 23:54:25 -08:00 |
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Andrew Waterman
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01a156eb98
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make # of dcache lines configurable
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2012-02-01 21:11:45 -08:00 |
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Andrew Waterman
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a5a020f97b
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update chisel and remove SRAM_READ_LATENCY
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2012-01-23 20:59:38 -08:00 |
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Henry Cook
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8623d58724
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split into two caches, compiles
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2012-01-18 17:09:35 -08:00 |
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Andrew Waterman
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0369b05deb
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move replays to writeback stage
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2012-01-17 21:12:31 -08:00 |
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Andrew Waterman
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eb657dd250
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reduce superfluous replays
we only replay after a cache miss if we mis-scheduled the use of a load.
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2012-01-01 21:28:38 -08:00 |
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Andrew Waterman
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b5a8b6dc73
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fix divider for RV32
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2011-12-19 16:57:53 -08:00 |
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Andrew Waterman
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82700cad72
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fix multiplier for rv32
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2011-12-17 07:20:00 -08:00 |
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Andrew Waterman
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a8d0cd95e6
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hellacache now works
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2011-12-17 03:26:11 -08:00 |
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Andrew Waterman
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56c4f44c2a
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hellacache returns!
but AMOs are unimplemented.
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2011-12-12 06:49:39 -08:00 |
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Andrew Waterman
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ce201559f3
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Support cache->cpu nacks one cycle after request
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2011-12-10 00:42:09 -08:00 |
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Andrew Waterman
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c01e1f1cef
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Don't replay from EX stage.
EX replays are now handled from MEM. We may move them to WB.
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2011-12-09 19:42:58 -08:00 |
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Andrew Waterman
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218f63e66e
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code cleanup/parameterization
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2011-12-09 00:42:43 -08:00 |
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Rimas Avizienis
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fa784d1d7d
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made setReadLatency argument a parameter defined in consts.scala
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2011-12-05 00:33:17 -08:00 |
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Rimas Avizienis
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bc44572d99
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bugfixes due to new hcl jar file
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2011-11-30 21:54:55 -08:00 |
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Rimas Avizienis
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80b4253318
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fixed dcache amo bug, cleaned up testharness, added RDTIME instruction
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2011-11-16 02:04:28 -08:00 |
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Rimas Avizienis
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db87924fbf
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made eret instruction take an illegal inst exception when ET is set
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2011-11-14 14:35:10 -08:00 |
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Rimas Avizienis
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cd6e463320
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added ei and di instructions
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2011-11-14 13:48:49 -08:00 |
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Rimas Avizienis
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b791010bb1
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flush.i invalidates I$ & ITLB, writing PTBR invalidates both TLBs
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2011-11-14 04:13:13 -08:00 |
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Rimas Avizienis
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5b29765917
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synced up with supervisor mode state in latest ISA simulator
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2011-11-14 01:37:20 -08:00 |
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Rimas Avizienis
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67c7e7e28f
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cache/tlb bugfixes, increased memory size to 256meg
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2011-11-13 13:06:35 -08:00 |
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Rimas Avizienis
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fbd44ea936
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added checks for addresses > physical memory size, increased memsize to 64M
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2011-11-12 23:39:43 -08:00 |
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Rimas Avizienis
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e4fa94aa27
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checkpoint
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2011-11-10 17:41:22 -08:00 |
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Rimas Avizienis
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f86d5b1334
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cleanup, lots of minor fixes, added more PCR regs (COREID, NUMCORES), parameterized BTB
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2011-11-10 11:26:13 -08:00 |
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Rimas Avizienis
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4bd0263a4a
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added misaligned instruction check, cleaned up badvaddr handling
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2011-11-10 03:38:59 -08:00 |
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Rimas Avizienis
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36aa4bcc9d
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moved exception handling from ex stage in dpath to mem stage in ctrl
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2011-11-10 02:26:26 -08:00 |
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Rimas Avizienis
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6664af3bc0
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cleanup before adding dtlb
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2011-11-09 23:27:29 -08:00 |
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Rimas Avizienis
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e96430d862
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integrating ITLB & PTW
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2011-11-09 14:52:17 -08:00 |
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Rimas Avizienis
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4459935554
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dcache fixes - all tests and ubmarks pass, hello world still broken
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2011-11-04 15:40:41 -07:00 |
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Rimas Avizienis
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7479e085ec
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dcache loads working - 1/2 cycle load/use delay depending on load type
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2011-11-01 22:04:45 -07:00 |
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Rimas Avizienis
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08b89e7710
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interface cleanup, major pipeline changes
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2011-11-01 17:59:27 -07:00 |
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Rimas Avizienis
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c06e2d16e4
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initial commit of rocket chisel project, riscv assembly tests and benchmarks
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2011-10-25 23:02:47 -07:00 |
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