riscv/rocket-chip
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Author SHA1 Message Date
Yunsup Lee
b19d783fbd add vector irq handler 2012-03-14 14:15:28 -07:00
Yunsup Lee
040d62f372 refactored vector exception handling interface 2012-03-13 23:45:34 -07:00
Yunsup Lee
b100544b25 datapath to read out vector state 2012-03-13 23:45:34 -07:00
Yunsup Lee
5655dbd5da add vvcfg and vtcfg instructions 2012-03-13 23:45:34 -07:00
Andrew Waterman
53cd543d3f fix minor coherence bugs 2012-03-13 19:10:54 -07:00
Andrew Waterman
ab6c9350db fix minor coherence bugs 2012-03-13 19:10:54 -07:00
Andrew Waterman
53d69d3006 parameterize broadcast hub by # of tiles 2012-03-13 17:12:01 -07:00
Andrew Waterman
1788c34113 parameterize broadcast hub by # of tiles 2012-03-13 17:12:01 -07:00
Andrew Waterman
1492457df5 add probe replies to HTIF 2012-03-13 16:56:47 -07:00
Andrew Waterman
1258f31825 add probe unit 2012-03-13 16:43:51 -07:00
Andrew Waterman
b0f798962c add probe unit 2012-03-13 16:43:51 -07:00
Huy Vo
1b733e7cf0 Merge branch 'master' of github.com:ucb-bar/riscv-rocket 2012-03-13 12:34:39 -07:00
Huy Vo
6e32cc8b20 Merge branch 'master' of github.com:ucb-bar/riscv-rocket 2012-03-13 12:34:39 -07:00
Huy Vo
fdffb124e3 Merge branch 'master' of github.com:ucb-bar/riscv-rocket 2012-03-13 12:34:39 -07:00
Huy Vo
6fd1527476 fix to rocket vec_dpath, updating makefiles to run xcpt test cases 2012-03-13 12:34:02 -07:00
Henry Cook
287bc1c262 Further refinement of tag_match/tag_hit signals 2012-03-13 11:48:12 -07:00
Andrew Waterman
d76b05bde1 fix way selection on D$ write upgrades 2012-03-13 02:21:02 -07:00
Andrew Waterman
fd29e00db0 support non-power-of-2 queue sizes 
need to manually wrap queue pointers.
 2012-03-13 01:58:28 -07:00
Henry Cook
23c822a82e fix hit logic for amos 2012-03-12 22:01:52 -07:00
Henry Cook
cbf7b13341 fix hit logic for amos 2012-03-12 22:01:52 -07:00
Henry Cook
95f880da70 fixed abort bug 2012-03-12 22:01:52 -07:00
Henry Cook
6229a33dc4 fixed cache controller flush unit deadlock 2012-03-12 22:01:52 -07:00
Henry Cook
ea0775643b fixed abort bug 2012-03-12 22:01:52 -07:00
Yunsup Lee
1ba5e7b865 changes to the vector exception interface 2012-03-11 21:38:47 -07:00
Yunsup Lee
113a94a21d add vector hold waits 2012-03-11 16:29:19 -07:00
Yunsup Lee
e42a4c767e don't stall on vector fences, keep replaying 2012-03-11 16:29:19 -07:00
Henry Cook
c5dd37ae80 bugfix in locking arbiter 2012-03-11 15:47:27 -07:00
Henry Cook
cb5ce3fe73 More broadcast hub bugfixes 2012-03-11 14:17:27 -07:00
Henry Cook
4ebf637642 More broadcast hub bugfixes 2012-03-11 14:17:27 -07:00
Henry Cook
a4d0025187 fix icache prefetch global_xact_id bug 2012-03-11 00:50:11 -08:00
Yunsup Lee
1aa4b0e93d going back to null coherence hub 2012-03-10 20:16:20 -08:00
Andrew Waterman
8ffdac9526 fix D$ store-upgrade bug 
loads to the same address as stores that cause an upgrade
could return the old value
 2012-03-10 15:50:10 -08:00
Andrew Waterman
d777f1cb24 fix null hub store ack bug 2012-03-10 15:19:12 -08:00
Andrew Waterman
4f4b990a4f fix null hub store ack bug 2012-03-10 15:19:12 -08:00
Yunsup Lee
44ff22a26f vector exception handler now handles prefetches correctly 2012-03-10 12:54:36 -08:00
Andrew Waterman
7eb73c325e fix signedness of zero fmul results 
We were using the FMA unit to compute rs1 * rs2 + 0.0 for fmul,
which incorrectly computes +0.0 when rs1 * rs2 == -0.0.  Now we
add -0.0 if rs1*rs2 is negative.
 2012-03-10 00:21:51 -08:00
Andrew Waterman
e3a68848e0 fix D$ critical paths and fix verilog build 2012-03-09 20:02:51 -08:00
Henry Cook
e591d83e91 Fixed global_xact_id propagation bug 2012-03-09 11:05:44 -08:00
Henry Cook
2014db41bd Special cased NTILES == 1 due to log2up revision 2012-03-09 11:04:58 -08:00
Henry Cook
9319130483 Special cased NTILES == 1 due to log2up revision 2012-03-09 11:04:58 -08:00
Andrew Waterman
85504f0ddc fix bug in fence.i and improve test 2012-03-09 03:26:05 -08:00
Andrew Waterman
766bac88f8 refactor D$ writebacks and flushes 
MSHRs now arbitrate for writebacks and handle flushes.
 2012-03-09 02:55:46 -08:00
Andrew Waterman
2607153b67 Merge branch 'master' of github.com:ucb-bar/riscv-rocket 2012-03-09 02:08:55 -08:00
Andrew Waterman
3a72ace057 Merge branch 'master' of github.com:ucb-bar/riscv-rocket 2012-03-09 02:08:55 -08:00
Andrew Waterman
ff2e47f380 Merge branch 'master' of github.com:ucb-bar/riscv-rocket 2012-03-09 02:08:55 -08:00
Yunsup Lee
a1b30282dd major refactoring on vector exception interface 2012-03-09 01:09:22 -08:00
Yunsup Lee
8acbe98f53 change how fence.*.cv works, now control processor stalls on the fence instruction 2012-03-08 23:32:31 -08:00
Henry Cook
22726ae646 icache and htif now obey require_ack field of TransactionReply. Avoids extraneous TransactionFinish on prefetcher-supplied icache data 2012-03-08 18:47:32 -08:00
Henry Cook
2df5c19f13 Added require_ack field to TransactionReply bundle 2012-03-08 18:07:44 -08:00
Henry Cook
4d2e7172f6 Added require_ack field to TransactionReply bundle 2012-03-08 18:07:44 -08:00