Howard Mao
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3103fa8da2
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rename tl to mem in generator
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2015-10-27 17:14:56 -07:00 |
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Howard Mao
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c10870a87c
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make sure ID width requirement in TL -> NASTI converter is correct
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2015-10-27 13:25:29 -07:00 |
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Howard Mao
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aeb9c86459
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use the uncached port instead of the cached port
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2015-10-26 23:09:36 -07:00 |
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Howard Mao
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b22088d934
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make sure data checked is same as data sent
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2015-10-26 21:55:04 -07:00 |
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Howard Mao
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2b252bc6ff
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first commit
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2015-10-26 21:43:50 -07:00 |
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Colin Schmidt
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86d67051b2
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Merge commit 'e31be75' into rocc-fpu-port
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2015-10-26 16:29:51 -07:00 |
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Howard Mao
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eb62ff6a50
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add queues between Nasti -> TL converter and Nasti interconnect
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2015-10-26 14:15:25 -07:00 |
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Howard Mao
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f37938e4de
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implement MultiChannel routing
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2015-10-26 14:15:25 -07:00 |
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Howard Mao
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096dbb3c2d
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get rid of NastiTopInterconnect
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2015-10-26 14:14:53 -07:00 |
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Howard Mao
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5440d6c2ae
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balance MultiChannel router correctly
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2015-10-26 12:23:03 -07:00 |
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Howard Mao
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9fa4541916
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get rid of unused full signal in ReorderQueue
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2015-10-26 12:17:25 -07:00 |
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Howard Mao
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3270d17ad3
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add MultiChannel routing to Nasti interconnect generator
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2015-10-26 12:16:17 -07:00 |
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Yunsup Lee
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a175afae73
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make ZscaleChip work with new parameters framework
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2015-10-25 10:24:39 -07:00 |
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Yunsup Lee
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c7235fecb5
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further state optimization in CSRfile when not UseVM
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2015-10-25 10:23:46 -07:00 |
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Howard Mao
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c3a7dcf0ab
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fix missing cde library dependencies in submodules
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2015-10-23 15:05:19 -07:00 |
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Colin Schmidt
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854feab08e
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add knob and constraint dumping
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2015-10-22 17:25:38 -07:00 |
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Colin Schmidt
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652fb393a3
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Merge remote-tracking branch 'origin/master' into rocc-fpu-port
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2015-10-22 16:38:28 -07:00 |
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Howard Mao
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6403f27fbe
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fix bug in ReorderQueue breaking TileLink Unwrapper
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2015-10-22 15:52:55 -07:00 |
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Jim Lawson
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0c587704a7
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Add ability to generate libraryDependency on cde.
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2015-10-22 11:37:20 -07:00 |
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Jim Lawson
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4c2b0a9032
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Add ability to generate libraryDependency on cde.
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2015-10-22 09:57:02 -07:00 |
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Jim Lawson
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8fe4917d8e
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Add ability to generate libraryDependency on cde.
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2015-10-22 09:52:26 -07:00 |
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Henry Cook
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9769b2747c
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now depend on external cde library rather than chisel.params (bump all submodules)
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2015-10-21 18:24:16 -07:00 |
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Henry Cook
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47bc193c16
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added CDE library as submodule
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2015-10-21 18:24:16 -07:00 |
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Henry Cook
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4f8468b60f
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depend on external cde library
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2015-10-21 18:19:23 -07:00 |
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Henry Cook
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f8594da1d3
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depend on external cde library
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2015-10-21 18:17:17 -07:00 |
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Henry Cook
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9c3cd8f9fe
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depend on external cde library
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2015-10-21 18:16:03 -07:00 |
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Colin Schmidt
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942f6a7d7f
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Merge commit 'd1eae61970f864afe4fde8ca7f75380c70c4658f' into rocc-fpu-port
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2015-10-21 17:18:20 -07:00 |
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Howard Mao
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21f342ad42
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fix typo causing L2 cache configuration to fail
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2015-10-21 13:37:33 -07:00 |
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Colin Schmidt
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97f29b1618
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Merge remote-tracking branch 'origin/master' into rocc-fpu-port
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2015-10-21 11:33:42 -07:00 |
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Howard Mao
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02d113b39f
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outerDataBits / innerDataBits should be per beat, not per block
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2015-10-21 11:31:13 -07:00 |
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Howard Mao
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d5a75fd113
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accidentally committed some code I didn't mean to in Rocket
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2015-10-21 09:21:54 -07:00 |
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Howard Mao
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0b7c828b5d
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go back to using standard LockingArbiter
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2015-10-21 09:15:51 -07:00 |
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Howard Mao
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693a4ae00e
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fix some more memory system bugs
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2015-10-20 23:29:59 -07:00 |
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Howard Mao
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baf95533a4
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fix combinational loop in TileLink Unwrapper
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2015-10-20 23:26:11 -07:00 |
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Howard Mao
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c68d9f8137
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make ProbeUnit state machine easier to understand
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2015-10-20 23:25:23 -07:00 |
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Howard Mao
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ffe7df2fed
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make sure TL -> NASTI converter acquire ready not dependent on valid
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2015-10-20 22:09:22 -07:00 |
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Howard Mao
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c311c9938e
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nitpicky declaration move
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2015-10-20 21:10:54 -07:00 |
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Howard Mao
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1c135c1628
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fix ready-valid mixup in TileLink unwrapper
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2015-10-20 21:07:42 -07:00 |
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Henry Cook
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62765e9609
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L2 rowBits param bugfix
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2015-10-20 18:57:19 -07:00 |
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Howard Mao
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11eacda84a
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generalize NastiReadDataArbiter
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2015-10-20 18:36:19 -07:00 |
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Henry Cook
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3fc630405b
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Vectorize RoCC and Tile memory interfaces (bump uncore, rocket, zscale)
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2015-10-20 15:05:12 -07:00 |
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Henry Cook
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1a1185be3f
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Vectorize ROCC and Tile memory interfaces
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2015-10-20 15:02:24 -07:00 |
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Henry Cook
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4389b9edb0
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tilelink parameter tweak: addrBits now a constant
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2015-10-20 15:00:30 -07:00 |
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Yunsup Lee
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cedef98045
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fix NASTI -> MemIO converter bug
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2015-10-19 21:43:59 -07:00 |
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Howard Mao
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4346111d2a
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fix remaining vsim harness typo
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2015-10-19 20:20:14 -07:00 |
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Howard Mao
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896aa892d1
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bump uncore for TL -> NASTI converter fix
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2015-10-19 15:31:59 -07:00 |
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Howard Mao
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d12403e7dc
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fix up and simplify TL -> NASTI converter logic
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2015-10-19 13:47:13 -07:00 |
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Colin Schmidt
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2cee8c8bec
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Merge commit '3c3e35a56e954b35e6ceb17179ebadc52e8d9b3f' into rocc-fpu-port
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2015-10-18 13:09:17 -07:00 |
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Henry Cook
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8c3370c2e3
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L2 AMOALU bugfix and simpler TileLinkParameters (bump rocket, uncore, zscale)
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2015-10-16 19:15:47 -07:00 |
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Henry Cook
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6f8997bee9
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Minor refactor of StoreGen/AMOALU.
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2015-10-16 19:12:46 -07:00 |
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