Andrew Waterman
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257747a3a1
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no dessert tonight :(
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2012-03-26 23:50:09 -07:00 |
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Andrew Waterman
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6bda8674bd
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no dessert tonight :(
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2012-03-26 23:50:09 -07:00 |
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Yunsup Lee
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a70f0414fa
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fix a workaroundable bug
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2012-03-26 20:51:54 -07:00 |
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Yunsup Lee
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32d95e9594
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fix -1:0 index problem for direct map case
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2012-03-26 17:00:01 -07:00 |
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Andrew Waterman
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25fe46dc18
|
remove bug from dessert
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2012-03-26 14:18:57 -07:00 |
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Andrew Waterman
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e2fe525fb6
|
remove bug from dessert
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2012-03-26 14:18:57 -07:00 |
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Yunsup Lee
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e6b0e565de
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turn HAVE_VEC on
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2012-03-26 01:21:39 -07:00 |
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Andrew Waterman
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5f53cd4ac1
|
reduce HTIF width
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2012-03-25 23:49:59 -07:00 |
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Andrew Waterman
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ef505de017
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reduce HTIF width
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2012-03-25 23:49:45 -07:00 |
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Andrew Waterman
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4e6302fedc
|
add dessert
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2012-03-25 23:03:20 -07:00 |
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Andrew Waterman
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31f0b600fd
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add dessert
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2012-03-25 23:03:20 -07:00 |
|
Andrew Waterman
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5a00143035
|
loop host.in to host.out during reset
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2012-03-25 21:45:10 -07:00 |
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Andrew Waterman
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1666d3fbd7
|
loop host.in to host.out during reset
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2012-03-25 21:45:10 -07:00 |
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Andrew Waterman
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f62a02ab54
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remove dumb stuff in top.scala
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2012-03-25 21:30:01 -07:00 |
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Andrew Waterman
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a7ebea13fc
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add mem serdes unit
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2012-03-25 17:03:58 -07:00 |
|
Andrew Waterman
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88bf8a4f23
|
add mem serdes unit
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2012-03-25 17:03:58 -07:00 |
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Andrew Waterman
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7fa93da4f5
|
add backup memory port (disabled for now)
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2012-03-25 15:49:32 -07:00 |
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Yunsup Lee
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1f33f6bb58
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HAVE_VEC is on
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2012-03-24 20:54:43 -07:00 |
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Andrew Waterman
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86d56ff67b
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refactor cpu/i$/d$ into Tile (rather than Top)
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2012-03-24 16:57:28 -07:00 |
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Andrew Waterman
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3a487ac89b
|
improve htif<->pcr interface
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2012-03-24 16:57:28 -07:00 |
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Andrew Waterman
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54fa6f660d
|
new supervisor mode
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2012-03-24 13:03:31 -07:00 |
|
Yunsup Lee
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65929a62e3
|
fix reset value for appvl
|
2012-03-22 15:32:04 -07:00 |
|
Yunsup Lee
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aaed0241af
|
get rid of vxcptwait
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2012-03-21 15:09:04 -07:00 |
|
Yunsup Lee
|
023734175d
|
now fence stalls in decode
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2012-03-20 17:10:05 -07:00 |
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Yunsup Lee
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e450e3aa40
|
fix irt counter bug regarding vector stuff
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2012-03-20 17:09:54 -07:00 |
|
Yunsup Lee
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7d7d7f49f9
|
change the tlb arbiter to a round robing one
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2012-03-20 15:21:36 -07:00 |
|
Yunsup Lee
|
5f69c5a764
|
fix bug in coherence hub, specifically in abort handling logic
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2012-03-20 02:16:28 -07:00 |
|
Yunsup Lee
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1cddd5de56
|
fix amo locking up problem
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2012-03-20 02:16:28 -07:00 |
|
Yunsup Lee
|
56cb9b7a63
|
fix bug in coherence hub, specifically in abort handling logic
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2012-03-20 02:16:28 -07:00 |
|
Yunsup Lee
|
c036fff79c
|
fix id interrupt signal
|
2012-03-19 15:13:57 -07:00 |
|
Yunsup Lee
|
0edea00166
|
now HAVE_VEC is true, since it passes the emulator
|
2012-03-19 03:10:00 -07:00 |
|
Yunsup Lee
|
264732556f
|
fixes to match verilog X semantics
|
2012-03-19 03:10:00 -07:00 |
|
Andrew Waterman
|
bd27d0fab2
|
can now take interrupts on stalled instructions
|
2012-03-19 01:02:06 -07:00 |
|
Andrew Waterman
|
2ed0be65f9
|
fix RRArbiter
|
2012-03-19 00:19:33 -07:00 |
|
Yunsup Lee
|
ba06cd953e
|
add chosen
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2012-03-18 20:43:17 -07:00 |
|
Andrew Waterman
|
c4a91303fb
|
update vector fence names and encoding
|
2012-03-18 20:42:38 -07:00 |
|
Yunsup Lee
|
2a01f558ba
|
fix unmasked valid bug in ctrl_vec
|
2012-03-18 19:55:24 -07:00 |
|
Yunsup Lee
|
98e10ddc3c
|
update vector exception instructions
|
2012-03-18 16:36:12 -07:00 |
|
Yunsup Lee
|
7493d55d3f
|
add pf fault handling
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2012-03-18 15:06:39 -07:00 |
|
Yunsup Lee
|
62ada5ea9e
|
hookup vitlb ptw port
|
2012-03-17 23:01:06 -07:00 |
|
Yunsup Lee
|
b793d63182
|
no vector interrupt masking
|
2012-03-17 23:01:06 -07:00 |
|
Yunsup Lee
|
8a4f95e617
|
changes to xcpt handling
|
2012-03-17 17:50:37 -07:00 |
|
Yunsup Lee
|
8c50c81b81
|
drop vec_irq_aux pcr register, now everything goes through badvaddr
|
2012-03-17 14:03:57 -07:00 |
|
Yunsup Lee
|
3b4680a834
|
add vitlb exception port
|
2012-03-17 14:03:33 -07:00 |
|
Andrew Waterman
|
a47eeb9571
|
retime D$ bypass into beginning of EX stage
|
2012-03-16 18:35:54 -07:00 |
|
Andrew Waterman
|
6c26921766
|
reduce D$ critical path through page table walker
costs an extra cycle per page table level to resolve a TLB miss. too bad.
|
2012-03-16 18:35:54 -07:00 |
|
Yunsup Lee
|
d38603a4ee
|
change number of tlb entries
|
2012-03-16 17:08:03 -07:00 |
|
Andrew Waterman
|
e38114e4b0
|
fix coherence bug
popping wrong store dependence queue
|
2012-03-16 01:24:07 -07:00 |
|
Andrew Waterman
|
f0157b9e2a
|
fix coherence bug
popping wrong store dependence queue
|
2012-03-16 01:24:07 -07:00 |
|
Andrew Waterman
|
cfca2d1411
|
clean up cache interfaces; avoid reserved keywords
|
2012-03-16 00:44:16 -07:00 |
|