f34843f1b9
fix assignment of incoherent vector
2016-09-04 10:12:16 -07:00
a4c1942958
flatten Coreplex module hierarchy
2016-09-02 17:45:08 -07:00
63679bb019
Add support for L1 data scratchpads instead of caches
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They fit in the same part of the address space as DRAM would be, and
are coherent (because they are not cacheable).
They are currently limited to single cores without DRAM. We intend
to lift both restrictions, probably when we add support for
heterogeneous tiles.
2016-09-02 16:22:07 -07:00
dc9ae19936
Work-around for current Scala compiler "structural type loses implicits".
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Running rocket-chip through the chisel3 gsdt branch which supports stricter connection checks and uses implicit definitions to deal with "old" direction overrides, exposed a possible bug in the Scala compiler.
[error] .../src/main/scala/uncore/devices/Prci.scala:27: value asOutput is not a member of uncore.devices.PRCIInterrupts{val mtip: chisel3.core.Bool; val msip: chisel3.core.Bool}
[error] possible cause: maybe a semicolon is missing before `value asOutput'?
[error] }.asOutput
[error] ^
[error] one error found
[error] (uncore/compile:compileIncremental) Compilation failed
This change isn't strictly required for current chisel3 code, but is being submitted in anticipation of an eventual merge of the gsdt branch prior to a compiler fix.
2016-09-02 15:38:18 -07:00
fb50f7c9dd
Set default TileLink width to XLen
2016-09-02 15:27:54 -07:00
e23e4d6de5
Add ClientUncachedTileLinkEnqueuer utility
2016-09-02 15:27:54 -07:00
7aeb42fa55
Allow narrow TL interface on PRCI; make mtime writable
2016-09-02 15:27:54 -07:00
6872000f5e
Merge pull request #239 from ucb-bar/move_rtc
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Move RTC
2016-09-02 15:17:49 -07:00
af364bc7bc
Rename RTC to RTCTick to clarify that it needs to be a Boolean signal, not a Clock type signal
2016-09-02 15:14:39 -07:00
8163a6b597
Make it easier to override the 'placeholder' Real-Time-Clock, to allow more real-world applications
2016-09-02 11:11:40 -07:00
c05ba1e864
Add TileId parameter, generalizing GroundTestId
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This usually shouldn't be used in Tiles that are meant to be P&R'd once
and multiply instantiated, as their RTL would no longer be homogeneous.
However, it is useful for conditionalizing RTL generation for
heterogeneous tiles.
2016-09-02 00:10:50 -07:00
4a7972be31
connect testharness components via member functions ( #236 )
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to prevent code duplication for new testbenches
2016-09-01 18:38:39 -07:00
08089f695d
allow configuration to be in separate project from test harness
2016-09-01 10:28:07 -07:00
c66318307c
no longer need to set invalidate_lr in RoCC examples
2016-08-31 22:05:35 -07:00
27c674972c
tie off invalidate_lr in RoCC
2016-08-31 22:00:27 -07:00
bb578494d8
don't override req.bits.phys in SimpleHellaCacheIF
2016-08-31 22:00:27 -07:00
50d6738caf
make sure DummyPTW sets all the necessary status and ptbr signals
2016-08-31 22:00:27 -07:00
403cc1c5c4
fix DecoupledTLB to handle misses appropriately
2016-08-31 22:00:27 -07:00
f4524e4c91
Add PML for Boolean.option; use it
2016-08-31 13:43:04 -07:00
2dfcf18167
Filter simv command-line args starting with -cm
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These confuse HTIF, so don't pass them through.
Contributed by @scottj97.
2016-08-31 13:39:35 -07:00
cf1bd90a70
Merge pull request #234 from zizztux/fix_export_mmio
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Add address map entries for exported mmio port.
2016-08-30 15:58:01 -07:00
b1ce3b8c98
Add address map entries for exported mmio port.
2016-08-31 06:58:38 +09:00
8dbee2b133
Don't conditionalize running bmarks on UseVM
2016-08-29 13:43:29 -07:00
07d48df88a
Get rid of FPU RoCC port logic when RoCC not present
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The previous approach used ex_reg_valid to determine whether to
source data from the FPU or RoCC. Thus, when the RoCC was not
present, it was still creating muxes. Using ex_cp_valid instead
gets rid of them.
2016-08-29 12:59:17 -07:00
f91552a650
Add performance counter support
2016-08-29 12:31:52 -07:00
1e3339e97c
Update breakpoints to match @timsifive's debug spec
2016-08-29 12:31:52 -07:00
9ca82dd397
reset default MulDiv config to moderately fast default
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Closes #228 .
In commit 3f8c60bbd6
2016-08-29 12:31:52 -07:00
33eaf08b60
set missing port direction
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Ideally, chisel should flag this as an error.
2016-08-29 12:31:52 -07:00
a19bd6de96
Get in line with FIRRTL randomization flag changes ( #231 )
2016-08-29 12:29:01 -07:00
35948918b6
Merge pull request #226 from ucb-bar/coreplex_peripheral_interrupts
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Allow some External Interrupts to come from Periphery
2016-08-26 11:52:04 -07:00
53ee54dbd1
Incorporate feedback to make the NExtPerhipheryInterrupts come from DeviceBlock itself
2016-08-26 10:40:39 -07:00
41aa80c5d7
Merge remote-tracking branch 'origin/master' into coreplex_peripheral_interrupts
2016-08-26 09:32:36 -07:00
79293f4fa2
Use a better iterator inside the DCache
2016-08-25 20:41:39 -07:00
115e8edd83
Merge branch 'master' into coreplex_peripheral_interrupts
2016-08-25 17:26:56 -07:00
93c801f598
Streamline the Generator App and associated utilities. Remove deprecated call to chiselMain and useless Chisel2 args. Update arguments to sbt run. ( #227 )
2016-08-25 17:26:28 -07:00
abfaae8f4b
Merge branch 'master' into coreplex_peripheral_interrupts
2016-08-25 14:57:53 -07:00
4f388add67
More accurate conditional include of generated .d make fragment ( #222 )
2016-08-25 14:42:04 -07:00
428eed79a1
Allow some External Interrupts to come from Periphery
2016-08-25 14:16:33 -07:00
8ff739d3fa
Merge pull request #225 from ucb-bar/remove-openocd
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Remove openocd from .gitmodules
2016-08-25 11:01:17 -07:00
3a674b413d
Remove openocd from .gitmodules
2016-08-25 10:05:30 -07:00
d5d076200e
Merge pull request #213 from ucb-bar/new_test_jtag_DTM
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Adds Logic & test support for JTAG implementation of Debug Transport Module.
2016-08-23 18:18:18 -07:00
67467c65f5
Add a jtag-dtm-regression target to the regression
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This doesn't get added to Travis, but this target can be used
by other automated testing tools which may want to do further
testing on rocket-chip.
2016-08-23 16:53:50 -07:00
32118269c1
Remove } introduced in merge
2016-08-23 08:20:52 -07:00
c22c77c7a4
remove pointer to openOCD
2016-08-23 07:35:48 -07:00
9974626d6a
Merge remote-tracking branch 'origin/master' into HEAD
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Conflicts:
src/main/scala/rocketchip/TestHarness.scala
2016-08-23 07:34:01 -07:00
61aa716f44
fix bus axi connections in periphery
2016-08-22 11:57:15 -07:00
f9ea14b4c2
extra devices should get elaborated in a single build function
2016-08-22 11:57:15 -07:00
96e2cefb34
Merge branch 'master' into HEAD
2016-08-22 11:37:30 -07:00
8d6f080ed0
Merge pull request #215 from ucb-bar/test-harness-fixes
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Test harness fixes
2016-08-22 10:33:01 -07:00
b7181ba49b
Merge branch 'master' into test-harness-fixes
2016-08-19 22:53:12 -07:00
