Howard Mao
6ddf81090b
didn't mean to turn off GenerateCached in last commit
2015-11-11 17:39:08 -08:00
Howard Mao
11f0b3d8db
restore old L2 cache AcquireTransactor configuration
2015-11-11 17:10:58 -08:00
Howard Mao
31da692ccc
default to single tile in WithMemtest
2015-11-11 14:54:13 -08:00
Howard Mao
55581195eb
add groundtest submodule for simple memory testing
2015-11-11 14:33:02 -08:00
Howard Mao
bbf14ddc01
use definitions in consts header whenever possible
2015-11-05 10:48:32 -08:00
Howard Mao
7b252d8f89
get rid of now-unnecessary bits in MIF tag
2015-11-05 10:48:32 -08:00
Sagar Karandikar
ee9195be26
rename NBANKS knob to NBANKS_PER_MEM_CHANNEL for clarity
2015-11-05 10:48:32 -08:00
Sagar Karandikar
354abf5e6b
fix NSets calculation
2015-11-05 10:48:32 -08:00
Howard Mao
dcef020ca0
get multichannel simulation working in emulator
2015-11-05 10:48:32 -08:00
Yunsup Lee
51116e0674
add 2 and 4 memory channel configs
2015-11-05 10:48:32 -08:00
Yunsup Lee
0d245741bc
add multichannel NASTI support in Verilog testbench
2015-11-05 10:48:32 -08:00
Howard Mao
9dabcab9c2
Get rid of MemIO in Top and replace with AXI throughout
2015-11-05 10:48:32 -08:00
Howard Mao
f37938e4de
implement MultiChannel routing
2015-10-26 14:15:25 -07:00
Yunsup Lee
a175afae73
make ZscaleChip work with new parameters framework
2015-10-25 10:24:39 -07:00
Henry Cook
9769b2747c
now depend on external cde library rather than chisel.params (bump all submodules)
2015-10-21 18:24:16 -07:00
Henry Cook
62765e9609
L2 rowBits param bugfix
2015-10-20 18:57:19 -07:00
Henry Cook
3fc630405b
Vectorize RoCC and Tile memory interfaces (bump uncore, rocket, zscale)
2015-10-20 15:05:12 -07:00
Henry Cook
8c3370c2e3
L2 AMOALU bugfix and simpler TileLinkParameters (bump rocket, uncore, zscale)
2015-10-16 19:15:47 -07:00
Howard Mao
c4117eb9a2
make sure TL parameters change properly throughout
...
* Outermost TL parameters should have the width set to be the same as the
MIF data width.
* Broadcast Hub and Narrower, which use different sets of TL parameters
should use the proper set of parameters at each interface
2015-10-14 18:03:39 -07:00
Henry Cook
4270fd78a5
Merge branch 'param-refactor-tl'
2015-10-14 12:16:22 -07:00
Henry Cook
dd5052888d
refactor tilelink params, compiles but ExampleSmallConfig fails
2015-10-13 23:44:05 -07:00
Howard Mao
a44e054c77
add support for different TileLink and MIF data widths
2015-10-13 12:46:23 -07:00
Henry Cook
9d11b64c75
added HasAddrMapParameters and GlobalAddrMap
2015-10-06 18:24:08 -07:00
Henry Cook
c4eadbda57
Removed all traces of params
2015-10-06 11:42:06 -07:00
Henry Cook
3d10a89907
refactor NASTI to not use param; new AddrMap class
2015-10-06 11:41:47 -07:00
Andrew Waterman
79cdf6efc0
Make perf counters optional
2015-09-28 13:56:08 -07:00
Howard Mao
7b0167b92e
make sure SCR and PCR data width matches xLen
2015-09-25 12:13:22 -07:00
Howard Mao
0d763524ef
make sure conf address map scales with number of cores
2015-09-25 09:41:19 -07:00
Howard Mao
56ecdff52d
Implement NASTI-based Mem/IO interconnect
2015-09-22 10:32:31 -07:00
Henry Cook
0c9a7817b6
Reduce outstanding mem accesses for FPGAConfig (to reduce MIFTagBits < 7)
2015-07-30 16:30:00 -07:00
Henry Cook
51c42083d0
Add new junctions repo as submodule (contains externally facing buses and peripherals).
...
Bump all submodules.
2015-07-29 18:15:45 -07:00
Yunsup Lee
efd6458a3d
add zscale programs
2015-07-27 19:06:06 -07:00
Yunsup Lee
e7802825c3
add Zscale testing
2015-07-17 12:02:02 -07:00
Henry Cook
76046c52fe
Cleanup testing rv64uf
2015-07-13 18:58:58 -07:00
Henry Cook
302cd3e638
Added BuildZscale param for use in Top and makefrag generation
2015-07-13 15:46:42 -07:00
Henry Cook
407d8e473e
first cut at parameter-based testing
2015-07-13 14:54:26 -07:00
Henry Cook
4e4015089d
rename Configs source
2015-07-09 15:04:11 -07:00
