272 lines
11 KiB
Scala
272 lines
11 KiB
Scala
// See LICENSE for license details.
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package rocketchip
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import Chisel._
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import junctions._
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import uncore._
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import rocket._
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import rocket.Util._
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import zscale._
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import scala.math.max
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import DefaultTestSuites._
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import cde.{Parameters, Config, Dump, Knob}
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class DefaultConfig extends Config (
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topDefinitions = { (pname,site,here) =>
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type PF = PartialFunction[Any,Any]
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def findBy(sname:Any):Any = here[PF](site[Any](sname))(pname)
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def genCsrAddrMap: AddrMap = {
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val csrSize = (1 << 12) * (site(XLen) / 8)
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val csrs = (0 until site(NTiles)).map{ i =>
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AddrMapEntry(s"csr$i", None, MemSize(csrSize, AddrMapConsts.RW))
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}
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val scrSize = site(HtifKey).nSCR * (site(XLen) / 8)
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val scr = AddrMapEntry("scr", None, MemSize(scrSize, AddrMapConsts.RW))
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new AddrMap(csrs :+ scr)
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}
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pname match {
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case HtifKey => HtifParameters(
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width = Dump("HTIF_WIDTH", 16),
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nSCR = 64,
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offsetBits = site(CacheBlockOffsetBits),
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nCores = site(NTiles))
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//Memory Parameters
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case PAddrBits => 32
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case PgIdxBits => 12
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case PgLevels => if (site(XLen) == 64) 3 /* Sv39 */ else 2 /* Sv32 */
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case PgLevelBits => site(PgIdxBits) - log2Up(site(XLen)/8)
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case VPNBits => site(PgLevels) * site(PgLevelBits)
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case PPNBits => site(PAddrBits) - site(PgIdxBits)
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case VAddrBits => site(VPNBits) + site(PgIdxBits)
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case ASIdBits => 7
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case MIFTagBits => // Bits needed at the L2 agent
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log2Up(site(NAcquireTransactors)+2) +
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// Bits added by NASTI interconnect
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log2Up(site(NMemoryChannels) * site(NBanksPerMemoryChannel) + 1) +
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// Bits added by final arbiter (not needed if true multichannel memory)
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log2Up(site(NMemoryChannels))
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case MIFDataBits => 64
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case MIFAddrBits => site(PAddrBits) - site(CacheBlockOffsetBits)
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case MIFDataBeats => site(CacheBlockBytes) * 8 / site(MIFDataBits)
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case NastiKey => {
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Dump("MEM_STRB_BITS", site(MIFDataBits) / 8)
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NastiParameters(
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dataBits = Dump("MEM_DATA_BITS", site(MIFDataBits)),
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addrBits = Dump("MEM_ADDR_BITS", site(PAddrBits)),
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idBits = Dump("MEM_ID_BITS", site(MIFTagBits)))
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}
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//Params used by all caches
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case NSets => findBy(CacheName)
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case NWays => findBy(CacheName)
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case RowBits => findBy(CacheName)
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case NTLBEntries => findBy(CacheName)
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case "L1I" => {
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case NSets => Knob("L1I_SETS") //64
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case NWays => Knob("L1I_WAYS") //4
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case RowBits => 4*site(CoreInstBits)
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case NTLBEntries => 8
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}:PF
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case "L1D" => {
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case NSets => Knob("L1D_SETS") //64
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case NWays => Knob("L1D_WAYS") //4
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case RowBits => 2*site(CoreDataBits)
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case NTLBEntries => 8
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}:PF
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case ECCCode => None
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case Replacer => () => new RandomReplacement(site(NWays))
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case AmoAluOperandBits => site(XLen)
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//L1InstCache
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case BtbKey => BtbParameters()
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//L1DataCache
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case WordBits => site(XLen)
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case StoreDataQueueDepth => 17
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case ReplayQueueDepth => 16
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case NMSHRs => Knob("L1D_MSHRS")
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case NIOMSHRs => 1
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case LRSCCycles => 32
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//L2 Memory System Params
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case NAcquireTransactors => 7
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case L2StoreDataQueueDepth => 1
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case L2DirectoryRepresentation => new NullRepresentation(site(NTiles))
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case BuildL2CoherenceManager => (p: Parameters) =>
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Module(new L2BroadcastHub()(p.alterPartial({
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case InnerTLId => "L1toL2"
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case OuterTLId => "L2toMC" })))
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//Tile Constants
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case BuildTiles => {
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TestGeneration.addSuites(rv64i.map(_("p")))
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TestGeneration.addSuites((if(site(UseVM)) List("pt","v") else List("pt")).flatMap(env => rv64u.map(_(env))))
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TestGeneration.addSuites(if(site(NTiles) > 1) List(mtBmarks, bmarks) else List(bmarks))
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List.fill(site(NTiles)){ (r: Bool, p: Parameters) =>
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Module(new RocketTile(resetSignal = r)(p.alterPartial({case TLId => "L1toL2"})))
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}
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}
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case BuildRoCC => None
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case RoccNMemChannels => 1
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//Rocket Core Constants
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case FetchWidth => 1
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case RetireWidth => 1
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case UseVM => true
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case UsePerfCounters => true
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case FastLoadWord => true
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case FastLoadByte => false
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case FastMulDiv => true
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case XLen => 64
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case UseFPU => {
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val env = if(site(UseVM)) List("p","pt","v") else List("p","pt")
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if(site(FDivSqrt)) TestGeneration.addSuites(env.map(rv64uf))
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else TestGeneration.addSuites(env.map(rv64ufNoDiv))
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true
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}
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case FDivSqrt => true
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case SFMALatency => 2
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case DFMALatency => 3
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case CoreInstBits => 32
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case CoreDataBits => site(XLen)
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case NCustomMRWCSRs => 0
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//Uncore Paramters
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case RTCPeriod => 100 // gives 10 MHz RTC assuming 1 GHz uncore clock
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case LNEndpoints => site(TLKey(site(TLId))).nManagers + site(TLKey(site(TLId))).nClients
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case LNHeaderBits => log2Ceil(site(TLKey(site(TLId))).nManagers) +
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log2Up(site(TLKey(site(TLId))).nClients)
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case TLKey("L1toL2") =>
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TileLinkParameters(
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coherencePolicy = new MESICoherence(site(L2DirectoryRepresentation)),
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nManagers = site(NBanksPerMemoryChannel)*site(NMemoryChannels),
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nCachingClients = site(NTiles),
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nCachelessClients = 1 + site(NTiles) *
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(1 + (if(site(BuildRoCC).isEmpty) 0 else site(RoccNMemChannels))),
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maxClientXacts = max(site(NMSHRs) + site(NIOMSHRs),
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if(site(BuildRoCC).isEmpty) 1 else site(RoccMaxTaggedMemXacts)),
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maxClientsPerPort = if(site(BuildRoCC).isEmpty) 1 else 2,
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maxManagerXacts = site(NAcquireTransactors) + 2,
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dataBits = site(CacheBlockBytes)*8)
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case TLKey("L2toMC") =>
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TileLinkParameters(
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coherencePolicy = new MEICoherence(new NullRepresentation(site(NBanksPerMemoryChannel))),
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nManagers = 1,
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nCachingClients = site(NBanksPerMemoryChannel),
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nCachelessClients = 0,
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maxClientXacts = 1,
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maxClientsPerPort = site(NAcquireTransactors) + 2,
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maxManagerXacts = 1,
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dataBits = site(CacheBlockBytes)*8)
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case TLKey("Outermost") => site(TLKey("L2toMC")).copy(dataBeats = site(MIFDataBeats))
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case NTiles => Knob("NTILES")
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case NMemoryChannels => 1
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case NBanksPerMemoryChannel => Knob("NBANKS")
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case NOutstandingMemReqsPerChannel => site(NBanksPerMemoryChannel)*(site(NAcquireTransactors)+2)
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case BankIdLSB => 0
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case CacheBlockBytes => 64
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case CacheBlockOffsetBits => log2Up(here(CacheBlockBytes))
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case UseBackupMemoryPort => true
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case MMIOBase => BigInt(1 << 30) // 1 GB
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case ExternalIOStart => 2 * site(MMIOBase)
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case GlobalAddrMap => AddrMap(
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AddrMapEntry("mem", None, MemChannels(site(MMIOBase), site(NMemoryChannels), AddrMapConsts.RWX)),
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AddrMapEntry("conf", None, MemSubmap(site(ExternalIOStart) - site(MMIOBase), genCsrAddrMap)),
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AddrMapEntry("io", Some(site(ExternalIOStart)), MemSize(2 * site(MMIOBase), AddrMapConsts.RW)))
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}},
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knobValues = {
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case "NTILES" => 1
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case "NBANKS" => 1
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case "L1D_MSHRS" => 2
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case "L1D_SETS" => 64
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case "L1D_WAYS" => 4
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case "L1I_SETS" => 64
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case "L1I_WAYS" => 4
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}
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)
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class DefaultVLSIConfig extends DefaultConfig
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class DefaultCPPConfig extends DefaultConfig
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class With2Cores extends Config(knobValues = { case "NTILES" => 2 })
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class With4Cores extends Config(knobValues = { case "NTILES" => 4 })
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class With8Cores extends Config(knobValues = { case "NTILES" => 8 })
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class With2Banks extends Config(knobValues = { case "NBANKS" => 2 })
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class With4Banks extends Config(knobValues = { case "NBANKS" => 4 })
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class With8Banks extends Config(knobValues = { case "NBANKS" => 8 })
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class WithL2Cache extends Config(
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(pname,site,here) => pname match {
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case "L2_CAPACITY_IN_KB" => Knob("L2_CAPACITY_IN_KB")
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case "L2Bank" => {
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case NSets => (((here[Int]("L2_CAPACITY_IN_KB")*1024) /
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site(CacheBlockBytes)) /
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site(NBanksPerMemoryChannel)*site(NMemoryChannels)) /
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site(NWays)
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case NWays => Knob("L2_WAYS")
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case RowBits => site(TLKey(site(TLId))).dataBitsPerBeat
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}: PartialFunction[Any,Any]
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case NAcquireTransactors => 2
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case NSecondaryMisses => 4
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case L2DirectoryRepresentation => new FullRepresentation(site(NTiles))
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case BuildL2CoherenceManager => (p: Parameters) =>
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Module(new L2HellaCacheBank()(p.alterPartial({
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case CacheName => "L2Bank"
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case InnerTLId => "L1toL2"
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case OuterTLId => "L2toMC"})))
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},
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knobValues = { case "L2_WAYS" => 8; case "L2_CAPACITY_IN_KB" => 2048 }
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)
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class WithL2Capacity2048 extends Config(knobValues = { case "L2_CAPACITY_IN_KB" => 2048 })
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class WithL2Capacity1024 extends Config(knobValues = { case "L2_CAPACITY_IN_KB" => 1024 })
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class WithL2Capacity512 extends Config(knobValues = { case "L2_CAPACITY_IN_KB" => 512 })
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class WithL2Capacity256 extends Config(knobValues = { case "L2_CAPACITY_IN_KB" => 256 })
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class WithL2Capacity128 extends Config(knobValues = { case "L2_CAPACITY_IN_KB" => 128 })
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class WithL2Capacity64 extends Config(knobValues = { case "L2_CAPACITY_IN_KB" => 64 })
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class DefaultL2Config extends Config(new WithL2Cache ++ new DefaultConfig)
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class DefaultL2VLSIConfig extends Config(new WithL2Cache ++ new DefaultVLSIConfig)
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class DefaultL2CPPConfig extends Config(new WithL2Cache ++ new DefaultCPPConfig)
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class DefaultL2FPGAConfig extends Config(new WithL2Capacity64 ++ new WithL2Cache ++ new DefaultFPGAConfig)
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class WithZscale extends Config(
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(pname,site,here) => pname match {
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case BuildZscale => {
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TestGeneration.addSuites(List(rv32ui("p"), rv32um("p")))
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TestGeneration.addSuites(List(zscaleBmarks))
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(r: Bool, p: Parameters) => Module(new Zscale(r)(p))
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}
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case BootROMCapacity => Dump("BOOT_CAPACITY", 16*1024)
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case DRAMCapacity => Dump("DRAM_CAPACITY", 64*1024*1024)
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}
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)
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class ZscaleConfig extends Config(new WithZscale ++ new DefaultConfig)
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class FPGAConfig extends Config (
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(pname,site,here) => pname match {
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case NAcquireTransactors => 4
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case UseBackupMemoryPort => false
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}
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)
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class DefaultFPGAConfig extends Config(new FPGAConfig ++ new DefaultConfig)
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class SmallConfig extends Config (
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topDefinitions = { (pname,site,here) => pname match {
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case UseFPU => false
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case FastMulDiv => false
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case NTLBEntries => 4
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case BtbKey => BtbParameters(nEntries = 8)
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}},
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knobValues = {
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case "L1D_SETS" => 64
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case "L1D_WAYS" => 1
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case "L1I_SETS" => 64
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case "L1I_WAYS" => 1
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}
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)
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class DefaultFPGASmallConfig extends Config(new SmallConfig ++ new DefaultFPGAConfig)
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class ExampleSmallConfig extends Config(new SmallConfig ++ new DefaultConfig)
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class MultibankConfig extends Config(new With2Banks ++ new DefaultConfig)
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class MultibankL2Config extends Config(
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new With2Banks ++ new WithL2Cache ++ new DefaultConfig)
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