Yunsup Lee
|
1cb2d1d7b7
|
initialize all SRAMs to avoid X propagation problem
|
2014-09-04 11:06:01 -07:00 |
|
Yunsup Lee
|
763c57931b
|
fix problem introduced with verilog generation in vsim/fsim
|
2014-09-04 09:49:57 -07:00 |
|
Scott Beamer
|
6c6f5a3843
|
add verilog target to build without simulator
|
2014-09-03 17:28:45 -07:00 |
|
Scott Beamer
|
13b6ec4712
|
including better sbt fixes
|
2014-09-02 15:16:31 -07:00 |
|
Scott Beamer
|
f8821b4cc9
|
better fix with explanation of sbt issue
|
2014-09-02 15:16:03 -07:00 |
|
Scott Beamer
|
600c5d50a9
|
better fix with explanation of sbt issue
|
2014-09-02 15:14:56 -07:00 |
|
Scott Beamer
|
26649b30ed
|
fixes sbt error during first run
|
2014-09-02 14:34:55 -07:00 |
|
Scott Beamer
|
f9922a106b
|
fixes sbt error during first run
|
2014-09-02 14:34:36 -07:00 |
|
Scott Beamer
|
bfb662968d
|
fixes sbt error during first run
|
2014-09-02 14:33:58 -07:00 |
|
Henry Cook
|
82467313dd
|
merge in rocketchip changes from master
|
2014-09-02 13:51:57 -07:00 |
|
Henry Cook
|
3250db0dd5
|
bump uncore
|
2014-09-02 12:37:44 -07:00 |
|
Henry Cook
|
712f3a754d
|
merge in master
|
2014-09-02 12:34:42 -07:00 |
|
Henry Cook
|
8622eb0f5b
|
bump rocket
|
2014-09-01 13:34:15 -07:00 |
|
Henry Cook
|
b42a2ab40a
|
Final parameter refactor
|
2014-09-01 13:28:58 -07:00 |
|
Adam Izraelevitz
|
2d6aafc32e
|
Merge branch 'dse' of github.com:ucb-bar/rocket-staging into HEAD
|
2014-09-01 11:23:50 -07:00 |
|
Yunsup Lee
|
7734285507
|
forgot to comment out hwacha
|
2014-09-01 09:01:36 -07:00 |
|
Yunsup Lee
|
0d18e491c7
|
update gitignore
|
2014-09-01 08:59:59 -07:00 |
|
Yunsup Lee
|
882fecf43a
|
update README
|
2014-08-31 20:57:16 -07:00 |
|
Yunsup Lee
|
c03c09ec31
|
update for rocket-chip release
|
2014-08-31 20:26:55 -07:00 |
|
Sagar Karandikar
|
83c6c2c9e2
|
rename refs to zynq-fpga to fpga-zynq
|
2014-08-29 10:26:48 -07:00 |
|
Henry Cook
|
78ab83d224
|
refactor fpga top/config
|
2014-08-28 13:07:54 -07:00 |
|
Scott Beamer
|
83380053de
|
use fpga backend for fpga
|
2014-08-26 15:56:27 -07:00 |
|
Henry Cook
|
bf356b9cb4
|
Refactor to combine fpga and vlsi tops, part 1
|
2014-08-24 19:30:53 -07:00 |
|
Henry Cook
|
17b2359c9a
|
htif parameters trait
|
2014-08-24 19:27:58 -07:00 |
|
Henry Cook
|
a41d55b643
|
Final parameter refactor.
|
2014-08-23 01:26:03 -07:00 |
|
Henry Cook
|
dc5643b12f
|
Final parameter refactor.
|
2014-08-23 01:19:36 -07:00 |
|
Scott Beamer
|
63b62394d9
|
added l2 to fpga
with new chisel & uncore, it goes into brams
|
2014-08-20 15:41:07 -07:00 |
|
Scott Beamer
|
e384b33cc3
|
don't generate a write mask for BigMem if it isn't used
not needed for llc data
|
2014-08-19 15:50:20 -07:00 |
|
Henry Cook
|
9b36162b67
|
Point rocket/ to rocket-staging repo
|
2014-08-19 14:20:15 -07:00 |
|
Henry Cook
|
2741bbf2b9
|
Point rocket/ to rocket-staging repo
|
2014-08-19 13:53:24 -07:00 |
|
Henry Cook
|
6a4193cf90
|
minor cache param cleanup
|
2014-08-19 11:38:46 -07:00 |
|
Henry Cook
|
2de268b3b1
|
Cache utility traits. Completely compiles, asm tests hang.
|
2014-08-19 11:38:20 -07:00 |
|
Henry Cook
|
ca5f38ff26
|
a few more fixes. some param lookups fail (here() in Alter blocks)
|
2014-08-19 11:38:11 -07:00 |
|
Henry Cook
|
0dac9a7467
|
Full conversion to params. Compiles but does not elaborate.
|
2014-08-19 11:38:02 -07:00 |
|
Adam Izraelevitz
|
4e6d69892d
|
Added initial brainstorm for parameter hierarchical flattening, does not compile ;)
|
2014-08-19 11:37:50 -07:00 |
|
Adam Izraelevitz
|
812353bace
|
Ported FPU parameters to new Chisel Parameters
|
2014-08-19 11:37:27 -07:00 |
|
Yunsup Lee
|
4ac8e59b1f
|
add .gitignore
|
2014-08-18 19:27:50 -07:00 |
|
Yunsup Lee
|
d520846638
|
add README and sbt files
|
2014-08-18 19:23:10 -07:00 |
|
Scott Beamer
|
e1a4d12c65
|
fix small typos in README
|
2014-08-14 17:59:24 -07:00 |
|
Henry Cook
|
1563c1bb36
|
Fixed cache params. Asm and bmark tests pass.
|
2014-08-12 15:00:54 -07:00 |
|
Henry Cook
|
e26f8a6f6a
|
Fix errors in derived cache params
|
2014-08-12 14:55:44 -07:00 |
|
Henry Cook
|
910c886837
|
bump chisel
|
2014-08-12 14:53:19 -07:00 |
|
Henry Cook
|
74796868e7
|
chisel bump
|
2014-08-12 10:58:09 -07:00 |
|
Henry Cook
|
0ca24a5d91
|
fix debug flags
|
2014-08-12 10:35:39 -07:00 |
|
Henry Cook
|
7f07771600
|
Cache utility traits. Completely compiles, asm tests hang.
|
2014-08-11 18:37:10 -07:00 |
|
Henry Cook
|
9ab3a4262c
|
Cache utility traits. Completely compiles, asm tests hang.
|
2014-08-11 18:35:49 -07:00 |
|
Henry Cook
|
1983260e6f
|
a few more fixes. some param lookups fail (here() in Alter blocks)
|
2014-08-10 23:08:21 -07:00 |
|
Henry Cook
|
63bd0b9d2a
|
Partial conversion to params. Compiles but does not elaborate. Rocket and uncore conversion complete. FPGA and VLSI config are identical. HwachaConfig and MemoryControllerConfig not yet removed.
|
2014-08-08 12:27:47 -07:00 |
|
Henry Cook
|
f411fdcce3
|
Full conversion to params. Compiles but does not elaborate.
|
2014-08-08 12:21:57 -07:00 |
|
Scott Beamer
|
d3a8a224fe
|
README updated for new fpga flow
|
2014-08-07 14:52:56 -07:00 |
|