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2014-08-12 10:35:39 -07:00
chisel@e600be365d First cut at using new chisel parameters for toplevel parameters and fpu 2014-08-01 18:09:37 -07:00
csrc fix bug in htif_fini, need to use vc_handle! 2014-03-18 01:35:08 -07:00
dramsim2@0b3ee6799a integrate updated rocket/uncore 2012-10-18 17:51:41 -07:00
emulator fix debug flags 2014-08-12 10:35:39 -07:00
hardfloat@4a938b1aae Better branch prediction 2014-04-07 16:08:06 -07:00
project generate verilog for rekall 2014-03-15 15:31:04 -07:00
riscv-tests@83ed3f519d push tools/tests 2014-04-14 21:18:22 -07:00
riscv-tools@1f62b9b6b6 push tools/tests 2014-04-14 21:18:22 -07:00
rocket@44618ac072 Cache utility traits. Completely compiles, asm tests hang. 2014-08-11 18:37:10 -07:00
src/main/scala Cache utility traits. Completely compiles, asm tests hang. 2014-08-11 18:37:10 -07:00
uncore@041a1ec127 Cache utility traits. Completely compiles, asm tests hang. 2014-08-11 18:37:10 -07:00
.gitignore Better branch prediction 2014-04-07 16:08:06 -07:00
.gitmodules add chisel and hardfloat back as sub-projects, bump other sub-projects 2013-09-26 12:01:46 -07:00
Makefrag Merge branch 'master' of github.com:ucb-bar/reference-chip into dse 2014-08-01 18:07:22 -07:00
README use --recursive to populate all submodules. with current instructions you can't run tests because riscv-tests/env isn't pulled in 2014-02-06 16:20:48 -08:00
sbt-launch.jar Bump scala to 2.10.2, sbt to 0.13-RC2, including new launcher. Upgrade reflection in network.scala to 2.10 lib. Constants now obtained from subproject package objects. Give network its own file. 2013-07-24 23:28:43 -07:00

Quick and dirty instructions:

CHECKOUT THE CODE:

  git submodule update --init --recursive


BUILDING THE TOOLCHAIN:

  To build RISC-V ISA simulator, frontend server, proxy kernel and newlib based GNU toolchain:

    export RISCV=/path/to/riscv/toolchain/installation
    cd riscv-tools
    ./build.sh

  To build asm tests and benchmarks (you must have the RISC-V toolchain installed and in your path):

    cd riscv-tests/isa/
    make -j

    cd riscv-tests/benchmarks
    make -j

BUILDING THE PROJECT:

  To build the C simulator:

    cd emulator
    make

  To build the VCS simulator:

    cd vlsi/build/vcs-sim-rtl
    make

  in either case, you can run a set of assembly tests or simple benchmarks:

    make run-asm-tests
    make run-vecasm-tests
    make run-vecasm-timer-tests
    make run-bmarks-test

  To build a C simulator that is capable of VCD waveform generation:

    cd emulator
    make emulator-debug

  And to run the assembly tests on the C simulator and generate waveforms:

    make run-asm-tests-debug
    make run-vecasm-tests-debug
    make run-vecasm-timer-tests-debug
    make run-bmarks-test-debug


UPDATING TO A NEWER VERSION OF CHISEL:

  To grab a newer version of chisel:

    git submodule update --init
    cd chisel
    git pull origin master

  Then, to compile it and install it into the rocket repo:

    cd sbt
    sbt package
    cp chisel/target/scala-2.8.1/chisel_2.8.1-1.1.jar ../../sbt/work/lib

  If you commit a new jar, you must also commit the updated chisel submodule.