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2014-08-19 14:20:15 -07:00
chisel@2e1b6e2efc newest version of chisel needed for brams 2014-08-07 13:49:31 -07:00
csrc fix bug in htif_fini, need to use vc_handle! 2014-03-18 01:35:08 -07:00
dramsim2@0b3ee6799a integrate updated rocket/uncore 2012-10-18 17:51:41 -07:00
emulator Timeout cycles now defined in toplevel Makefrag in order to allow for easier alteration when debugging. 2014-02-12 16:50:13 -08:00
hardfloat@4a938b1aae Better branch prediction 2014-04-07 16:08:06 -07:00
project generate verilog for rekall 2014-03-15 15:31:04 -07:00
riscv-tests@83ed3f519d push tools/tests 2014-04-14 21:18:22 -07:00
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src/main/scala Refactored Metadata, expanded coherence API (bump rocket, uncore, chisel) 2014-05-28 17:16:49 -07:00
uncore@ebe0f493a6 Refactored Metadata, expanded coherence API (bump rocket, uncore, chisel) 2014-05-28 17:16:49 -07:00
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.gitmodules Point rocket/ to rocket-staging repo 2014-08-19 14:20:15 -07:00
Makefrag include new mm test in benchmarks 2014-04-18 18:05:30 -07:00
README.md fix small typos in README 2014-08-14 17:59:24 -07:00
sbt-launch.jar Bump scala to 2.10.2, sbt to 0.13-RC2, including new launcher. Upgrade reflection in network.scala to 2.10 lib. Constants now obtained from subproject package objects. Give network its own file. 2013-07-24 23:28:43 -07:00

Quick and dirty instructions:

Checkout The Code

$ git submodule update --init --recursive

Building The Toolchain

To build RISC-V ISA simulator, frontend server, proxy kernel and newlib based GNU toolchain:

$ export RISCV=/path/to/riscv/toolchain/installation
$ cd riscv-tools
$ ./build.sh

To build asm tests and benchmarks (you must have the RISC-V toolchain installed and in your path):

$ cd riscv-tests/isa/
$ make -j
$ cd riscv-tests/benchmarks
$ make -j

Building The Project

To build the C simulator:

$ cd emulator
$ make

To build the VCS simulator:

$ cd vlsi/build/vcs-sim-rtl
$ make

in either case, you can run a set of assembly tests or simple benchmarks:

$ make run-asm-tests
$ make run-vecasm-tests
$ make run-vecasm-timer-tests
$ make run-bmarks-test

To build a C simulator that is capable of VCD waveform generation:

$ cd emulator
$ make emulator-debug

(note that you must have run make emulator at least once before running make emulator-debug)

And to run the assembly tests on the C simulator and generate waveforms:

$ make run-asm-tests-debug
$ make run-vecasm-tests-debug
$ make run-vecasm-timer-tests-debug
$ make run-bmarks-test-debug

To get FPGA-synthesizable verilog (output will be in fpga/generated-src):

$ cd fpga/build/syn
$ make

Updating To A Newer Version Of Chisel

To grab a newer version of chisel:

$ git submodule update --init
$ cd chisel
$ git pull origin master