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2014-09-02 13:51:57 -07:00
chisel@18e601271a merge in rocketchip changes from master 2014-09-02 13:51:57 -07:00
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sbt-launch.jar Bump scala to 2.10.2, sbt to 0.13-RC2, including new launcher. Upgrade reflection in network.scala to 2.10 lib. Constants now obtained from subproject package objects. Give network its own file. 2013-07-24 23:28:43 -07:00

Quick and dirty instructions:

Checkout The Code

$ git submodule update --init --recursive

Building The Toolchain

To build RISC-V ISA simulator, frontend server, proxy kernel and newlib based GNU toolchain:

$ export RISCV=/path/to/riscv/toolchain/installation
$ cd riscv-tools
$ ./build.sh

Building The Project

To build the C simulator:

$ cd emulator
$ make

To build the VCS simulator:

$ cd vsim
$ make

in either case, you can run a set of assembly tests or simple benchmarks:

$ make run-asm-tests
$ make run-vecasm-tests
$ make run-vecasm-timer-tests
$ make run-bmarks-test

To build a C simulator that is capable of VCD waveform generation:

$ cd emulator
$ make emulator-debug

(note that you must have run make emulator at least once before running make emulator-debug)

And to run the assembly tests on the C simulator and generate waveforms:

$ make run-asm-tests-debug
$ make run-vecasm-tests-debug
$ make run-vecasm-timer-tests-debug
$ make run-bmarks-test-debug

To get FPGA-synthesizable verilog (output will be in fsim/generated-src):

$ cd fsim
$ make

Updating To A Newer Version Of Chisel

To grab a newer version of chisel:

$ git submodule update --init
$ cd chisel
$ git pull origin master