922b1adc9c
Add optional PLRU replacement to the L2
2015-12-16 10:00:56 -08:00
ddc79674f9
fix some issues with cache request merging
2015-12-15 21:31:02 -08:00
e71293e2ae
fix bug in narrower logic
2015-12-06 02:58:12 -08:00
93aa370b87
yunsup's fix for dgemm-opt assertion failure
2015-12-03 14:03:10 -08:00
e52685f2e9
Fix LoadGen zero flag
2015-11-25 20:52:30 -08:00
27df04354f
Add ROM with NASTI interface
2015-11-25 20:04:31 -08:00
57e82442a1
Make LoadGen and StoreGen generic
2015-11-24 18:12:42 -08:00
ee6514e4f4
make sure WritebackUnit sends correct probe addresses
2015-11-21 15:55:11 -08:00
04383a31f5
Revert "make sure L2MetadataArray assigns unoccupied way if available"
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This reverts commit 1857f36c1e6f2b2859c724eea6ae3cfb2618f81b.
2015-11-21 10:35:40 -08:00
3c95afebc6
Shift set index for multi-bank configurations
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Prior to this commit, the L2 cache banks used the lower bits of the
block address as the set index. However, the lower bits are also used to
route addresses to different banks. As a result, in multi-bank
configurations, only a fraction of the sets in each bank could be
accessed. This commit fixes that problem by using the bits ahead of the
bank index as the set index, so that all sets in the cache can be
accessed.
2015-11-20 23:24:57 -08:00
55a85cc67a
make sure wmask is passed for PutBlock in broadcast hub
2015-11-20 14:09:24 -08:00
941b64cd62
make partial write-masking PutBlock constructor always set alloc bit
2015-11-20 13:34:07 -08:00
24f7b9f472
make sure L2MetadataArray assigns unoccupied way if available
2015-11-19 10:45:54 -08:00
e50c7ad306
add NASTI error assertions back in
2015-11-18 17:05:54 -08:00
2b977325e3
Make prefetch type available in a_type, issue probeInvalidates for putPrefetches
2015-11-16 23:26:13 -08:00
d426ecee78
Remove IPI network
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This is now provided via MMIO.
2015-11-16 21:52:24 -08:00
0290635454
amo_shift_bits -> amo_shift_bytes
2015-11-16 19:07:58 -08:00
64aaf71b06
L2AcquireTracker refactor to support merging Gets and Puts into Prefetches of the correct type.
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Transaction metadata for primary and seconday misses now stored in the secondary miss queue.
Added BuiltInAcquireBuilder factory.
2015-11-16 18:10:09 -08:00
03fa06e6e7
fix prefetch lockup on L2 hit
2015-11-15 12:51:34 -08:00
e12efab423
skip meta_write state if no meta write pending
2015-11-13 13:50:35 -08:00
7e7d688a01
make sure L2 passes no-alloc acquires through to outer memory
2015-11-12 15:40:58 -08:00
b3865c370a
make sure correct addr_beat is sent for Get response by narrower/converter
2015-11-12 15:40:38 -08:00
f397d61033
add alloc option to Put constructor
2015-11-12 11:39:59 -08:00
7733fbe6a3
make sure no-alloc write still updates data array if there is a cache hit
2015-11-12 11:39:36 -08:00
b59ce5fed4
make sure L2 waits for outer grant before sending grant for write request
2015-11-10 16:06:14 -08:00
42d3d09d7a
add a ClientTileLinkEnqueuer to complement the TileLinkEnqueuer
2015-11-09 11:49:19 -08:00
7942be4e01
make sure outerTL method is idempotent
2015-11-09 11:10:02 -08:00
e3efc09b5b
remove unnecessary UInt encode/decode on releaseMatches path
2015-11-05 17:20:03 -08:00
3698153535
OHToUInt instead of PriorityEncoder on Acq/RelMatches signals in L2Bank
2015-11-03 14:31:35 -08:00
baa2544651
Fix some more issues with narrower
2015-10-31 19:36:30 -07:00
812c5bcc55
make sure narrower can handle sub-block level requests correctly
2015-10-31 15:58:36 -07:00
d4b8653002
fix too strict assertion in broadcast hub
2015-10-31 15:58:10 -07:00
c10870a87c
make sure ID width requirement in TL -> NASTI converter is correct
2015-10-27 13:25:29 -07:00
9fa4541916
get rid of unused full signal in ReorderQueue
2015-10-26 12:17:25 -07:00
6403f27fbe
fix bug in ReorderQueue breaking TileLink Unwrapper
2015-10-22 15:52:55 -07:00
4c2b0a9032
Add ability to generate libraryDependency on cde.
2015-10-22 09:57:02 -07:00
f8594da1d3
depend on external cde library
2015-10-21 18:17:17 -07:00
02d113b39f
outerDataBits / innerDataBits should be per beat, not per block
2015-10-21 11:31:13 -07:00
baf95533a4
fix combinational loop in TileLink Unwrapper
2015-10-20 23:26:11 -07:00
ffe7df2fed
make sure TL -> NASTI converter acquire ready not dependent on valid
2015-10-20 22:09:22 -07:00
1c135c1628
fix ready-valid mixup in TileLink unwrapper
2015-10-20 21:07:42 -07:00
4389b9edb0
tilelink parameter tweak: addrBits now a constant
2015-10-20 15:00:30 -07:00
d12403e7dc
fix up and simplify TL -> NASTI converter logic
2015-10-19 13:47:13 -07:00
d391f97953
Minor refactor of StoreGen/AMOALU. Bugfix for 32b ops in L2's AMOALU.
2015-10-16 19:11:06 -07:00
e1f573918d
simplify TileLinkParameters with Option
2015-10-16 18:24:38 -07:00
49667aa4b0
make sure broadcast acquire tracker doesn't try to send requests back-to-back
2015-10-14 18:56:13 -07:00
1d362d6d3a
make sure correct parameters are used for TileLink constructors
2015-10-14 17:58:54 -07:00
7fa3eb95e3
refactor tilelink params
2015-10-14 12:13:37 -07:00
66ea39638e
GlobalAddrMap
2015-10-14 00:23:28 -07:00
31be6407ec
Removed all traces of params
2015-10-14 00:23:28 -07:00
