Andrew Waterman
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0ce98a7e0c
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Update riscv-tools
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2014-01-28 03:52:55 -08:00 |
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Andrew Waterman
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fb827abbfa
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Use dynamic fesvr library
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2014-01-28 03:50:19 -08:00 |
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Andrew Waterman
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0266c1f76a
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Support retirement width > 1 in CSR file
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2014-01-24 16:37:40 -08:00 |
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Andrew Waterman
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267394d3cc
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Fix CSR interlocks
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2014-01-24 16:37:40 -08:00 |
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Andrew Waterman
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1f986d1c96
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Branches don't care about the ALU input/function
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2014-01-24 16:37:40 -08:00 |
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Andrew Waterman
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a1b7774f5d
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Simplify handling of CAUSE register
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2014-01-24 16:37:39 -08:00 |
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Yunsup Lee
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ce36d67f05
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push tools/tests
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2014-01-22 20:18:44 -08:00 |
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Andrew Waterman
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3e634aef1d
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Fix HTIF for cache line sizes other than 64 B
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2014-01-22 18:20:36 -08:00 |
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Christopher Celio
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a2be21361e
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Allow ICacheConfig to toggle fetch-width.
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2014-01-22 16:19:57 -08:00 |
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Andrew Waterman
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7c11cf49b8
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Update riscv-tools
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2014-01-21 16:23:32 -08:00 |
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Andrew Waterman
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b6c6bddb62
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Add full CSRRx support and an asm test
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2014-01-21 16:20:24 -08:00 |
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Andrew Waterman
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a7489920ce
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Support CSR atomics on all CSRs, not just STATUS
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2014-01-21 16:17:39 -08:00 |
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Stephen Twigg
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e7ee94bcc8
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Merge branch 'master' into hwacha-port
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2014-01-21 15:23:05 -08:00 |
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Andrew Waterman
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6ba2c1abe5
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Use auto-generated CAUSE constants
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2014-01-21 15:01:54 -08:00 |
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Stephen Twigg
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ee0c4ca291
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Push chisel, rocket, hwacha, tools, tests to incorporate a bunch of new changes (ISA alterations)
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2014-01-21 14:48:04 -08:00 |
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Andrew Waterman
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6f7ae01b1a
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More FPU fixes
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2014-01-17 14:10:10 -08:00 |
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Andrew Waterman
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95de358a96
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More of the same FPU fix
some SP ops followed by DP stores were not working because they
were encoded as subnormals, not NaNs.
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2014-01-17 14:09:30 -08:00 |
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Andrew Waterman
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6f028b2d52
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Increase BTB size; fix Rocket FPU bug
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2014-01-17 03:53:08 -08:00 |
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Andrew Waterman
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cf38001e98
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Fix fmv.s.x -> fsd
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2014-01-17 03:52:35 -08:00 |
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Yunsup Lee
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30b894c2c4
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Merge remote-tracking branch 'origin/master' into hwacha-port
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2014-01-16 16:04:48 -08:00 |
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Yunsup Lee
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6bbbf36979
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push accel/rocket dmem port back to rocket
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2014-01-16 16:01:41 -08:00 |
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Andrew Waterman
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dfc13236d1
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Linux works again!
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2014-01-16 12:44:29 -08:00 |
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Andrew Waterman
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57f4d89c90
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Generate D$ replay_next signals correctly
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2014-01-16 00:16:09 -08:00 |
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Andrew Waterman
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6ebdc4d94e
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Simplify store conditional failure code generation
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2014-01-16 00:15:48 -08:00 |
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Andrew Waterman
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31060ea8ae
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Fix fubar long-latency writeback control logic
Load miss writebacks happening at the same time as multiplication
wasn't working. Hopefully this does it.
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2014-01-14 04:02:43 -08:00 |
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Andrew Waterman
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4f1213cb8b
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Fix Scala integer overflow
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2014-01-13 21:45:14 -08:00 |
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Andrew Waterman
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e8486817e6
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Clean up formatting (i.e. remove tabs, semicolons)
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2014-01-13 21:43:56 -08:00 |
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Andrew Waterman
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a50a1f7d50
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Clean up multiplier/divider stuff
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2014-01-13 21:37:16 -08:00 |
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Andrew Waterman
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4d236979bd
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Fix very far forward JALs
We were sign-extending from the wrong bit, causing a backwards jump.
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2014-01-13 00:55:48 -08:00 |
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Andrew Waterman
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c546f66404
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Swap JAL/JALR encodings (again)
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2014-01-13 00:54:49 -08:00 |
|
Quan Nguyen
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37b86c89fa
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Introduce confprec
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2013-12-13 03:38:16 -08:00 |
|
Quan Nguyen
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ebec444ad2
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Increase tag width for configurable precision in Hwacha
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2013-12-13 03:33:02 -08:00 |
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Andrew Waterman
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d99ee1f9c2
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Update hardfloat, fixing SFMA unit
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2013-12-09 20:31:58 -08:00 |
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Andrew Waterman
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07a91bb99a
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Miscellaneous cleanup
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2013-12-09 19:53:14 -08:00 |
|
Andrew Waterman
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ab6cd9c9e8
|
Update chisel, rocket
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2013-12-09 15:09:48 -08:00 |
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Andrew Waterman
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da3135ac9b
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Begin integer unit clean-up
...to make it easier to generate the superscalar version of the core.
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2013-12-09 15:06:13 -08:00 |
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Andrew Waterman
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16d5250924
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Correct FP trap behavior on FCSR
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2013-12-05 04:18:04 -08:00 |
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Andrew Waterman
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5814a90472
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Make DecodeLogic interface more flexible
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2013-12-05 04:16:48 -08:00 |
|
Andrew Waterman
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a43cf9d688
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Update to new privileged ISA
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2013-11-25 04:45:06 -08:00 |
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Andrew Waterman
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924261e2b2
|
Update to new privileged ISA... phew
|
2013-11-25 04:35:15 -08:00 |
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Andrew Waterman
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acc0d2b06c
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Only use LSBs for HTIF control regs
For now, at least...
|
2013-11-25 04:34:16 -08:00 |
|
Andrew Waterman
|
65b8340cea
|
Mitigate D$ hit -> branch -> NPC critical path
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2013-11-24 14:21:03 -08:00 |
|
Andrew Waterman
|
53f726008b
|
Use Mem instead of Vec[Reg] for TLB
QoR-neutral, improves simulation speed
|
2013-11-24 14:21:02 -08:00 |
|
Yunsup Lee
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1c6f4e91f9
|
merge origin/master, and push hwacha
|
2013-11-21 15:02:40 -08:00 |
|
Yunsup Lee
|
d450b85483
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Merge branch 'master', remote-tracking branch 'origin' into hwacha
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2013-11-21 14:57:38 -08:00 |
|
Yunsup Lee
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9e6e5adeba
|
push uncore
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2013-11-21 14:55:57 -08:00 |
|
Yunsup Lee
|
951226f413
|
fix slli/slliw encoding bug
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2013-11-21 14:46:31 -08:00 |
|
Yunsup Lee
|
25fdf9827f
|
push tests
|
2013-11-21 14:45:59 -08:00 |
|
Yunsup Lee
|
68e270eeb2
|
fix slli/slliw encoding bug
|
2013-11-21 14:44:58 -08:00 |
|
Yunsup Lee
|
5642194834
|
push hwacha to consistent state
|
2013-11-20 16:44:33 -08:00 |
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