d31b26c342
Clean up handling of icache's io.cpu.npc signal
2015-05-18 18:22:48 -07:00
b09832f1b5
ICache now returns the "next PC" signal.
...
useful for other modules that need access to the fetch PC on the
cycle it is sent to the SRAM.
2015-05-07 04:53:05 -07:00
3048f4785a
HeaderlessTileLinkIO -> ClientTileLinkIO
2015-04-17 16:56:53 -07:00
49f1c0aa7b
moved ecc lib to uncore
2015-04-13 15:58:10 -07:00
91e882e3f8
Use HeaderlessTileLinkIO
2015-04-13 15:58:10 -07:00
517d0d4b89
feedback on PR
2015-04-12 18:44:03 -07:00
11dbd4221a
Fixed front-end to support four-wide fetch.
2015-04-10 17:53:47 -07:00
543ac91cf2
Misaligned fetches can't happen at the I$ anymore
...
They are caught before the I$ ever sees them, so leverage that fact.
2015-03-24 23:55:43 -07:00
e85c54cc4b
New privileged ISA implementation
2015-03-14 02:49:07 -07:00
95aa295c39
Use HeaderlessTileLinkIO to cut down on unconnected port errors in VCS
2015-03-09 16:34:43 -07:00
5d07733057
Removed TLBPTWIO from the io.cpu bundle for icache/dcache
2015-03-03 16:40:39 -08:00
1e0c16c557
new metadata api
2015-02-28 17:00:32 -08:00
741e6b77ad
Rename some params, use refactored TileLink
2015-02-01 20:37:31 -08:00
b70f7683d3
Merge branch 'master' into ss-frontend
...
Conflicts:
src/main/scala/ctrl.scala
2015-01-04 19:59:18 -08:00
2aee85cb11
Flush pipeline from MEM stage
...
This means we no longer have to rely on the instruction behind a serializing
instruction being valid, simplifying the control. But we have to be a
little more cautious when flusing the I$/ITLB/BTB.
2015-01-04 16:40:16 -08:00
1cb65d5ec1
%s/master/manager/g
2014-12-29 22:56:18 -08:00
08dcf4c6ca
refactor cache params
2014-12-17 14:28:05 -08:00
72ea24283b
multibeat TL; passes all tests
2014-12-12 16:54:33 -08:00
6749f67b7f
Fixed BHT update error.
...
- separated out BTB/BHT update
- BHT updates counters on every branch
- BTB update only on mispredicted and taken branches
2014-11-16 22:02:27 -08:00
c9e7874818
Major tilelink revision for uncached message types
2014-11-11 17:36:48 -08:00
fea31d2167
Significant changes and fixes to BTB for superscalar fetch.
...
- BTBUpdate only occurs on mispredicts now.
- RASUpdate broken out from BTBUpdate (allows RASUpdate to be performed in
Decode).
- Added optional 2nd CAM port to BTB for updates (for when updates to the
BTB may occur out-of-order).
- Fixed resp.mask bit logic.
2014-11-11 03:34:05 -08:00
3be3cd7731
Fixed error with icache/btb resp mask.
2014-11-03 01:13:22 -08:00
08d2c13330
Fixed btb/icache bugs regarding resp mask, fw==1
2014-10-20 18:45:23 -07:00
91efdc379b
Merge remote-tracking branch 'origin/master' into ss-frontend
...
Also fixed bridx logic and zero-width wire logic.
Conflicts:
src/main/scala/btb.scala
2014-10-14 18:10:29 -07:00
99614e37aa
Merge remote-tracking branch 'origin/master' into ss-frontend
...
Conflicts:
src/main/scala/btb.scala
src/main/scala/core.scala
2014-10-03 04:22:58 -07:00
9cc35dee9a
Returned history update to fetch.
...
- Global history only contains branches.
- Only update BHT and history on BTB hits.
- Gate off speculative update on stall or icmiss.
- Fixed bug where BHT updates were delayed a cycle.
2014-09-29 21:41:07 -07:00
8ccd07cfeb
Moved updating global history from fetch to decode.
...
- No longer update global history in fetch stage.
- Only update global history when instruction is a branch.
- Does allow for the possibility of back-to-back branches to see
slightly different histories on subsequent executions.
2014-09-28 05:16:36 -07:00
681b43f398
Bug fixes with global history register.
...
- Updated in fetch speculatively.
* Updates gated off by cpu.resp.fire().
* BTB direction factored into history update.
- All branches update the BHT.
- Each instruction carries history; index into BHT is recomputed by
passing in mem_reg_pc.
2014-09-26 10:39:57 -07:00
180d3d365d
Expanded front-end to support superscalar fetch.
2014-09-17 14:24:03 -07:00
8abf62fae3
add LICENSE
2014-09-12 18:06:41 -07:00
b42a2ab40a
Final parameter refactor
2014-09-01 13:28:58 -07:00
6a4193cf90
minor cache param cleanup
2014-08-19 11:38:46 -07:00
2de268b3b1
Cache utility traits. Completely compiles, asm tests hang.
2014-08-19 11:38:20 -07:00
ca5f38ff26
a few more fixes. some param lookups fail (here() in Alter blocks)
2014-08-19 11:38:11 -07:00
0dac9a7467
Full conversion to params. Compiles but does not elaborate.
2014-08-19 11:38:02 -07:00
4ca152b012
Use BundleWithConf to avoid clone method boilerplate
2014-05-09 19:37:16 -07:00
1b156c6db9
TileLinkIO.GrantAck -> TileLinkIO.Finish
2014-04-26 15:18:21 -07:00
1da8ef2ddf
Added serdes to decouple cache row size from tilelink data size
2014-04-10 12:34:12 -07:00
910b3b203a
removed AddressSpaceConstants, CacheConstants, and TileLinkSizeConstants
2014-04-10 12:32:44 -07:00
ebdc0a2692
merge Aqcuire and AcquireData. cache line size coupled to tilelink data size
2014-04-10 12:09:52 -07:00
f235fa0db6
Move branch resolution to M stage
2014-04-07 15:58:49 -07:00
db59fc65ab
Add return address stack
2014-04-01 15:01:27 -07:00
e3b12e0b85
Make BTB more complexity-effective
...
BTB entries reference a small number of unique pages, so we separate the
storage of pages from indices. This makes much larger BTBs feasible. It's
easy to exacerbate cycle time this way, so one-hot encoding is used as needed.
2014-03-25 05:22:04 -07:00
804b09c8c5
Frontend QoR tweaks
2014-03-25 05:20:24 -07:00
2c2b3a7678
cleanups supporting uncore hierarchy
2014-01-31 12:07:26 -08:00
a2be21361e
Allow ICacheConfig to toggle fetch-width.
2014-01-22 16:19:57 -08:00
65b8340cea
Mitigate D$ hit -> branch -> NPC critical path
2013-11-24 14:21:03 -08:00
1edb1e2a0a
Ignore LSB of PC
2013-09-12 17:55:58 -07:00
d06e24ac24
new enum syntax
2013-09-10 10:51:35 -07:00
3a266cbbfa
final Reg changes
2013-08-15 15:28:15 -07:00
Andrew Waterman
Christopher Celio
Henry Cook
Andrew Waterman
Yunsup Lee
Andrew Waterman