Yunsup Lee
|
a0bd0adeb2
|
change write/read port ordering for vlsi_mem_gen script
|
2013-01-29 21:32:42 -08:00 |
|
Andrew Waterman
|
66eb3720a4
|
fix SRAM semantics bug in HellaFlowQueue
|
2013-01-29 21:16:42 -08:00 |
|
Yunsup Lee
|
60bd3a6413
|
Revert "shuffled FPU control logic around to make functional unit retiming work better"
This reverts commit 20dd308067b143adff4913fc7ac710a393ca1d86.
|
2013-01-29 19:34:55 -08:00 |
|
Andrew Waterman
|
6275e009f8
|
fix HellaQueue deq.valid signal
|
2013-01-28 20:57:43 -08:00 |
|
Andrew Waterman
|
45d8066f45
|
add HellaQueue, an SRAM-based queue
|
2013-01-28 20:54:25 -08:00 |
|
Andrew Waterman
|
37c67f1d87
|
pipeline reset to the vector unit
|
2013-01-28 17:56:32 -08:00 |
|
Rimas Avizienis
|
f2df6147df
|
shuffled FPU control logic around to make functional unit retiming work better
|
2013-01-28 17:17:09 -08:00 |
|
Henry Cook
|
f5729c9f25
|
removed ack_required field from grant messages
|
2013-01-28 16:44:17 -08:00 |
|
Henry Cook
|
8cbd316b5e
|
Merge branch 'ready-sig-fix' into pin-cleanup
|
2013-01-27 23:04:58 -08:00 |
|
Henry Cook
|
931cffa749
|
ready signal fix
|
2013-01-27 23:04:35 -08:00 |
|
Henry Cook
|
83c207c852
|
pin cleanup in htif
|
2013-01-27 12:00:28 -08:00 |
|
Henry Cook
|
409b549d3c
|
actually cleared up tile ios
|
2013-01-27 11:27:09 -08:00 |
|
Henry Cook
|
696dd102eb
|
cleans up unconnected tile io pins (networking headers overwritten at top level)
|
2013-01-27 10:59:41 -08:00 |
|
Andrew Waterman
|
c890099e09
|
add System Control Register space to HTIF
|
2013-01-24 23:41:24 -08:00 |
|
Andrew Waterman
|
575bd3445a
|
re-generalize scoreboard
|
2013-01-24 18:00:39 -08:00 |
|
Andrew Waterman
|
1fbc20450e
|
don't allow simultaneous reads and writes to the tag ram
|
2013-01-24 17:55:00 -08:00 |
|
Andrew Waterman
|
37ee843b2c
|
don't use reset combinationally
|
2013-01-24 17:55:00 -08:00 |
|
Andrew Waterman
|
bb6fbddf1f
|
don't probe the mshr file to inquire about refills
|
2013-01-24 17:54:59 -08:00 |
|
Andrew Waterman
|
5b9f938263
|
correctly sign-extend badvaddr, epc, and ebase
|
2013-01-24 17:54:59 -08:00 |
|
Rimas Avizienis
|
63060bc0a8
|
minor tweaks for eos18 tapeout (SRAM r/w port ordering, etc)
|
2013-01-23 19:27:53 -08:00 |
|
Henry Cook
|
6b00e7ff74
|
New TileLink bundle names
|
2013-01-21 17:18:23 -08:00 |
|
Henry Cook
|
a2fa3fd04d
|
Refactored packet headers/payloads
|
2013-01-15 15:50:37 -08:00 |
|
Henry Cook
|
e1225c5114
|
standardize IO naming convention
|
2013-01-07 13:41:36 -08:00 |
|
Henry Cook
|
261e14f831
|
Refactored uncore conf
|
2013-01-07 13:41:36 -08:00 |
|
Andrew Waterman
|
78868f6075
|
add config option to trade mul/div area for speed
|
2013-01-06 03:47:17 -08:00 |
|
Andrew Waterman
|
ce9f4881d2
|
remove broken multiplier early out
|
2013-01-06 03:47:00 -08:00 |
|
Andrew Waterman
|
05f19b21d0
|
merge multiplier and divider
|
2012-12-12 02:22:47 -08:00 |
|
Andrew Waterman
|
c921fc34a9
|
merge ALU left and right shifters
|
2012-12-12 02:22:34 -08:00 |
|
Andrew Waterman
|
f5c53ce35d
|
add ecc support to d$ data rams
i haven't injected errors yet; it may well be incorrect.
|
2012-12-11 15:58:53 -08:00 |
|
Andrew Waterman
|
3f59e439ef
|
fix d$ tag raw hazard
|
2012-12-07 15:14:20 -08:00 |
|
Andrew Waterman
|
e9752f1d72
|
pipeline host pcr access
|
2012-12-06 14:22:07 -08:00 |
|
Andrew Waterman
|
4dda38204f
|
fix d$ reset bug
|
2012-12-06 03:13:22 -08:00 |
|
Andrew Waterman
|
290d3d226c
|
fix AMO and store bypass bugs
thanks, torture tester
|
2012-12-06 02:07:52 -08:00 |
|
Andrew Waterman
|
4608660f6e
|
torture revealed a couple bugs
FP loads/stores with certain negative offsets could cause illegal rounding
mode traps, and x's were cropping up in situations that are benign in HW.
|
2012-12-04 05:57:53 -08:00 |
|
Andrew Waterman
|
90cae54ac4
|
fix D$ read/write concurrency bug
|
2012-11-27 02:42:27 -08:00 |
|
Andrew Waterman
|
9c857b83f0
|
refactor PCR file
|
2012-11-27 01:28:06 -08:00 |
|
Andrew Waterman
|
64674d4d39
|
clean up PTW and support PADDR_BITS < VADDR_BITS
|
2012-11-26 20:38:45 -08:00 |
|
Andrew Waterman
|
608f65e716
|
don't wastefully read 2x the bits from D$ RAMs
|
2012-11-26 20:34:30 -08:00 |
|
Andrew Waterman
|
352bb464b5
|
clock gate X/M and M/W store data registers
|
2012-11-26 20:33:41 -08:00 |
|
Andrew Waterman
|
8a6ff5f9aa
|
fix D$ writeback bug
I swear I did this last week... perhaps I am finally losing it!
|
2012-11-25 19:46:48 -08:00 |
|
Andrew Waterman
|
de2f28193a
|
get rid of more global constants
|
2012-11-25 04:24:25 -08:00 |
|
Andrew Waterman
|
c036cdc1ea
|
add option for 2-cycle load-use delay
|
2012-11-24 22:01:08 -08:00 |
|
Andrew Waterman
|
b514c7b725
|
clean up I$ parity code
|
2012-11-24 22:00:43 -08:00 |
|
Andrew Waterman
|
55082e45c4
|
add AVec, which automatically infers element type
should consider modifying Vec as such
|
2012-11-24 18:19:28 -08:00 |
|
Andrew Waterman
|
2b26082132
|
use 1r1w ram for tags; merge tags & permissions
setting the dirty bit now allocates an MSHR (to reuse the existing datapath)
|
2012-11-20 04:09:26 -08:00 |
|
Andrew Waterman
|
72f94d1141
|
fix virtual address sign extension detection
|
2012-11-20 04:06:57 -08:00 |
|
Andrew Waterman
|
30038bda8a
|
bypass stores to subsequent loads
since we handle subword stores as RMW operations, this occurs frequently
|
2012-11-20 01:33:32 -08:00 |
|
Yunsup Lee
|
395e4e3dd6
|
andrew'x fix for D$ corner case in writeback->abort->probe
|
2012-11-18 03:11:06 -08:00 |
|
Yunsup Lee
|
06eeb90e2a
|
vector unit interfaces to the new D$
|
2012-11-17 20:07:41 -08:00 |
|
Yunsup Lee
|
81d711e892
|
fix D$ bug; now D$ doesn't respond to prefetches
|
2012-11-17 20:06:13 -08:00 |
|
Andrew Waterman
|
29bc361d6c
|
remove global constants; disentangle hwacha a bit
|
2012-11-17 17:24:08 -08:00 |
|
Andrew Waterman
|
5a7777fe4d
|
clock gate integer datapath more aggressively
|
2012-11-17 06:48:44 -08:00 |
|
Andrew Waterman
|
cc067026a2
|
pipeline D$ response -> FPU regfile
|
2012-11-17 06:48:11 -08:00 |
|
Andrew Waterman
|
e68b039133
|
fix misc. D$ control bugs
|
2012-11-17 06:47:27 -08:00 |
|
Andrew Waterman
|
dad7b71062
|
provide cmd/addr with cache response
|
2012-11-16 21:26:12 -08:00 |
|
Andrew Waterman
|
cb8ac73045
|
provide store data with cache response
|
2012-11-16 21:15:13 -08:00 |
|
Andrew Waterman
|
9e010beffe
|
fix D$ refill bug
|
2012-11-16 21:05:29 -08:00 |
|
Andrew Waterman
|
8dce89703a
|
new D$ with better QoR and AMO pipelining
Vector unit is disabled because nack handling needs to be fixed.
|
2012-11-16 02:39:33 -08:00 |
|
Andrew Waterman
|
a90a1790a5
|
improve tlb qor
|
2012-11-16 01:59:38 -08:00 |
|
Andrew Waterman
|
ff8c736d94
|
move icache invalidate out of request bundle
|
2012-11-16 01:55:45 -08:00 |
|
Andrew Waterman
|
6d10115b19
|
fix D$ tag width
|
2012-11-15 16:46:39 -08:00 |
|
Yunsup Lee
|
be1980dd2d
|
refactored vector queue interface
|
2012-11-07 01:15:33 -08:00 |
|
Yunsup Lee
|
8764fe786a
|
refactored vector tlb
|
2012-11-06 23:53:52 -08:00 |
|
Yunsup Lee
|
9a02298f6f
|
andrew's fix for tlb lockup
|
2012-11-06 23:52:58 -08:00 |
|
Andrew Waterman
|
4d1ca8ba3a
|
remove more global consts; refactor DTLBs
D$ now contains DTLB. provide full VAddr with initial request.
VU now has its own DTLBs.
|
2012-11-06 08:13:44 -08:00 |
|
Andrew Waterman
|
e76892f758
|
remove more global constants
|
2012-11-06 02:55:45 -08:00 |
|
Andrew Waterman
|
c5b93798fb
|
factor out more global constants
|
2012-11-05 23:52:32 -08:00 |
|
Yunsup Lee
|
ee081d1671
|
modify code to fix UFix := Bits error
|
2012-11-05 01:35:55 -08:00 |
|
Yunsup Lee
|
2a25307a8f
|
revamp the vector unit with the new frontend
|
2012-11-05 01:35:55 -08:00 |
|
Andrew Waterman
|
5b20ed71be
|
move rd=0 check into bypass logic
before, the check was in the write enable logic, but moving it obviated
an awkward corner case for mtpcr with rd=0.
|
2012-11-05 01:30:57 -08:00 |
|
Andrew Waterman
|
5e103054fd
|
fix bug in quine mccluskey
|
2012-11-05 00:28:25 -08:00 |
|
Andrew Waterman
|
e9eca6a95d
|
refactor I$ config; remove Top class
|
2012-11-04 16:59:36 -08:00 |
|
Andrew Waterman
|
7380c9fe60
|
aggressively clock gate int and fp datapaths
|
2012-11-04 16:40:14 -08:00 |
|
Andrew Waterman
|
bd2d61de03
|
use 8T SRAM for I$; gate clock more aggressively
|
2012-11-04 16:39:25 -08:00 |
|
Andrew Waterman
|
fedee6c67d
|
add generic error correcting codes
|
2012-10-30 01:03:47 -07:00 |
|
Andrew Waterman
|
5773cbb68a
|
rejigger htif to use UncoreConfiguration
|
2012-10-18 17:26:03 -07:00 |
|
Henry Cook
|
e2eb7ce8e9
|
Cleanup git incompetence
|
2012-10-16 16:54:58 -07:00 |
|
Henry Cook
|
88ac5af181
|
Merged consts-as-traits
|
2012-10-16 16:32:35 -07:00 |
|
Henry Cook
|
6cff1c13d8
|
Refer to traits moved to uncore, add UncoreConfiguration to top
|
2012-10-16 14:22:23 -07:00 |
|
Andrew Waterman
|
b9a2af697d
|
turn off HAVE_VEC as it's currently broken
the new I$/frontend needs to be integrated
|
2012-10-16 07:38:19 -07:00 |
|
Andrew Waterman
|
0a640f2cc6
|
make DecodeLogic deterministic (hopefully)
|
2012-10-16 04:51:21 -07:00 |
|
Andrew Waterman
|
5821900329
|
don't refetch from I$ if on same 16B block
|
2012-10-16 02:24:38 -07:00 |
|
Andrew Waterman
|
b955985b38
|
improve divider QoR
|
2012-10-16 02:24:38 -07:00 |
|
Andrew Waterman
|
197154c485
|
use BTB for JALR
|
2012-10-16 02:24:37 -07:00 |
|
Andrew Waterman
|
fc648d13a1
|
remove old Mux1H; add implicit conversions
|
2012-10-16 02:24:37 -07:00 |
|
Andrew Waterman
|
661f8e635b
|
merge I$, ITLB, BTB into Frontend
|
2012-10-16 02:24:37 -07:00 |
|
Andrew Waterman
|
fcd69dba98
|
add optional early-out to mul/div
|
2012-10-16 02:24:37 -07:00 |
|
Andrew Waterman
|
27ddff1adb
|
simplify and improve multiplier
|
2012-10-16 02:24:37 -07:00 |
|
Henry Cook
|
8970b635b2
|
improvements to implicit RocketConfiguration parameter
|
2012-10-15 16:29:49 -07:00 |
|
Henry Cook
|
a7a4e65690
|
Initial verison of reading config from files
|
2012-10-15 16:05:50 -07:00 |
|
Henry Cook
|
5d2a470215
|
all rocket-specific arbiters in one file and refactored traits slightly
|
2012-10-15 16:05:32 -07:00 |
|
Huy Vo
|
1864e41361
|
memserdes + slowio out of rocket and into uncore
|
2012-10-10 15:25:24 -07:00 |
|
Huy Vo
|
fe21142972
|
fixed memdessert unpacking
|
2012-10-09 13:03:17 -07:00 |
|
Henry Cook
|
9025d0610c
|
first pass at configuration object passed as implicit parameter
|
2012-10-07 22:37:29 -07:00 |
|
Henry Cook
|
dfdfddebe8
|
constants as traits
|
2012-10-07 22:20:03 -07:00 |
|
Henry Cook
|
b5ff436092
|
decode constant object split into multiple objects
|
2012-10-05 15:50:42 -07:00 |
|
Andrew Waterman
|
ed8cc4a1cf
|
eliminate D$ probe->WB critical path
|
2012-10-04 09:05:14 -07:00 |
|
Huy Vo
|
e909093f37
|
factoring out uncore into separate uncore repo
|
2012-10-01 16:08:41 -07:00 |
|
Henry Cook
|
b9a9664de5
|
uncore and rocket changes for new xact types
|
2012-10-01 10:47:36 -07:00 |
|
Huy Vo
|
d9cb96c0ae
|
factored out common stuff to ChiselUtil
|
2012-09-27 22:53:34 -07:00 |
|
Andrew Waterman
|
667b4ee858
|
remove Queue flush port (override reset instead)
|
2012-08-22 13:39:19 -07:00 |
|
Andrew Waterman
|
d4a001b867
|
add PriorityMux; use to implement PriorityEncoder
|
2012-08-22 13:38:25 -07:00 |
|
Andrew Waterman
|
743e032f06
|
generalize interface to DecodeLogic
|
2012-08-22 13:38:07 -07:00 |
|
Andrew Waterman
|
0f20771664
|
rename queue to Queue
fixes build with case-insensitive file system
|
2012-08-08 22:11:59 -07:00 |
|
Andrew Waterman
|
897a4e349b
|
fix some LLC control bugs
|
2012-08-06 17:10:04 -07:00 |
|
Andrew Waterman
|
e9c35b4923
|
ameliorate DTLB kill->rdy critical path
|
2012-08-06 17:05:05 -07:00 |
|
Andrew Waterman
|
b94e6915ab
|
refactor IPIs; use new tohost/fromhost protocol
|
2012-08-03 19:00:34 -07:00 |
|
Andrew Waterman
|
6510f020c7
|
fix deadlock in coherence hub
|
2012-08-03 19:00:03 -07:00 |
|
Andrew Waterman
|
e3726c4db0
|
fix control bug in LLC
structural hazard on tag ram caused deadlock
|
2012-08-03 18:59:37 -07:00 |
|
Andrew Waterman
|
def913096e
|
pipeline LLC further
|
2012-07-31 17:45:14 -07:00 |
|
Andrew Waterman
|
3a8f3e0de5
|
further pipeline the LLC
|
2012-07-30 20:12:11 -07:00 |
|
Andrew Waterman
|
80c243469e
|
add flow queues and skid buffers
hopefully they work
|
2012-07-30 18:47:12 -07:00 |
|
Andrew Waterman
|
be4fa936dd
|
fix PriorityEncoderOH bug
|
2012-07-30 18:28:54 -07:00 |
|
Andrew Waterman
|
2ec76390e3
|
improve PriorityEncoderOH and add Counter util
|
2012-07-30 16:06:55 -07:00 |
|
Yunsup Lee
|
2af84f994a
|
remove reset pin on llc
|
2012-07-28 21:14:51 -07:00 |
|
Yunsup Lee
|
0a1cd1175c
|
add reset pin to llc
|
2012-07-27 18:44:39 -07:00 |
|
Huy Vo
|
db91c4cf6c
|
hwacha
|
2012-07-27 18:13:20 -07:00 |
|
Huy Vo
|
32a16d183f
|
consts file doesn't depend on WIDTH_PVFB if HAVE_PVFB == false
|
2012-07-27 18:13:20 -07:00 |
|
Andrew Waterman
|
130fa95ed6
|
expand HTIF's PCR register space
|
2012-07-27 14:52:39 -07:00 |
|
Andrew Waterman
|
7778802395
|
reduce number of outstanding transactions
|
2012-07-26 14:51:41 -07:00 |
|
Andrew Waterman
|
9c50621a19
|
remove chip-specific uncore gunk
|
2012-07-26 03:26:52 -07:00 |
|
Andrew Waterman
|
a5bea4364f
|
memory system bug fixes
|
2012-07-26 00:05:21 -07:00 |
|
Yunsup Lee
|
3a2b305ddf
|
change htif width to 16
|
2012-07-25 17:25:50 -07:00 |
|
Andrew Waterman
|
177dbdadd9
|
merge HTIF port and backup memory port
|
2012-07-25 00:18:02 -07:00 |
|
Yunsup Lee
|
309193dd07
|
change llc size
|
2012-07-24 14:10:29 -07:00 |
|
Yunsup Lee
|
6541cf22a4
|
fix bug in coherence hub, respect xact_rep.ready
|
2012-07-23 20:56:55 -07:00 |
|
Yunsup Lee
|
f4e3e72ad1
|
hoist HTIF_WIDTH out to consts
|
2012-07-23 17:30:04 -07:00 |
|
Andrew Waterman
|
a21c355114
|
fix htif split request/response
|
2012-07-23 17:15:16 -07:00 |
|
Andrew Waterman
|
938effc053
|
don't dequeue probe queue during reset
|
2012-07-22 21:05:52 -07:00 |
|
Yunsup Lee
|
379f021359
|
change ioHTIF interface between the tile/uncore boundary to cope with asynchrony
|
2012-07-22 18:26:02 -07:00 |
|
Yunsup Lee
|
c892950bf1
|
hoist out uncore as its own component
|
2012-07-22 17:48:17 -07:00 |
|
Huy Vo
|
0a97d6ab4d
|
type casting
|
2012-07-18 13:03:35 -07:00 |
|
Andrew Waterman
|
f42c6afed2
|
decouple all interfaces between tile and top
also, add an "incoherent" bit to tilelink to indicate no probes needed
|
2012-07-17 22:55:40 -07:00 |
|
Andrew Waterman
|
4e44ed7400
|
allow back pressure on IPI requests
|
2012-07-17 22:55:40 -07:00 |
|
Yunsup Lee
|
f633a55722
|
fix dcache tag array size
|
2012-07-16 22:19:03 -07:00 |
|
Andrew Waterman
|
e496cd7584
|
use Mem to implement queues to speed things up
|
2012-07-13 21:48:05 -07:00 |
|
Huy Vo
|
fd95159837
|
INPUT/OUTPUT orderring swapped
|
2012-07-12 18:16:57 -07:00 |
|
Andrew Waterman
|
bac82762d3
|
use only one (wide) tag ram for set assoc. caches
|
2012-07-12 14:50:12 -07:00 |
|
Andrew Waterman
|
429fcbed8e
|
fix some LLC bugs
|
2012-07-11 17:56:39 -07:00 |
|
Andrew Waterman
|
f645fb4dd7
|
add L2$
It still has performance bugs but no correctness bugs AFAIK.
|
2012-07-10 05:23:29 -07:00 |
|
Andrew Waterman
|
5035374f36
|
update to new chisel
|
2012-07-08 17:59:41 -07:00 |
|
Andrew Waterman
|
39d198ecdc
|
fix htif handling of large memory reads
|
2012-06-26 19:12:11 -07:00 |
|
Andrew Waterman
|
4e5f874266
|
update to new chisel/hwacha
|
2012-06-08 00:13:14 -07:00 |
|
Huy Vo
|
a99cebb483
|
ioDecoupled -> FIFOIO, ioPipe -> PipeIO
|
2012-06-06 18:22:56 -07:00 |
|
Huy Vo
|
04304fe788
|
moving util out into Chisel standard library
|
2012-06-06 12:51:26 -07:00 |
|
Huy Vo
|
c975c21e44
|
views removed
|
2012-06-06 12:51:26 -07:00 |
|
Andrew Waterman
|
943b6d0616
|
remove debug println
|
2012-06-06 02:48:48 -07:00 |
|
Andrew Waterman
|
7f6319047e
|
update to new scala/chisel/Mem
|
2012-06-06 02:47:22 -07:00 |
|
Huy Vo
|
7408c9ab69
|
removing wires
|
2012-05-24 10:42:39 -07:00 |
|
Huy Vo
|
181b20d69c
|
working vec unit with pvfb
|
2012-05-24 10:38:14 -07:00 |
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