Howard Mao
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2723b2f515
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fix issues in SimpleHellaCacheIF and document the changes
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2016-07-18 17:02:47 -07:00 |
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Andrew Waterman
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d78f1aacd0
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Clean up some zero-width wire cases using UInt.extract
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2016-07-14 22:08:01 -07:00 |
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Howard Mao
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f7b392306e
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make sure SimpleHellaCacheIF can work with blocking DCache
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2016-07-07 18:59:23 -07:00 |
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Andrew Waterman
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25fdabdd59
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Don't implicitly create Vecs, since they're heavyweight
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2016-07-06 01:41:31 -07:00 |
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Howard Mao
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a9e0a5e2df
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changes to imports after uncore refactor
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2016-06-28 14:09:31 -07:00 |
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Andrew Waterman
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60bddddfe6
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Merge sptbr and sasid
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2016-06-17 18:29:05 -07:00 |
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Colin Schmidt
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2c325151bf
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pass invalidate_lr through simple cache interface (#45)
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2016-06-09 17:22:36 -07:00 |
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Andrew Waterman
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51379621d6
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Flush blocking D$ on FENCE.I
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2016-05-31 19:27:28 -07:00 |
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Andrew Waterman
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0c50bfcfb3
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Work around more zero-width wire cases
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2016-05-25 21:47:48 -07:00 |
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Wesley W. Terpstra
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e19c5e5d2c
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IOMSHR: support atomic operations
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2016-05-24 15:00:50 -07:00 |
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Howard Mao
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f228309bd1
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add assertion to make sure SimpleHellaCacheIF doesn't get exception
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2016-05-20 16:30:27 -07:00 |
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Andrew Waterman
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4aef567a80
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Fix MMIO bug: replay_next wasn't set
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2016-05-13 17:59:53 -07:00 |
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Albert Ou
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0ff4fd0ccd
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Fix IOMSHR to send finishes for stores
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2016-04-30 22:20:29 -07:00 |
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Andrew Waterman
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fe8c91f620
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Fix IOMSHR state machine bug
Sending the finish too early causes the CPU response to get dropped.
attn @zhemao
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2016-04-26 15:32:25 -07:00 |
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Andrew Waterman
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d93677a343
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Support larger cache sets when not using VM
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2016-04-26 15:31:32 -07:00 |
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Howard Mao
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b7527268bb
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use address map instead of MMIOBase to find size of memory
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2016-04-21 18:44:39 -07:00 |
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Andrew Waterman
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51e0870e23
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Separate I$ and D$ interface signals that span clock cycles
For example, Decopuled[HellaCacheReq].bits.kill doesn't make sense,
since it doesn't come the same cycle as ready/valid.
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2016-04-01 19:30:39 -07:00 |
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Andrew Waterman
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72f7f71eb5
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No need to allow finishes to be sent in s_refill_resp state
This is a hold-over from when writebacks needed finish messages.
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2016-04-01 16:19:57 -07:00 |
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Henry Cook
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78bc18736e
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LRSC startvation fix: HellaCache generates its own Finish messages again.
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2016-04-01 16:04:25 -07:00 |
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Henry Cook
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54dd82ff76
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bugfix for WB data buffer
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2016-03-31 17:53:49 -07:00 |
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Christopher Celio
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1792d01ce1
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fix leaky assert in nbdcache
Squash of #33.
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2016-03-31 15:56:14 -07:00 |
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Andrew Waterman
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1ae6d09751
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Slightly ameliorate D$->I$ critical path via scoreboard
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2016-03-25 15:29:32 -07:00 |
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Andrew Waterman
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8d1ba4d1ec
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Remove hard-coded XLEN values from D$
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2016-03-24 14:52:12 -07:00 |
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Andrew Waterman
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7ae44d4905
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Add RV32 support
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2016-03-10 17:32:00 -08:00 |
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Howard Mao
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7937fbf074
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fix number of IOMSHRs at 1
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2016-01-29 14:51:56 -08:00 |
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Howard Mao
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77e068c153
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fix Chisel3 compat issue in SimpleHellaCacheIF
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2016-01-14 22:42:44 -08:00 |
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Howard Mao
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120361226d
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fix more Chisel3 deprecations
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2016-01-14 14:46:31 -08:00 |
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Andrew Waterman
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6d1bf5c014
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Use generic LoadGen/StoreGen
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2015-11-24 18:13:33 -08:00 |
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Howard Mao
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b0a06a77db
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fix a few Chisel3 compat issues
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2015-11-20 13:33:15 -08:00 |
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Howard Mao
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19daee10f0
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use default constructors for IOMSHR acquire construction
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2015-11-12 15:54:05 -08:00 |
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jackkoenig
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1e259a55da
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Fix SimpleHellaCacheIF assumption about receiving rejected request back 2 cycles later
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2015-11-08 21:16:31 -08:00 |
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Henry Cook
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4f8468b60f
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depend on external cde library
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2015-10-21 18:19:23 -07:00 |
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Howard Mao
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0b7c828b5d
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go back to using standard LockingArbiter
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2015-10-21 09:15:51 -07:00 |
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Howard Mao
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c68d9f8137
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make ProbeUnit state machine easier to understand
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2015-10-20 23:25:23 -07:00 |
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Henry Cook
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1a1185be3f
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Vectorize ROCC and Tile memory interfaces
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2015-10-20 15:02:24 -07:00 |
|
Henry Cook
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6f8997bee9
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Minor refactor of StoreGen/AMOALU.
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2015-10-16 19:12:46 -07:00 |
|
Henry Cook
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68cb54bc68
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refactor tilelink params
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2015-10-14 12:14:36 -07:00 |
|
Henry Cook
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84576650b5
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Removed all traces of params
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2015-10-05 21:48:05 -07:00 |
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Howard Mao
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19656e4abe
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make sure to generate release from clean coh state on probe miss
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2015-09-30 16:58:18 -07:00 |
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Andrew Waterman
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833909a2b5
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Chisel3 compatibility fixes
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2015-09-30 14:36:26 -07:00 |
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Howard Mao
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2f3d15675c
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fix DataArray writemask in L1D
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2015-09-28 16:02:39 -07:00 |
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Andrew Waterman
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b93a94597c
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Remove needless control logic
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2015-09-27 13:31:52 -07:00 |
|
Andrew Waterman
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c3fff12ff0
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Revert "replace remaining uses of Vec.fill"
This reverts commit f7a0d125e83f8ca59d9913bb1db79cef5a6d344a.
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2015-09-25 17:09:06 -07:00 |
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Andrew Waterman
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0bfb2962a6
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Assume coh.isRead returns true for store-conditional
This requires an uncore update.
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2015-09-25 15:26:11 -07:00 |
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Howard Mao
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a66bdb1956
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replace remaining uses of Vec.fill
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2015-09-24 17:53:26 -07:00 |
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Howard Mao
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9eb988a4c6
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make sure access to invalid physical address treated as exception
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2015-09-22 10:11:43 -07:00 |
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Howard Mao
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16c748576a
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don't mux data_word_bypass between IOMSHR and cache
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2015-09-22 10:10:57 -07:00 |
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Howard Mao
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382faba4a6
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Implement bypassing L1 data cache for MMIO
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2015-09-22 10:10:57 -07:00 |
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Andrew Waterman
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78b2e947de
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Chisel3 compatibility fixes
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2015-09-11 15:43:07 -07:00 |
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Andrew Waterman
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546205b174
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Chisel3 compatibility: use >>Int instead of >>UInt
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2015-08-05 15:29:03 -07:00 |
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