Yunsup Lee
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c036fff79c
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fix id interrupt signal
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2012-03-19 15:13:57 -07:00 |
|
Yunsup Lee
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0edea00166
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now HAVE_VEC is true, since it passes the emulator
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2012-03-19 03:10:00 -07:00 |
|
Yunsup Lee
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264732556f
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fixes to match verilog X semantics
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2012-03-19 03:10:00 -07:00 |
|
Andrew Waterman
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bd27d0fab2
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can now take interrupts on stalled instructions
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2012-03-19 01:02:06 -07:00 |
|
Andrew Waterman
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2ed0be65f9
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fix RRArbiter
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2012-03-19 00:19:33 -07:00 |
|
Yunsup Lee
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ba06cd953e
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add chosen
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2012-03-18 20:43:17 -07:00 |
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Andrew Waterman
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c4a91303fb
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update vector fence names and encoding
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2012-03-18 20:42:38 -07:00 |
|
Yunsup Lee
|
2a01f558ba
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fix unmasked valid bug in ctrl_vec
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2012-03-18 19:55:24 -07:00 |
|
Yunsup Lee
|
98e10ddc3c
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update vector exception instructions
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2012-03-18 16:36:12 -07:00 |
|
Yunsup Lee
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7493d55d3f
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add pf fault handling
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2012-03-18 15:06:39 -07:00 |
|
Yunsup Lee
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62ada5ea9e
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hookup vitlb ptw port
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2012-03-17 23:01:06 -07:00 |
|
Yunsup Lee
|
b793d63182
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no vector interrupt masking
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2012-03-17 23:01:06 -07:00 |
|
Yunsup Lee
|
8a4f95e617
|
changes to xcpt handling
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2012-03-17 17:50:37 -07:00 |
|
Yunsup Lee
|
8c50c81b81
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drop vec_irq_aux pcr register, now everything goes through badvaddr
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2012-03-17 14:03:57 -07:00 |
|
Yunsup Lee
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3b4680a834
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add vitlb exception port
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2012-03-17 14:03:33 -07:00 |
|
Andrew Waterman
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a47eeb9571
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retime D$ bypass into beginning of EX stage
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2012-03-16 18:35:54 -07:00 |
|
Andrew Waterman
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6c26921766
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reduce D$ critical path through page table walker
costs an extra cycle per page table level to resolve a TLB miss. too bad.
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2012-03-16 18:35:54 -07:00 |
|
Yunsup Lee
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d38603a4ee
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change number of tlb entries
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2012-03-16 17:08:03 -07:00 |
|
Andrew Waterman
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e38114e4b0
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fix coherence bug
popping wrong store dependence queue
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2012-03-16 01:24:07 -07:00 |
|
Andrew Waterman
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f0157b9e2a
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fix coherence bug
popping wrong store dependence queue
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2012-03-16 01:24:07 -07:00 |
|
Andrew Waterman
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cfca2d1411
|
clean up cache interfaces; avoid reserved keywords
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2012-03-16 00:44:16 -07:00 |
|
Andrew Waterman
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820884c7e6
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fix probes for smaller cache sizes
address bits (pgidx_bits-1,taglsb) were omitted from tag checks.
|
2012-03-15 23:08:30 -07:00 |
|
Andrew Waterman
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4684171ac6
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fix fence.i for associative caches
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2012-03-15 21:23:21 -07:00 |
|
Andrew Waterman
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3129040bda
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use divided clk for htif. UDPATE YOUR FESVR
by default, we now load programs via a backdoor, because otherwise
it takes too long to simulate.
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2012-03-15 18:36:51 -07:00 |
|
Andrew Waterman
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2b0bc8df2b
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use divided clk for htif. UDPATE YOUR FESVR
by default, we now load programs via a backdoor, because otherwise
it takes too long to simulate.
|
2012-03-15 18:36:51 -07:00 |
|
Yunsup Lee
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ba566f246e
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change icache parameters
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2012-03-15 15:35:12 -07:00 |
|
Yunsup Lee
|
72006160dc
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fix vxcptwait inst bug, it was incorrect when exception_valid was on before do_xcptwait
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2012-03-15 02:10:21 -07:00 |
|
Yunsup Lee
|
f972977da1
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refactored VMU, now uses one skid buffer
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2012-03-15 01:10:17 -07:00 |
|
Henry Cook
|
b5fa86e844
|
4-way associative by default
|
2012-03-14 17:51:12 -07:00 |
|
Andrew Waterman
|
77c405ffa1
|
use broadcast hub and coherent HTIF
|
2012-03-14 16:44:35 -07:00 |
|
Andrew Waterman
|
7dde7099d2
|
use broadcast hub and coherent HTIF
|
2012-03-14 16:44:35 -07:00 |
|
Yunsup Lee
|
b19d783fbd
|
add vector irq handler
|
2012-03-14 14:15:28 -07:00 |
|
Yunsup Lee
|
040d62f372
|
refactored vector exception handling interface
|
2012-03-13 23:45:34 -07:00 |
|
Yunsup Lee
|
b100544b25
|
datapath to read out vector state
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2012-03-13 23:45:34 -07:00 |
|
Yunsup Lee
|
5655dbd5da
|
add vvcfg and vtcfg instructions
|
2012-03-13 23:45:34 -07:00 |
|
Andrew Waterman
|
53cd543d3f
|
fix minor coherence bugs
|
2012-03-13 19:10:54 -07:00 |
|
Andrew Waterman
|
ab6c9350db
|
fix minor coherence bugs
|
2012-03-13 19:10:54 -07:00 |
|
Andrew Waterman
|
53d69d3006
|
parameterize broadcast hub by # of tiles
|
2012-03-13 17:12:01 -07:00 |
|
Andrew Waterman
|
1788c34113
|
parameterize broadcast hub by # of tiles
|
2012-03-13 17:12:01 -07:00 |
|
Andrew Waterman
|
1492457df5
|
add probe replies to HTIF
|
2012-03-13 16:56:47 -07:00 |
|
Andrew Waterman
|
1258f31825
|
add probe unit
|
2012-03-13 16:43:51 -07:00 |
|
Andrew Waterman
|
b0f798962c
|
add probe unit
|
2012-03-13 16:43:51 -07:00 |
|
Huy Vo
|
1b733e7cf0
|
Merge branch 'master' of github.com:ucb-bar/riscv-rocket
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2012-03-13 12:34:39 -07:00 |
|
Huy Vo
|
6e32cc8b20
|
Merge branch 'master' of github.com:ucb-bar/riscv-rocket
|
2012-03-13 12:34:39 -07:00 |
|
Huy Vo
|
fdffb124e3
|
Merge branch 'master' of github.com:ucb-bar/riscv-rocket
|
2012-03-13 12:34:39 -07:00 |
|
Huy Vo
|
6fd1527476
|
fix to rocket vec_dpath, updating makefiles to run xcpt test cases
|
2012-03-13 12:34:02 -07:00 |
|
Henry Cook
|
287bc1c262
|
Further refinement of tag_match/tag_hit signals
|
2012-03-13 11:48:12 -07:00 |
|
Andrew Waterman
|
d76b05bde1
|
fix way selection on D$ write upgrades
|
2012-03-13 02:21:02 -07:00 |
|
Andrew Waterman
|
fd29e00db0
|
support non-power-of-2 queue sizes
need to manually wrap queue pointers.
|
2012-03-13 01:58:28 -07:00 |
|
Henry Cook
|
23c822a82e
|
fix hit logic for amos
|
2012-03-12 22:01:52 -07:00 |
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