Andrew Waterman
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672e904c86
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update to new rocket/uncore
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2012-11-16 02:41:50 -08:00 |
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Andrew Waterman
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8dce89703a
|
new D$ with better QoR and AMO pipelining
Vector unit is disabled because nack handling needs to be fixed.
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2012-11-16 02:39:33 -08:00 |
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Andrew Waterman
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3e6dc35809
|
issue self-probes for uncached read transactions
this facilitates I$ coherence. but it seems like a hack and perhaps
the mechanism should be rethought.
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2012-11-16 02:37:56 -08:00 |
|
Andrew Waterman
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a90a1790a5
|
improve tlb qor
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2012-11-16 01:59:38 -08:00 |
|
Andrew Waterman
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ff8c736d94
|
move icache invalidate out of request bundle
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2012-11-16 01:55:45 -08:00 |
|
Andrew Waterman
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6d10115b19
|
fix D$ tag width
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2012-11-15 16:46:39 -08:00 |
|
Yunsup Lee
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1a91637673
|
refactored vector queue interface
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2012-11-07 01:16:02 -08:00 |
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Yunsup Lee
|
be1980dd2d
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refactored vector queue interface
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2012-11-07 01:15:33 -08:00 |
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Yunsup Lee
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29d4c0b857
|
refactored tlb
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2012-11-06 23:54:14 -08:00 |
|
Yunsup Lee
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8764fe786a
|
refactored vector tlb
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2012-11-06 23:53:52 -08:00 |
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Yunsup Lee
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9a02298f6f
|
andrew's fix for tlb lockup
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2012-11-06 23:52:58 -08:00 |
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Andrew Waterman
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e2afae011a
|
factor out global constants
|
2012-11-06 08:18:40 -08:00 |
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Andrew Waterman
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4d1ca8ba3a
|
remove more global consts; refactor DTLBs
D$ now contains DTLB. provide full VAddr with initial request.
VU now has its own DTLBs.
|
2012-11-06 08:13:44 -08:00 |
|
Andrew Waterman
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e76892f758
|
remove more global constants
|
2012-11-06 02:55:45 -08:00 |
|
Andrew Waterman
|
c5b93798fb
|
factor out more global constants
|
2012-11-05 23:52:32 -08:00 |
|
Yunsup Lee
|
1305372ce7
|
refactor flush logic
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2012-11-05 23:01:08 -08:00 |
|
Yunsup Lee
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9844ba1c1d
|
revamp the vector unit with the new frontend
HAVE_PVFB is still broken, we need to multi-thread the frontend
|
2012-11-05 01:44:02 -08:00 |
|
Yunsup Lee
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ee081d1671
|
modify code to fix UFix := Bits error
|
2012-11-05 01:35:55 -08:00 |
|
Yunsup Lee
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2a25307a8f
|
revamp the vector unit with the new frontend
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2012-11-05 01:35:55 -08:00 |
|
Andrew Waterman
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5b20ed71be
|
move rd=0 check into bypass logic
before, the check was in the write enable logic, but moving it obviated
an awkward corner case for mtpcr with rd=0.
|
2012-11-05 01:30:57 -08:00 |
|
Andrew Waterman
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5e103054fd
|
fix bug in quine mccluskey
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2012-11-05 00:28:25 -08:00 |
|
Yunsup Lee
|
dd6ee2571d
|
add vector vm tests
|
2012-11-04 19:29:56 -08:00 |
|
Andrew Waterman
|
0c372fc9ec
|
refactor I$ config into RocketConfiguration
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2012-11-04 17:00:19 -08:00 |
|
Andrew Waterman
|
e9eca6a95d
|
refactor I$ config; remove Top class
|
2012-11-04 16:59:36 -08:00 |
|
Andrew Waterman
|
4ed2d614a2
|
update to new rocket; retime fpu in dc-syn
|
2012-11-04 16:43:02 -08:00 |
|
Andrew Waterman
|
7380c9fe60
|
aggressively clock gate int and fp datapaths
|
2012-11-04 16:40:14 -08:00 |
|
Andrew Waterman
|
bd2d61de03
|
use 8T SRAM for I$; gate clock more aggressively
|
2012-11-04 16:39:25 -08:00 |
|
Andrew Waterman
|
fedee6c67d
|
add generic error correcting codes
|
2012-10-30 01:03:47 -07:00 |
|
Henry Cook
|
0cd0f8a9db
|
Initial version of migratory protocol
|
2012-10-23 18:01:53 -07:00 |
|
Henry Cook
|
538b23c223
|
Initial version of using sbt tasks to elaborate chisel source and invoke backends' makefiles
|
2012-10-23 12:52:59 -07:00 |
|
Henry Cook
|
17d2bd8926
|
Initial version of sbt tasks (elaborate task with no parameters)
|
2012-10-23 12:52:00 -07:00 |
|
Yunsup Lee
|
3edc1f42aa
|
revamp the backup memory link in the vlsi backend
|
2012-10-23 03:31:34 -07:00 |
|
Andrew Waterman
|
367b5489d1
|
first crack at continuous compilation/testing flow
try it out: cd emulator; make test
|
2012-10-19 04:09:07 -07:00 |
|
Andrew Waterman
|
1ad928cfe2
|
directly integrate dramsim build
also, build it as a static library to simplify dependencies
|
2012-10-18 18:59:37 -07:00 |
|
Andrew Waterman
|
edf0eeed01
|
integrate updated rocket/uncore
|
2012-10-18 17:51:41 -07:00 |
|
Andrew Waterman
|
5773cbb68a
|
rejigger htif to use UncoreConfiguration
|
2012-10-18 17:26:03 -07:00 |
|
Andrew Waterman
|
2aecb0024f
|
UncoreConfiguration now contains coherence policy
|
2012-10-18 16:57:28 -07:00 |
|
Andrew Waterman
|
ffda0e41a9
|
parameterize width of MemSerdes/MemDesser
|
2012-10-18 16:56:36 -07:00 |
|
Henry Cook
|
e2eb7ce8e9
|
Cleanup git incompetence
|
2012-10-16 16:54:58 -07:00 |
|
Henry Cook
|
88ac5af181
|
Merged consts-as-traits
|
2012-10-16 16:32:35 -07:00 |
|
Henry Cook
|
9df5cfa552
|
Factored out tilelink classes
|
2012-10-16 14:26:33 -07:00 |
|
Henry Cook
|
6cff1c13d8
|
Refer to traits moved to uncore, add UncoreConfiguration to top
|
2012-10-16 14:22:23 -07:00 |
|
Henry Cook
|
8509cda813
|
Refined traits for use with rocket asserts, added UncoreConfiguration to handle ntiles
|
2012-10-16 13:58:18 -07:00 |
|
Miquel Moreto
|
6d49dc51a0
|
Fixed emulator Makefile + extra info in the README file
|
2012-10-16 11:06:48 -07:00 |
|
Andrew Waterman
|
b9a2af697d
|
turn off HAVE_VEC as it's currently broken
the new I$/frontend needs to be integrated
|
2012-10-16 07:38:19 -07:00 |
|
Andrew Waterman
|
0a640f2cc6
|
make DecodeLogic deterministic (hopefully)
|
2012-10-16 04:51:21 -07:00 |
|
Andrew Waterman
|
5821900329
|
don't refetch from I$ if on same 16B block
|
2012-10-16 02:24:38 -07:00 |
|
Andrew Waterman
|
b955985b38
|
improve divider QoR
|
2012-10-16 02:24:38 -07:00 |
|
Andrew Waterman
|
197154c485
|
use BTB for JALR
|
2012-10-16 02:24:37 -07:00 |
|
Andrew Waterman
|
fc648d13a1
|
remove old Mux1H; add implicit conversions
|
2012-10-16 02:24:37 -07:00 |
|