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Author SHA1 Message Date
Wesley W. Terpstra 45189c3e30 tilelink: CacheCork now supports errors and BtoT upgrade 
- Acquire.BtoT succeeds with toT instantly
- AccessAckData.error causes Grant.toN.error
 2017-07-27 18:38:13 -07:00
Wesley W. Terpstra 2e4f1611ed tilelink: Error device supports Acquire 
We need this if we want to divert traffic to it from a TL-C slave.
 2017-07-27 18:32:58 -07:00
Wesley W. Terpstra 651da73d89 tilelink: it is now legal to support Acquire for UNCACHED regions 
These cases exist:
  GET_EFFECTS, PUT_EFFECTS, UNCACHEABLE && !supportsAcquire: MMIO
  UNCACHED && !supportsAcquire: speculation ok and may be cached
  UNCACHED && supportsAcquire: LLC/CacheCork applied (slave never probes)
  CACHED, TRACKED && supportsAcquire: slave might probe
 2017-07-27 11:11:22 -07:00
Wesley W. TerpstraandAndrew Waterman 0ab5cb67b3 tilelink: fix RAMModel handling of AMOs on early source reuse (#897) 2017-07-27 11:07:13 -07:00
Wesley W. TerpstraandGitHub 9804bdc34e tilelink: remove obsolete addr_lo signal (#895) 
When we first implemented TL, we thought this was helpful, because
it made WidthWidgets stateless in all cases. However, it put too
much burden on all other masters and slaves, none of which benefitted
from this signal. Furthermore, even with addr_lo, WidthWidgets were
information lossy because when they widen, they have no information
about what to fill in the new high bits of addr_lo.
 2017-07-26 16:01:21 -07:00
Wesley W. TerpstraandGitHub 3cceb866cf Merge pull request #896 from freechipsproject/fuzzer-rage 
Fuzzer rage
 2017-07-26 16:01:07 -07:00
Wesley W. Terpstra d096d5d1c4 tilelink: fix AtomicAutomata bug wrt early source reuse 
The new fuzzer already found it's first victim.
 2017-07-26 12:52:29 -07:00
Wesley W. Terpstra 6550ae2e31 tilelink: increase Fuzzer source reuse aggression 2017-07-26 12:37:31 -07:00
Wesley W. Terpstra 1efdca106c tilelink: RAMModel support early reuse of source 2017-07-26 12:37:31 -07:00
Wesley W. Terpstra 138276fd87 tilelink: SourceShrinker should work also for 0 latency 2017-07-26 12:37:31 -07:00
Wesley W. TerpstraandGitHub f02c921d0f Merge pull request #893 from freechipsproject/width-update 
Width widget enhancements
 2017-07-26 12:35:51 -07:00
Wesley W. Terpstra b2edca2a6b tilelink: cut WidthWidget from dependency on addr_lo 2017-07-26 10:31:09 -07:00
Wesley W. Terpstra ede87c1f73 tilelink: rewrite WidthWidget beat splitter 
- split the data based on the address, not the mask
  (the first version of TileLink did not have low address bits)
- the dependency on addr_lo is now exposed and easy to replace
 2017-07-26 10:24:16 -07:00
Wesley W. Terpstra 0f5065fbf3 tilelink: WidthWidget rewrite beat merging 
- errors are properly OR reduced
- registers latched only as needed (was previously a shift register)
- combines beats without inspecting address (removes addr_lo dependency)
 2017-07-26 10:24:12 -07:00
Wesley W. TerpstraandGitHub f0ffb7e31e tilelink: initialize toggle in Fragmenter (#894) 
No strictly necessary, because the initial value does not matter, but good hygiene since it drives a cycle of logic.
 2017-07-26 10:21:31 -07:00
Wesley W. TerpstraandGitHub c2b8b08461 tilelink: fix Fragmenter source re-use bug (#888) 
Consider the following waveform for two 4-beat bursts:
---A----A------------
-------D-----DDD-DDDD
Under TL rules, the second A can use the same source as the first A,
because the source is released for reuse on the first response beat.

However, if we fragment the requests, it looks like this:
---3210-3210---------
-------3-----210-3210
... now we've broken the rules because 210 are twice inflight.

To solve this, we alternate an a.source bit every time D completes a txn.
 2017-07-25 16:23:55 -07:00
Wesley W. TerpstraandGitHub 68ed055f6d chiplink: adjust bus view to include the splitter (#886) 2017-07-24 21:41:17 -07:00
Wesley W. TerpstraandGitHub 8d793daf9c Merge pull request #876 from freechipsproject/sq-helper 
ShiftQueue: support constant propagation
 2017-07-18 16:30:23 -07:00
Wesley W. Terpstra a9c58e9d9f diplomacy: support creating ShiftQueues as well 2017-07-18 14:57:02 -07:00
Wesley W. Terpstra c0a3bb58e9 ShiftQueue: use Vec of Bool to support constant prop of enq.valid 2017-07-18 14:56:59 -07:00
Wesley W. TerpstraandGitHub 416629b3bf tilelink: FIFOFixer should fix no domain => domain cases (#873) 2017-07-17 22:32:17 -07:00
Wesley W. TerpstraandGitHub d09a985729 zero: fix attachment in multichannel case (#870) 2017-07-17 21:48:31 -07:00
Wesley W. TerpstraandGitHub fc75ada577 tilelink: Monitor should report line numbers of connection that failed (#872) 2017-07-17 21:29:14 -07:00
Wesley W. TerpstraandGitHub 16e8709144 tilelink: it is now legal to have errors on {Release,Hint}Ack (#864) 2017-07-14 16:13:30 -07:00
Wesley W. TerpstraandGitHub b7f1ba3428 tilelink: FIFOFixer must support null cases (#860) 
In particular, it is ok if no slaves actually need FIFO fixing.
It is also ok if none of those fixed are FIFO.
 2017-07-12 22:20:31 -07:00
Wesley W. TerpstraandGitHub 0053a060ae Merge pull request #859 from freechipsproject/fifo-fixer-configable 
Fifo fixer configable
 2017-07-12 19:44:23 -07:00
Wesley W. Terpstra 4eface8a9e rocket: do not require FIFO order for memory-like regions 2017-07-12 17:39:00 -07:00
Wesley W. Terpstra 09b9d33a9a tilelink: FIFOFixer now has a policy parameter 2017-07-12 17:38:55 -07:00
Wesley W. Terpstra b363a94480 diplomacy: add a new UNCACHEABLE RegionType 2017-07-12 16:31:50 -07:00
Wesley W. Terpstra c8a7648169 diplomacy: only evaluate a Nexus node's map function once 2017-07-12 16:20:55 -07:00
Wesley W. TerpstraandGitHub af3976aa67 regmapper: add byte-sized RegField helper function (#854) 2017-07-10 21:08:02 -07:00
Wesley W. TerpstraandGitHub 29f5f77817 Merge pull request #853 from freechipsproject/sram-errors 
SRAM errors
 2017-07-07 22:44:28 -07:00
Wesley W. Terpstra 5db0e770d5 tilelink: TestSRAM can emulate incompletely populated memory 2017-07-07 21:40:40 -07:00
Wesley W. Terpstra 702143eb33 tilelink: SRAM can emulate incompletely populated memory 2017-07-07 21:40:40 -07:00
Wesley W. Terpstra 9310a33e77 apb: SRAM can emulate incompletely populated memory 2017-07-07 21:40:40 -07:00
Wesley W. Terpstra 28fbf1af8e ahb: SRAM can emulate incompletely populated memory 2017-07-07 21:40:39 -07:00
Wesley W. Terpstra df44b23956 axi4: SRAM can emulate incompletely populated memory 2017-07-07 21:40:39 -07:00
Wesley W. Terpstra b2cc4b99ed tilelink: TestSRAM reports errors on illegal access 2017-07-07 21:40:36 -07:00
Wesley W. Terpstra e8cb6dafd3 tilelink: SRAM reports errors on illegal access 2017-07-07 21:15:36 -07:00
Wesley W. Terpstra f1fb3be603 ahb: SRAM reports errors on illegal access 2017-07-07 21:15:36 -07:00
Wesley W. Terpstra 19851a7c9e apb: SRAM reports errors on illegal access 2017-07-07 21:15:33 -07:00
Wesley W. TerpstraandGitHub 025f7d890b axi4: SRAM now reports errors on illegal address (#852) 2017-07-07 19:27:32 -07:00
Wesley W. TerpstraandGitHub 367d4aebe6 Set complete unconditionally 2017-06-30 10:15:53 -07:00
Wesley W. TerpstraandGitHub 4e9f65b2ef Simplify logic further and bugfix 
complete was being set unconditionally
 2017-06-30 10:07:39 -07:00
Wesley W. TerpstraandGitHub 3dca2bc4a3 gah 2017-06-30 01:07:29 -07:00
Wesley W. TerpstraandGitHub e43b7accf9 Fix compile error and eliminate wasteful wires 2017-06-30 01:06:02 -07:00
Wesley W. TerpstraandGitHub e3c7bb3b1f SRAM: MemoryDevices use .reg (not .reg("mem")) (#835) 2017-06-29 19:07:12 -07:00
Wesley W. TerpstraandGitHub 7dae3388e1 Merge pull request #830 from freechipsproject/flip-dts-idtim 
Flip dts itim and dtim references
 2017-06-29 00:18:19 -07:00
Wesley W. Terpstra 5edc4546e3 rocket: add dtim and itim refs to cpus 2017-06-28 23:10:58 -07:00
Wesley W. Terpstra 7d6f8d48f2 Revert "rocket: link dtim to its cpu" 
This reverts commit e6c2d446cc.
 2017-06-28 23:10:57 -07:00
Wesley W. Terpstra fbcd6f0eb2 Revert "rocket: link itim to its cpu" 
This reverts commit 48390ed604.
 2017-06-28 23:10:57 -07:00
Wesley W. TerpstraandGitHub 5002d2accf Merge pull request #827 from freechipsproject/dts-improvements 
Dts improvements
 2017-06-28 17:45:06 -07:00
Wesley W. Terpstra 66489ffa13 rom+sram: add a compatible field 2017-06-28 15:41:20 -07:00
Wesley W. Terpstra ca3030cba3 dcache: fix a gender inversion bug introduced in #826 2017-06-28 15:38:53 -07:00
Wesley W. Terpstra 02aa80a958 TLZero: include a version number 2017-06-28 15:12:46 -07:00
Wesley W. Terpstra 48390ed604 rocket: link itim to its cpu 2017-06-28 15:06:19 -07:00
Wesley W. Terpstra e6c2d446cc rocket: link dtim to its cpu 2017-06-28 15:06:19 -07:00
Wesley W. Terpstra 3f6d5110cd rocket: dtim is not a dcache 2017-06-28 15:06:19 -07:00
Wesley W. Terpstra bca3db0866 diplomacy: add RWXC permissions also to ResourceMappings 2017-06-28 15:06:19 -07:00
Wesley W. Terpstra 5436be54ff periphery: use SimpleBus for mmio ports 2017-06-28 15:06:19 -07:00
Wesley W. Terpstra 171e1a4c05 diplomacy: add SimpleBus to describe bridges 2017-06-28 15:06:19 -07:00
Wesley W. Terpstra 84dc23c215 devices: add reg-names to most devices 2017-06-28 15:06:16 -07:00
Wesley W. Terpstra 0bf46edb6c diplomacy: support reg-names in DTS output 2017-06-28 14:26:55 -07:00
Wesley W. Terpstra 852f03282f rocket: give itim and dtim a compatible field for drivers to match 2017-06-28 14:26:55 -07:00
Wesley W. Terpstra 6c2b770605 plic: do not output #address-cells 
This is only needed for an interrupt-map, not an interrupt-controller.
 2017-06-28 14:26:55 -07:00
Wesley W. TerpstraandGitHub 66f64a9759 tilelink2 ToAXI4: don't interlock R+W for non-FIFO masters (#822) 
idCount <= 1 implies that no more than one transaction can be inflight,
so there is no need to interlock R+W. However, when stripBits > 0, it is
possible for a non-FIFO master to have > 1 idCount. In this case, we
also don't need to interlock R+W.
 2017-06-26 17:54:17 -07:00
Wesley W. TerpstraandGitHub 7a0655ae88 Merge pull request #816 from freechipsproject/reduce-axi-queues 
Reduce AXI4 queues
 2017-06-23 18:31:41 -07:00
Wesley W. Terpstra 8ca6c10994 tilelink2: ToAXI4 can strip off low source ID bits 
Some TL converters place extra meta data in the low bits of source.
Examples include the TLFragmenter and CacheCork.

This new argument makes it possible to save AXI4 ID space by reclaiming
those bits upon conversion.
 2017-06-23 17:22:45 -07:00
Wesley W. Terpstra feecfb53ed axi4: Deinterleaver need not make a Q for an unused AXI id 2017-06-23 17:22:42 -07:00
Wesley W. TerpstraandGitHub 9bea7c1c58 Merge pull request #815 from freechipsproject/reduce-others 
Reduce others
 2017-06-23 12:13:48 -07:00
Wesley W. Terpstra 2d8b2f4edd ReduceOthers: remove constants from the balanced AND tree 2017-06-23 00:28:05 -07:00
Wesley W. Terpstra 48611266fa diplomacy: use ReduceOthers in the RegMapper 2017-06-22 19:43:47 -07:00
Wesley W. Terpstra 11d1cb02eb util ReduceOthers produces nlogn cost ready-valid logic 2017-06-22 19:43:20 -07:00
Wesley W. Terpstra 2f2fe0a973 clint: don't ask for what you know (nTiles) 2017-06-20 17:21:53 -07:00
Wesley W. Terpstra bb309e573f TLSplitter: special-case the case of no split necessary 2017-06-20 14:10:25 -07:00
Wesley W. Terpstra 53f030c037 TLSplitter: default policy is roundRobin 
Track commit 274d908d98
 2017-06-20 14:03:01 -07:00
Wesley W. Terpstra 1aa4f5ce33 TLSplitter: QoR improvements 
Track commit 985d9750e6
 2017-06-20 14:01:07 -07:00
Wesley W. Terpstra f6e0dd12c8 TLSplitter: ManagerUnification is not used in Xbars 
Track the change made in 5994714970
 2017-06-20 13:58:30 -07:00
Wesley W. Terpstra a89c0551b7 travis: use travis_wait again 
Timeouts due to inactivity again :-/
 2017-06-15 23:04:17 -07:00
Wesley W. TerpstraandGitHub 93d423d202 diplomacy: optimize IdRange.contains (#798) 
This should make an optimal circuit for a wider class of ranges.
 2017-06-15 15:56:14 -07:00
Wesley W. TerpstraandGitHub c259e39fa3 Merge pull request #796 from freechipsproject/buffer-instance 
diplomacy: BufferParams can now directly create a Queue
 2017-06-14 15:58:29 -07:00
Wesley W. Terpstra 1f8c4ba4ca CoreplexNetwork: don't force a buffer on the coherence manager 
Let the l2Config.coherenceManager create its own appropriate buffers.
This can matter if you need to make sure the buffer is in the right
place in the hierarchy for hierarchical place and route.
 2017-06-14 14:27:23 -07:00
Wesley W. Terpstra 4a15d47061 diplomacy: BufferParams can now directly create a Queue 2017-06-14 13:47:37 -07:00
Wesley W. TerpstraandGitHub 36562ce48e Merge pull request #794 from freechipsproject/xbar-debug 
Deal with lots of sources more gracefully.
 2017-06-13 19:44:28 -07:00
Wesley W. Terpstra c85486e67c travis: don't give up if gcc is slow to build riscv-tools 2017-06-13 16:59:31 -07:00
Wesley W. Terpstra b4b165112c PeripheryErrorSlave: do not put a TLMonitor between the fragmenter and slave 
This edge has the largest number of source bits by far. Let's just exclude it.
 2017-06-13 16:59:29 -07:00
Wesley W. Terpstra 94f85e8bc8 tilelink2: TLMonitor will not create giant wires 2017-06-13 16:58:22 -07:00
Wesley W. TerpstraandGitHub 87a5665e43 axi4: only block writes if SAME master has outstanding reads (#782) 
* axi4: only block writes if SAME master has outstanding reads
* tilelink2: ToAXI4 rename variable
TL uses sources, not IDs like AXI. Keep it less confusing.
* tilelink2: ToAXI4 improve stall circuit delay
Don't bother decoding the AXI ID to compute stall.
 2017-06-05 16:54:00 -07:00
Wesley W. Terpstra b1917e7915 coreplex: add an ISPPort trait to add cross-connect points 2017-06-02 20:43:23 -07:00
Wesley W. Terpstra 81d372137a coreplex: unconditionally insert a Splitter between tiles and l1tol2 2017-06-02 20:43:21 -07:00
Wesley W. Terpstra d002cec6ac NodeNumberer: add an adapter to map inter-chip fabrics 2017-06-02 20:42:17 -07:00
Wesley W. Terpstra 5a2a6b0386 diplomacy: add a CustomNode type that allows direct overload of methods 2017-06-02 20:42:17 -07:00
Wesley W. Terpstra fed1f53afa tilelink2: add a TLSplitter to be used for the ISP port 2017-06-02 20:42:17 -07:00
Wesley W. Terpstra a4bf678954 tilelink2: fix latent Xbar truncation bug 
This was introduced when we switched to HeterogeneousBag for diplomatic IO.
It seems a lucky coincidence that nothing has run into this yet!
 2017-06-02 20:42:16 -07:00
Wesley W. Terpstra ce12a64f4b tilelink2: support SplitterNodes 2017-06-02 20:42:16 -07:00
Wesley W. Terpstra de39af7f65 tilelink2: make some Xbar methods reusable 2017-06-02 20:42:16 -07:00
Wesley W. Terpstra 0a2a93c27d diplomacy: add the new Splitter node type 2017-06-02 20:42:16 -07:00
Wesley W. Terpstra c695237050 diplomacy: make :=* and :*= resolution more flexible 2017-06-02 20:42:16 -07:00
Wesley W. TerpstraandGitHub 4679545b60 travis: front-load the longer running tests and tolerate no output (#779) 2017-06-02 20:41:26 -07:00
Wesley W. TerpstraandGitHub 63b1f4f047 Merge pull request #777 from freechipsproject/print-axi-ids 
coreplex: Improve memory map and AXI ID map output
 2017-06-02 18:52:55 -07:00