Merge pull request #827 from freechipsproject/dts-improvements
Dts improvements
This commit is contained in:
commit
5002d2accf
@ -118,14 +118,15 @@ trait CoreplexNetworkModule extends HasCoreplexParameters {
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private def collect(path: List[String], value: ResourceValue): List[(String, ResourceAddress)] = {
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value match {
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case r: ResourceAddress => List((path(1), r))
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case b: ResourceMapping => List((path(1), ResourceAddress(b.address, b.permissions)))
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case ResourceMap(value, _) => value.toList.flatMap { case (key, seq) => seq.flatMap(r => collect(key :: path, r)) }
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case _ => Nil
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}
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}
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private val ranges = collect(Nil, outer.bindingTree).groupBy(_._2).toList.flatMap { case (key, seq) =>
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AddressRange.fromSets(key.address).map { r => (r, key.r, key.w, key.x, key.c, seq.map(_._1)) }
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AddressRange.fromSets(key.address).map { r => (r, key.permissions, seq.map(_._1)) }
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}.sortBy(_._1)
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private val json = ranges.map { case (range, r, w, x, c, names) =>
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private val json = ranges.map { case (range, ResourcePermissions(r, w, x, c), names) =>
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println(fmt.format(
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range.base,
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range.base+range.size,
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@ -26,12 +26,12 @@ object JSON
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}
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private def helper(res: ResourceValue)(implicit path: Map[String, String]): Seq[String] = res match {
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case ResourceAddress(address, r, w, x, c) =>
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case ResourceAddress(address, ResourcePermissions(r, w, x, c)) =>
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AddressRange.fromSets(address).map { case AddressRange(base, size) =>
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s"""{"base":${base},"size":${size},"r":${r},"w":${w},"x":${x},"c":${c}}"""}
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case ResourceMapping(address, offset) =>
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case ResourceMapping(address, offset, ResourcePermissions(r, w, x, c)) =>
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AddressRange.fromSets(address).map { case AddressRange(base, size) =>
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s"""{"base":${base},"size":${size},"offset":${offset}}"""}
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s"""{"base":${base},"size":${size},"offset":${offset},"r":${r},"w":${w},"x":${x},"c":${c}}"""}
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case ResourceInt(value) => Seq(value.toString)
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case ResourceString(value) => Seq("\"" + value + "\"")
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case ResourceReference(value) => Seq("\"&" + path(value) + "\"")
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@ -7,8 +7,9 @@ import config._
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import scala.collection.immutable.{ListMap,SortedMap}
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sealed trait ResourceValue
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final case class ResourceAddress(address: Seq[AddressSet], r: Boolean, w: Boolean, x: Boolean, c: Boolean) extends ResourceValue
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final case class ResourceMapping(address: Seq[AddressSet], offset: BigInt) extends ResourceValue
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case class ResourcePermissions(r: Boolean, w: Boolean, x: Boolean, c: Boolean) // Not part of DTS
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final case class ResourceAddress(address: Seq[AddressSet], permissions: ResourcePermissions) extends ResourceValue
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final case class ResourceMapping(address: Seq[AddressSet], offset: BigInt, permissions: ResourcePermissions) extends ResourceValue
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final case class ResourceInt(value: BigInt) extends ResourceValue
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final case class ResourceString(value: String) extends ResourceValue
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final case class ResourceReference(value: String) extends ResourceValue
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@ -69,15 +70,29 @@ trait DeviceRegName
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this: Device =>
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val prefix = "soc/" // nearly everything on-chip belongs here
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def describeName(devname: String, resources: ResourceBindings): String = {
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val reg = resources("reg")
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require (!reg.isEmpty, "Device is missing the 'reg' property")
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reg.head.value match {
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case x: ResourceAddress => s"${prefix}${devname}@${x.address.head.base.toString(16)}"
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case _ => require(false, "Device has the wrong type of 'reg' property (${reg.head})"); ""
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val reg = resources.map.filterKeys(regFilter)
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if (reg.isEmpty) {
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devname
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} else {
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val (named, bulk) = reg.partition { case (k, v) => regName(k).isDefined }
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val mainreg = reg.find(x => regName(x._1) == "control").getOrElse(reg.head)._2
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require (!mainreg.isEmpty, s"reg binding for $devname is empty!")
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mainreg.head.value match {
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case x: ResourceAddress => s"${prefix}${devname}@${x.address.head.base.toString(16)}"
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case _ => require(false, "Device has the wrong type of 'reg' property (${reg.head})"); ""
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}
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}
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}
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def reg = Seq(Resource(this, "reg"))
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def reg(name: String): Seq[Resource] = Seq(Resource(this, "reg/" + name))
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def reg: Seq[Resource] = Seq(Resource(this, "reg"))
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def regFilter(name: String): Boolean = name == "reg" || name.take(4) == "reg/"
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def regName(name: String): Option[String] = {
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val keys = name.split("/")
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require (keys.size >= 1 && keys.size <= 2 && keys(0) == "reg", s"Invalid reg name '${name}'")
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if (keys.size == 1) None else Some(keys(1))
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}
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}
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class SimpleDevice(devname: String, devcompat: Seq[String]) extends Device with DeviceInterrupts with DeviceRegName
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@ -85,16 +100,54 @@ class SimpleDevice(devname: String, devcompat: Seq[String]) extends Device with
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def describe(resources: ResourceBindings): Description = {
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val name = describeName(devname, resources)
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val int = describeInterrupts(resources)
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val compat =
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if (devcompat.isEmpty) None else
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Some("compatible" -> devcompat.map(ResourceString(_)))
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Description(name,
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ListMap("reg" -> resources("reg").map(_.value))
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++ compat ++ int)
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def optDef(x: String, seq: Seq[ResourceValue]) = if (seq.isEmpty) None else Some(x -> seq)
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val compat = optDef("compatible", devcompat.map(ResourceString(_)))
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val reg = resources.map.filterKeys(regFilter)
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val (named, bulk) = reg.partition { case (k, v) => regName(k).isDefined }
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// We need to be sure that each named reg has exactly one AddressRange associated to it
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named.foreach {
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case (k, Seq(Binding(_, value: ResourceAddress))) =>
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val ranges = AddressRange.fromSets(value.address)
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require (ranges.size == 1, s"DTS device $name has $k = $ranges, must be a single range!")
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case (k, seq) =>
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require (false, s"DTS device $name has $k = $seq, must be a single ResourceAddress!")
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}
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val names = optDef("reg-names", named.map(x => ResourceString(regName(x._1).get)).toList)
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val regs = optDef("reg", (named ++ bulk).flatMap(_._2.map(_.value)).toList)
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Description(name, ListMap() ++ compat ++ int ++ names ++ regs)
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}
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}
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class SimpleBus(devname: String, devcompat: Seq[String], offset: BigInt = 0) extends SimpleDevice(devname, devcompat ++ Seq("simple-bus"))
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{
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override def describe(resources: ResourceBindings): Description = {
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val ranges = resources("ranges").map {
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case Binding(_, a: ResourceAddress) => ResourceMapping(a.address, offset, a.permissions)
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}
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require (!ranges.isEmpty, s"SimpleBus $devname must set ranges")
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val map = AddressRange.fromSets(ranges.flatMap(_.address))
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val minBase = map.map(_.base).min
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val maxBase = map.map(_.end).max
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val maxSize = map.map(_.size).max
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def ofInt(x: Int) = Seq(ResourceInt(BigInt(x)))
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val extra = Map(
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"#address-cells" -> ofInt((log2Ceil(maxBase) + 31) / 32),
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"#size-cells" -> ofInt((log2Ceil(maxSize) + 31) / 32),
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"ranges" -> ranges)
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val Description(_, mapping) = super.describe(resources)
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Description(s"${prefix}${devname}@${minBase.toString(16)}", mapping ++ extra)
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}
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def ranges = Seq(Resource(this, "ranges"))
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}
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class MemoryDevice extends Device with DeviceRegName
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{
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override val prefix = ""
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@ -83,7 +83,8 @@ class DCacheModule(outer: DCache) extends HellaCacheModule(outer) {
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}
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val q_depth = if (rational) (2 min maxUncachedInFlight-1) else 0
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val tl_out_a = if (q_depth == 0) tl_out.a else Queue(tl_out.a, q_depth, flow = true, pipe = true)
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val tl_out_a = Wire(tl_out.a)
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tl_out.a <> (if (q_depth == 0) tl_out_a else Queue(tl_out_a, q_depth, flow = true, pipe = true))
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val s1_valid = Reg(next=io.cpu.req.fire(), init=Bool(false))
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val s1_probe = Reg(next=tl_out.b.fire(), init=Bool(false))
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@ -53,9 +53,9 @@ class FrontendIO(implicit p: Parameters) extends CoreBundle()(p) {
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val perf = new FrontendPerfEvents().asInput
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}
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class Frontend(val icacheParams: ICacheParams, hartid: Int)(implicit p: Parameters) extends LazyModule {
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class Frontend(val icacheParams: ICacheParams, hartid: Int, owner: => Option[Device] = None)(implicit p: Parameters) extends LazyModule {
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lazy val module = new FrontendModule(this)
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val icache = LazyModule(new ICache(icacheParams, hartid))
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val icache = LazyModule(new ICache(icacheParams, hartid, owner))
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val masterNode = TLOutputNode()
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val slaveNode = TLInputNode()
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@ -184,7 +184,8 @@ class FrontendModule(outer: Frontend) extends LazyModuleImp(outer)
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/** Mix-ins for constructing tiles that have an ICache-based pipeline frontend */
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trait HasICacheFrontend extends CanHavePTW with HasTileLinkMasterPort {
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val module: HasICacheFrontendModule
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val frontend = LazyModule(new Frontend(tileParams.icache.get, hartid: Int))
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def itimOwner : Option[Device] = None
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val frontend = LazyModule(new Frontend(tileParams.icache.get, hartid: Int, itimOwner))
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val hartid: Int
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tileBus.node := frontend.masterNode
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nPTWPorts += 1
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@ -35,18 +35,25 @@ class ICacheReq(implicit p: Parameters) extends CoreBundle()(p) with HasL1ICache
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val addr = UInt(width = vaddrBits)
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}
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class ICache(val icacheParams: ICacheParams, val hartid: Int)(implicit p: Parameters) extends LazyModule {
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class ICache(val icacheParams: ICacheParams, val hartid: Int, owner: => Option[Device] = None)(implicit p: Parameters) extends LazyModule {
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lazy val module = new ICacheModule(this)
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val masterNode = TLClientNode(TLClientParameters(name = s"Core ${hartid} ICache"))
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val device = new SimpleDevice("itim", Seq("sifive,itim0")) {
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override def describe(resources: ResourceBindings): Description = {
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val extra = owner.map(x => ("sifive,cpu" -> Seq(ResourceReference(x.label))))
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val Description(name, mapping) = super.describe(resources)
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Description(name, mapping ++ extra)
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}
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}
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val size = icacheParams.nSets * icacheParams.nWays * icacheParams.blockBytes
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val device = new SimpleDevice("itim", Nil)
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val slaveNode = icacheParams.itimAddr.map { itimAddr =>
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val wordBytes = icacheParams.fetchBytes
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TLManagerNode(Seq(TLManagerPortParameters(
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Seq(TLManagerParameters(
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address = Seq(AddressSet(itimAddr, size-1)),
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resources = device.reg,
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resources = device.reg("mem"),
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regionType = RegionType.UNCACHED,
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executable = true,
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supportsPutFull = TransferSizes(1, wordBytes),
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@ -42,7 +42,7 @@ class RocketTile(val rocketParams: RocketTileParams, val hartid: Int)(implicit p
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val c = if (rocketParams.core.useCompressed) "c" else ""
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val isa = s"rv${p(XLen)}i$m$a$f$d$c"
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val dcache = rocketParams.dcache.map(d => Map(
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val dcache = rocketParams.dcache.filter(!_.scratch.isDefined).map(d => Map(
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"d-cache-block-size" -> ofInt(block),
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"d-cache-sets" -> ofInt(d.nSets),
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"d-cache-size" -> ofInt(d.nSets * d.nWays * block))).getOrElse(Map())
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@ -89,6 +89,10 @@ class RocketTile(val rocketParams: RocketTileParams, val hartid: Int)(implicit p
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++ dcache ++ icache ++ nextlevel ++ mmu ++ itlb ++ dtlb)
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}
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}
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override def dtimOwner = Some(cpuDevice)
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override def itimOwner = Some(cpuDevice)
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val intcDevice = new Device {
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def describe(resources: ResourceBindings): Description = {
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Description(s"cpus/cpu@${hartid}/interrupt-controller", Map(
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@ -13,13 +13,20 @@ import uncore.tilelink2._
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import uncore.util._
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import util._
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class ScratchpadSlavePort(address: AddressSet)(implicit p: Parameters) extends LazyModule
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class ScratchpadSlavePort(address: AddressSet, owner: => Option[Device] = None)(implicit p: Parameters) extends LazyModule
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with HasCoreParameters {
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val device = new SimpleDevice("dtim", Nil)
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val device = new SimpleDevice("dtim", Seq("sifive,dtim0")) {
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override def describe(resources: ResourceBindings): Description = {
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val extra = owner.map(x => ("sifive,cpu" -> Seq(ResourceReference(x.label))))
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val Description(name, mapping) = super.describe(resources)
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Description(name, mapping ++ extra)
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}
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}
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val node = TLManagerNode(Seq(TLManagerPortParameters(
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Seq(TLManagerParameters(
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address = List(address),
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resources = device.reg,
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resources = device.reg("mem"),
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regionType = RegionType.UNCACHED,
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executable = true,
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supportsArithmetic = if (usingAtomics) TransferSizes(4, coreDataBytes) else TransferSizes.none,
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@ -102,6 +109,7 @@ trait CanHaveScratchpad extends HasHellaCache with HasICacheFrontend with HasCor
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val module: CanHaveScratchpadModule
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val slaveNode = TLInputNode() // Up to two uses for this input node:
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def dtimOwner: Option[Device] = None // who owns the Scratchpad?
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// 1) Frontend always exists, but may or may not have a scratchpad node
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val fg = LazyModule(new TLFragmenter(fetchWidth*coreInstBytes, p(CacheBlockBytes), earlyAck=true))
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@ -112,7 +120,7 @@ trait CanHaveScratchpad extends HasHellaCache with HasICacheFrontend with HasCor
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// 2) ScratchpadSlavePort always has a node, but only exists when the HellaCache has a scratchpad
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val scratch = tileParams.dcache.flatMap(d => d.scratch.map(s =>
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LazyModule(new ScratchpadSlavePort(AddressSet(s, d.dataScratchpadBytes-1)))))
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LazyModule(new ScratchpadSlavePort(AddressSet(s, d.dataScratchpadBytes-1), dtimOwner))))
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scratch foreach { lm => lm.node := TLFragmenter(xLen/8, p(CacheBlockBytes), earlyAck=true)(slaveNode) }
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def findScratchpadFromICache: Option[AddressSet] = scratch.map { s =>
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@ -177,11 +177,11 @@ trait HasPeripheryMasterAXI4MemPortModuleImp extends LazyMultiIOModuleImp with H
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/** Adds a AXI4 port to the system intended to master an MMIO device bus */
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trait HasPeripheryMasterAXI4MMIOPort extends HasSystemNetworks {
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private val config = p(ExtBus)
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private val device = new SimpleDevice("mmio", Nil)
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private val device = new SimpleBus("mmio", Nil)
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val mmio_axi4 = AXI4BlindOutputNode(Seq(AXI4SlavePortParameters(
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slaves = Seq(AXI4SlaveParameters(
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address = List(AddressSet(BigInt(config.base), config.size-1)),
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resources = device.reg,
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resources = device.ranges,
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executable = true, // Can we run programs on this memory?
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supportsWrite = TransferSizes(1, 256), // The slave supports 1-256 byte transfers
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supportsRead = TransferSizes(1, 256))),
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@ -252,11 +252,11 @@ trait HasPeripherySlaveAXI4PortModuleImp extends LazyMultiIOModuleImp with HasPe
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/** Adds a TileLink port to the system intended to master an MMIO device bus */
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trait HasPeripheryMasterTLMMIOPort extends HasSystemNetworks {
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private val config = p(ExtBus)
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private val device = new SimpleDevice("mmio", Nil)
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private val device = new SimpleBus("mmio", Nil)
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val mmio_tl = TLBlindOutputNode(Seq(TLManagerPortParameters(
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managers = Seq(TLManagerParameters(
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address = List(AddressSet(BigInt(config.base), config.size-1)),
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resources = device.reg,
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resources = device.ranges,
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executable = true,
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supportsGet = TransferSizes(1, cacheBlockBytes),
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supportsPutFull = TransferSizes(1, cacheBlockBytes),
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@ -70,8 +70,7 @@ class TLPLIC(params: PLICParams)(implicit p: Parameters) extends LazyModule
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val extra = Map(
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"interrupt-controller" -> Nil,
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"riscv,ndev" -> Seq(ResourceInt(nDevices)),
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"#interrupt-cells" -> Seq(ResourceInt(1)),
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"#address-cells" -> Seq(ResourceInt(0)))
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"#interrupt-cells" -> Seq(ResourceInt(1)))
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Description(name, mapping ++ extra)
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}
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}
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@ -13,7 +13,7 @@ import uncore.util._
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import config._
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class TLROM(val base: BigInt, val size: Int, contentsDelayed: => Seq[Byte], executable: Boolean = true, beatBytes: Int = 4,
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resources: Seq[Resource] = new SimpleDevice("rom", Nil).reg)(implicit p: Parameters) extends LazyModule
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resources: Seq[Resource] = new SimpleDevice("rom", Seq("sifive,rom0")).reg("mem"))(implicit p: Parameters) extends LazyModule
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{
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val node = TLManagerNode(beatBytes, TLManagerParameters (
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@ -283,7 +283,6 @@ class TLDebugModuleOuter(device: Device)(implicit p: Parameters) extends LazyMod
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val dmiNode = TLRegisterNode (
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address = AddressSet.misaligned(DMI_DMCONTROL << 2, 4),
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device = device,
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deviceKey = "reg",
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beatBytes = 4,
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executable = false
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)
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@ -430,7 +429,6 @@ class TLDebugModuleInner(device: Device, getNComponents: () => Int)(implicit p:
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address = AddressSet.misaligned(0, DMI_RegAddrs.DMI_DMCONTROL << 2) ++
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AddressSet.misaligned((DMI_RegAddrs.DMI_DMCONTROL + 1) << 2, (0x200 - ((DMI_RegAddrs.DMI_DMCONTROL + 1) << 2))),
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device = device,
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deviceKey = "reg",
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beatBytes = 4,
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executable = false
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)
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@ -438,7 +436,6 @@ class TLDebugModuleInner(device: Device, getNComponents: () => Int)(implicit p:
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val tlNode = TLRegisterNode(
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address=Seq(AddressSet(0, 0xFFF)), // This is required for correct functionality, it's not configurable.
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device=device,
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deviceKey="reg",
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beatBytes=p(XLen)/8,
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executable=true
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)
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@ -14,7 +14,7 @@ class TLError(address: Seq[AddressSet], beatBytes: Int = 4)(implicit p: Paramete
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val node = TLManagerNode(Seq(TLManagerPortParameters(
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Seq(TLManagerParameters(
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address = address,
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resources = device.reg,
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resources = device.reg("mem"),
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supportsGet = TransferSizes(1, beatBytes),
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supportsPutPartial = TransferSizes(1, beatBytes),
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supportsPutFull = TransferSizes(1, beatBytes),
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@ -57,11 +57,11 @@ case class TLManagerParameters(
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require (minAlignment >= maxTransfer, s"minAlignment ($minAlignment) must be >= maxTransfer ($maxTransfer)")
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def toResource: ResourceAddress = {
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ResourceAddress(address,
|
||||
ResourceAddress(address, ResourcePermissions(
|
||||
r = supportsAcquireB || supportsGet,
|
||||
w = supportsAcquireT || supportsPutFull,
|
||||
x = executable,
|
||||
c = supportsAcquireB)
|
||||
c = supportsAcquireB))
|
||||
}
|
||||
}
|
||||
|
||||
|
@ -11,7 +11,7 @@ import scala.math.{min,max}
|
||||
class TLRegisterNode(
|
||||
address: Seq[AddressSet],
|
||||
device: Device,
|
||||
deviceKey: String = "reg",
|
||||
deviceKey: String = "reg/control",
|
||||
concurrency: Int = 0,
|
||||
beatBytes: Int = 4,
|
||||
undefZero: Boolean = true,
|
||||
@ -88,7 +88,7 @@ object TLRegisterNode
|
||||
def apply(
|
||||
address: Seq[AddressSet],
|
||||
device: Device,
|
||||
deviceKey: String = "reg",
|
||||
deviceKey: String = "reg/control",
|
||||
concurrency: Int = 0,
|
||||
beatBytes: Int = 4,
|
||||
undefZero: Boolean = true,
|
||||
@ -103,7 +103,7 @@ object TLRegisterNode
|
||||
abstract class TLRegisterRouterBase(devname: String, devcompat: Seq[String], val address: AddressSet, interrupts: Int, concurrency: Int, beatBytes: Int, undefZero: Boolean, executable: Boolean)(implicit p: Parameters) extends LazyModule
|
||||
{
|
||||
val device = new SimpleDevice(devname, devcompat)
|
||||
val node = TLRegisterNode(Seq(address), device, "reg", concurrency, beatBytes, undefZero, executable)
|
||||
val node = TLRegisterNode(Seq(address), device, "reg/control", concurrency, beatBytes, undefZero, executable)
|
||||
val intnode = IntSourceNode(IntSourcePortSimple(num = interrupts, resources = Seq(Resource(device, "int"))))
|
||||
}
|
||||
|
||||
|
@ -10,11 +10,11 @@ import util._
|
||||
|
||||
class TLRAM(address: AddressSet, executable: Boolean = true, beatBytes: Int = 4, name: Option[String] = None)(implicit p: Parameters) extends LazyModule
|
||||
{
|
||||
val device = name.map(new SimpleDevice(_, Nil)).getOrElse(new MemoryDevice)
|
||||
val device = name.map(new SimpleDevice(_, Seq("sifive,sram0"))).getOrElse(new MemoryDevice)
|
||||
val node = TLManagerNode(Seq(TLManagerPortParameters(
|
||||
Seq(TLManagerParameters(
|
||||
address = List(address),
|
||||
resources = device.reg,
|
||||
resources = device.reg("mem"),
|
||||
regionType = RegionType.UNCACHED,
|
||||
executable = executable,
|
||||
supportsGet = TransferSizes(1, beatBytes),
|
||||
|
@ -15,7 +15,7 @@ class TLTestRAM(address: AddressSet, executable: Boolean = true, beatBytes: Int
|
||||
val node = TLManagerNode(Seq(TLManagerPortParameters(
|
||||
Seq(TLManagerParameters(
|
||||
address = List(address),
|
||||
resources = device.reg,
|
||||
resources = device.reg("mem"),
|
||||
regionType = RegionType.UNCACHED,
|
||||
executable = executable,
|
||||
supportsGet = TransferSizes(1, beatBytes),
|
||||
|
@ -8,12 +8,12 @@ import diplomacy._
|
||||
|
||||
class TLZero(address: AddressSet, executable: Boolean = true, beatBytes: Int = 4)(implicit p: Parameters) extends LazyModule
|
||||
{
|
||||
val device = new SimpleDevice("rom", Seq("ucbbar,cacheable-zero"))
|
||||
val device = new SimpleDevice("rom", Seq("ucbbar,cacheable-zero0"))
|
||||
|
||||
val node = TLManagerNode(Seq(TLManagerPortParameters(
|
||||
Seq(TLManagerParameters(
|
||||
address = List(address),
|
||||
resources = device.reg,
|
||||
resources = device.reg("mem"),
|
||||
regionType = RegionType.UNCACHED,
|
||||
executable = executable,
|
||||
supportsGet = TransferSizes(1, beatBytes),
|
||||
|
Loading…
Reference in New Issue
Block a user