Merge pull request #816 from freechipsproject/reduce-axi-queues
Reduce AXI4 queues
This commit is contained in:
Wesley W. Terpstra
GitHub
commit
7a0655ae88
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@ -28,7 +28,7 @@ class AXI4Deinterleaver(maxReadBytes: Int)(implicit p: Parameters) extends LazyM
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}
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((io.in zip io.out) zip (node.edgesIn zip node.edgesOut)) foreach { case ((in, out), (edgeIn, edgeOut)) =>
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val queues = edgeOut.master.endId
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val endId = edgeOut.master.endId
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val beatBytes = edgeOut.slave.beatBytes
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val beats = (maxReadBytes+beatBytes-1) / beatBytes
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@ -42,31 +42,43 @@ class AXI4Deinterleaver(maxReadBytes: Int)(implicit p: Parameters) extends LazyM
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// Nothing to do if only single-beat R
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in.r <> out.r
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} else {
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// Buffer R response
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val count = RegInit(Vec.fill(queues) { UInt(0, width=log2Ceil(beats+1)) })
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val qs = Seq.fill(queues) { Module(new Queue(out.r.bits, beats)) }
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// Queues to buffer R responses
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val qs = Seq.tabulate(endId) { i =>
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val depth = edgeOut.master.masters.find(_.id.contains(i)).flatMap(_.maxFlight).getOrElse(0)
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if (depth > 0) {
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Module(new Queue(out.r.bits, beats)).io
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} else {
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Wire(new QueueIO(out.r.bits, beats))
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}
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}
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// Which ID is being enqueued and dequeued?
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val locked = RegInit(Bool(false))
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val deq_id = Reg(UInt(width=log2Up(queues)))
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val deq_id = Reg(UInt(width=log2Up(endId)))
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val enq_id = out.r.bits.id
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val deq_OH = UIntToOH(deq_id, queues)
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val enq_OH = UIntToOH(enq_id, queues)
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val deq_OH = UIntToOH(deq_id, endId)
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val enq_OH = UIntToOH(enq_id, endId)
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// Track the number of completely received bursts per FIFO id
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val next_count = Wire(count)
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((count zip next_count) zip (enq_OH.toBools zip deq_OH.toBools)) foreach { case ((p, n), (i, d)) =>
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val inc = i && out.r.fire() && out.r.bits.last
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val dec = d && in.r.fire() && in.r.bits.last
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n := p + inc.asUInt - dec.asUInt
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// Bounds checking
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assert (!dec || p =/= UInt(0))
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assert (!inc || p =/= UInt(beats))
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}
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count := next_count
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val pending = Cat(Seq.tabulate(endId) { i =>
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val depth = edgeOut.master.masters.find(_.id.contains(i)).flatMap(_.maxFlight).getOrElse(0)
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if (depth == 0) {
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Bool(false)
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} else {
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val count = RegInit(UInt(0, width=log2Ceil(beats+1)))
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val next = Wire(count)
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val inc = enq_OH(i) && out.r.fire() && out.r.bits.last
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val dec = deq_OH(i) && in.r.fire() && in.r.bits.last
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next := count + inc.asUInt - dec.asUInt
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count := next
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// Bounds checking
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assert (!dec || count =/= UInt(0))
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assert (!inc || count =/= UInt(beats))
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next =/= UInt(0)
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}
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}.reverse)
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// Select which Q will we start sending next cycle
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val pending = Cat(next_count.map(_ =/= UInt(0)).reverse)
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val winner = pending & ~(leftOR(pending) << 1)
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when (!locked || (in.r.fire() && in.r.bits.last)) {
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locked := pending.orR
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@ -75,16 +87,16 @@ class AXI4Deinterleaver(maxReadBytes: Int)(implicit p: Parameters) extends LazyM
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// Transmit the selected burst to inner
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in.r.valid := locked
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in.r.bits := Vec(qs.map(_.io.deq.bits))(deq_id)
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in.r.bits := Vec(qs.map(_.deq.bits))(deq_id)
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(deq_OH.toBools zip qs) foreach { case (s, q) =>
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q.io.deq.ready := s && in.r.fire()
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q.deq.ready := s && in.r.fire()
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}
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// Feed response into matching Q
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out.r.ready := Vec(qs.map(_.io.enq.ready))(enq_id)
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out.r.ready := Vec(qs.map(_.enq.ready))(enq_id)
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(enq_OH.toBools zip qs) foreach { case (s, q) =>
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q.io.enq.valid := s && out.r.valid
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q.io.enq.bits := out.r.bits
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q.enq.valid := s && out.r.valid
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q.enq.bits := out.r.bits
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}
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}
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}
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@ -10,17 +10,22 @@ import util.ElaborationArtefacts
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import uncore.axi4._
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import scala.math.{min, max}
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case class TLToAXI4Node(beatBytes: Int) extends MixedAdapterNode(TLImp, AXI4Imp)(
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case class TLToAXI4Node(beatBytes: Int, stripBits: Int = 0) extends MixedAdapterNode(TLImp, AXI4Imp)(
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dFn = { p =>
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p.clients.foreach { c =>
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require (c.sourceId.start % (1 << stripBits) == 0 &&
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c.sourceId.end % (1 << stripBits) == 0,
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"Cannot strip bits of aligned client ${c.name}: ${c.sourceId}")
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}
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val clients = p.clients.sortWith(TLToAXI4.sortByType _)
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val idSize = clients.map { c => if (c.requestFifo) 1 else c.sourceId.size }
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val idSize = clients.map { c => if (c.requestFifo) 1 else (c.sourceId.size >> stripBits) }
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val idStart = idSize.scanLeft(0)(_+_).init
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val masters = ((idStart zip idSize) zip clients) map { case ((start, size), c) =>
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AXI4MasterParameters(
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name = c.name,
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id = IdRange(start, start+size),
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aligned = true,
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maxFlight = Some(if (c.requestFifo) c.sourceId.size else 1),
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maxFlight = Some(if (c.requestFifo) c.sourceId.size else (1 << stripBits)),
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nodePath = c.nodePath)
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}
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AXI4MasterPortParameters(
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@ -43,9 +48,9 @@ case class TLToAXI4Node(beatBytes: Int) extends MixedAdapterNode(TLImp, AXI4Imp)
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minLatency = p.minLatency)
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})
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class TLToAXI4(beatBytes: Int, combinational: Boolean = true, adapterName: Option[String] = None)(implicit p: Parameters) extends LazyModule
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class TLToAXI4(beatBytes: Int, combinational: Boolean = true, adapterName: Option[String] = None, stripBits: Int = 0)(implicit p: Parameters) extends LazyModule
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{
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val node = TLToAXI4Node(beatBytes)
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val node = TLToAXI4Node(beatBytes, stripBits)
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lazy val module = new LazyModuleImp(this) {
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val io = new Bundle {
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@ -71,7 +76,7 @@ class TLToAXI4(beatBytes: Int, combinational: Boolean = true, adapterName: Optio
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var idCount = Array.fill(edgeOut.master.endId) { 0 }
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val maps = (edgeIn.client.clients.sortWith(TLToAXI4.sortByType) zip edgeOut.master.masters) flatMap { case (c, m) =>
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for (i <- 0 until c.sourceId.size) {
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val id = m.id.start + (if (c.requestFifo) 0 else i)
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val id = m.id.start + (if (c.requestFifo) 0 else (i >> stripBits))
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sourceStall(c.sourceId.start + i) := idStall(id)
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sourceTable(c.sourceId.start + i) := UInt(id)
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idCount(id) = idCount(id) + 1
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@ -221,8 +226,8 @@ class TLToAXI4(beatBytes: Int, combinational: Boolean = true, adapterName: Optio
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object TLToAXI4
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{
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// applied to the TL source node; y.node := TLToAXI4(beatBytes)(x.node)
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def apply(beatBytes: Int, combinational: Boolean = true, adapterName: Option[String] = None)(x: TLOutwardNode)(implicit p: Parameters, sourceInfo: SourceInfo): AXI4OutwardNode = {
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val axi4 = LazyModule(new TLToAXI4(beatBytes, combinational, adapterName))
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def apply(beatBytes: Int, combinational: Boolean = true, adapterName: Option[String] = None, stripBits: Int = 0)(x: TLOutwardNode)(implicit p: Parameters, sourceInfo: SourceInfo): AXI4OutwardNode = {
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val axi4 = LazyModule(new TLToAXI4(beatBytes, combinational, adapterName, stripBits))
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axi4.node := x
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axi4.node
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}
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