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Commit Graph

212 Commits

Author SHA1 Message Date
Andrew Waterman
f235fa0db6 Move branch resolution to M stage 2014-04-07 15:58:49 -07:00
Andrew Waterman
db59fc65ab Add return address stack 2014-04-01 15:01:27 -07:00
Andrew Waterman
1b030777ce Remove vestigial control signal 2014-03-24 04:36:12 -07:00
Andrew Waterman
943d7ac80a Use LinkedHashSet/Map for simpler determinism 2014-03-15 17:31:48 -07:00
Donggyu Kim
53d62cb69d remove nondeterminism 2014-03-15 16:45:58 -07:00
Andrew Waterman
00bc1a2293 Add fclass.{s|d} instructions 2014-03-10 16:59:24 -07:00
Andrew Waterman
c7110c8389 Make FPU pipeline depths configurable 2014-02-28 13:39:59 -08:00
Andrew Waterman
a09ff9fdc7 Revert to old AUIPC definition 2014-02-10 19:04:42 -08:00
Andrew Waterman
1456170c6d Always stall decode on RoCC -> FENCE; never stall on RoCC -> deferred AMO.RL fence 2014-02-06 12:01:49 -08:00
Yunsup Lee
ff7cae29f7 hookup rocc interrupt and s bit 2014-02-06 00:09:42 -08:00
Stephen Twigg
6a02d15c21 Merge branch 'master' into hwacha-port 2014-02-04 17:05:03 -08:00
Andrew Waterman
febd26f505 Correct CSR privilege logic 2014-01-31 01:03:17 -08:00
Stephen Twigg
3c3c469725 Add exception signal to rocc interface 2014-01-28 22:13:16 -08:00
Andrew Waterman
267394d3cc Fix CSR interlocks 2014-01-24 16:37:40 -08:00
Andrew Waterman
1f986d1c96 Branches don't care about the ALU input/function 2014-01-24 16:37:40 -08:00
Andrew Waterman
a1b7774f5d Simplify handling of CAUSE register 2014-01-24 16:37:39 -08:00
Andrew Waterman
6ba2c1abe5 Use auto-generated CAUSE constants 2014-01-21 15:01:54 -08:00
Andrew Waterman
57f4d89c90 Generate D$ replay_next signals correctly 2014-01-16 00:16:09 -08:00
Andrew Waterman
31060ea8ae Fix fubar long-latency writeback control logic
Load miss writebacks happening at the same time as multiplication
wasn't working.  Hopefully this does it.
2014-01-14 04:02:43 -08:00
Andrew Waterman
e8486817e6 Clean up formatting (i.e. remove tabs, semicolons) 2014-01-13 21:43:56 -08:00
Andrew Waterman
07a91bb99a Miscellaneous cleanup 2013-12-09 19:53:14 -08:00
Andrew Waterman
da3135ac9b Begin integer unit clean-up
...to make it easier to generate the superscalar version of the core.
2013-12-09 15:06:13 -08:00
Andrew Waterman
16d5250924 Correct FP trap behavior on FCSR 2013-12-05 04:18:04 -08:00
Andrew Waterman
924261e2b2 Update to new privileged ISA... phew 2013-11-25 04:35:15 -08:00
Andrew Waterman
65b8340cea Mitigate D$ hit -> branch -> NPC critical path 2013-11-24 14:21:03 -08:00
Stephen Twigg
3532ae0b79 From Andrew, actually mark scoreboard when rocc instruction with a writeback is issued. Also, fix an issue with AccumulatorExample not properly tagging its memory requests. Finally, reverted changes from f27429c to more properly follow the spike model (always return previous value of accumulator). 2013-09-24 10:54:09 -07:00
Andrew Waterman
1d2f4f8437 New ISA encoding, AUIPC semantics 2013-09-21 06:32:40 -07:00
Andrew Waterman
f12bbc1e43 working RoCC AccumulatorExample 2013-09-14 22:34:53 -07:00
Andrew Waterman
a0cb711451 Start adding RoCC 2013-09-14 15:31:50 -07:00
Andrew Waterman
d053bdc89f Remove Hwacha from Rocket
Soon it will use the coprocessor interface.
2013-09-12 22:34:38 -07:00
Andrew Waterman
59f5358435 Implement AQ/RL; move fence logic out of cache 2013-09-12 16:07:30 -07:00
Andrew Waterman
243c4ae342 sync up rocket with new isa 2013-09-12 03:44:38 -07:00
Andrew Waterman
d1b5076fee Don't update BTB when garbage was fetched 2013-08-24 14:44:11 -07:00
Andrew Waterman
52e31f3298 Bypass scoreboard updates
This reduces div/mul/D$ miss latency by 1 cycle.
2013-08-24 14:44:04 -07:00
Andrew Waterman
d4a0db4575 Reflect ISA changes 2013-08-24 14:43:55 -07:00
Henry Cook
3a266cbbfa final Reg changes 2013-08-15 15:28:15 -07:00
Henry Cook
b570435847 Reg standardization 2013-08-13 17:50:02 -07:00
Henry Cook
1a9e43aa11 initial attempt at upgrade 2013-08-12 10:39:11 -07:00
Henry Cook
9abdf4e154 Make compatible with scala 2.10. List.sort deprecated. Refactor constants into package object. 2013-07-23 20:27:58 -07:00
Yunsup Lee
c837c1d800 fix bug in previous JALR commit
on commit tag 9a122c06d1bf11237d7fb0769d454a67bbb7400e
2013-05-21 18:28:44 -07:00
Andrew Waterman
28f914c3f2 don't JALR to speculatively-bypassed addresses
Technically not necessary, but probably improves performance.
2013-05-21 16:56:58 -07:00
Andrew Waterman
3a1b5f01b2 don't take interrupts while they're disabled!
a control bug allowed an interrupt to be taken on the instruction immediately
following an interrupt-disabling instruction (but not thereafter).
2013-05-19 23:27:47 -07:00
Andrew Waterman
50ccc20bf3 replace RDNPC with AUIPC 2013-04-22 04:20:15 -07:00
Andrew Waterman
8cbdeb2abf add LR/SC support 2013-04-04 17:07:09 -07:00
Andrew Waterman
fc46daecf6 don't flush pipeline on writes to side-effect-free PCRs
notably, K0, K1, and EPC
2013-04-04 17:07:09 -07:00
Andrew Waterman
d4a3351cfc expose pending interrupts in status register 2013-04-04 17:07:08 -07:00
Andrew Waterman
575bd3445a re-generalize scoreboard 2013-01-24 18:00:39 -08:00
Rimas Avizienis
63060bc0a8 minor tweaks for eos18 tapeout (SRAM r/w port ordering, etc) 2013-01-23 19:27:53 -08:00
Henry Cook
e1225c5114 standardize IO naming convention 2013-01-07 13:41:36 -08:00
Andrew Waterman
05f19b21d0 merge multiplier and divider 2012-12-12 02:22:47 -08:00