Howard Mao
4bda6b6757
fix bug in tlb refill
2015-09-26 21:27:36 -07:00
Howard Mao
6bf8f41cef
make sure passthrough requests are treated as vm_enabled = false
2015-09-26 20:29:51 -07:00
Howard Mao
c517d9f6e3
fix htif emulator constructor in vcs_main
2015-09-25 17:21:09 -07:00
Andrew Waterman
c3fff12ff0
Revert "replace remaining uses of Vec.fill"
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This reverts commit f7a0d125e83f8ca59d9913bb1db79cef5a6d344a.
2015-09-25 17:09:06 -07:00
Andrew Waterman
3b1da4c57e
Revert "replace remaining uses of Vec.fill"
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This reverts commit b6bb4e42127d1ed42b55ec8b859a4e074b347d47.
2015-09-25 17:06:57 -07:00
Andrew Waterman
20b7a82ab6
Use Vec.fill, not Vec.apply, when making Vec literals
2015-09-25 17:06:52 -07:00
Andrew Waterman
a08872c0e9
val -> def in static object
2015-09-25 17:05:28 -07:00
Andrew Waterman
e75674c0cb
Revert "replace remaining uses of Vec.fill"
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This reverts commit 16dca2186b95945ad2ba5f906113101de0726617.
2015-09-25 17:05:07 -07:00
Andrew Waterman
2179cb64ae
Let isRead be true for store-conditional
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This works around a deadlock bug in the L1 D$, and is arguably true.
2015-09-25 15:28:02 -07:00
Andrew Waterman
0bfb2962a6
Assume coh.isRead returns true for store-conditional
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This requires an uncore update.
2015-09-25 15:26:11 -07:00
Howard Mao
7b0167b92e
make sure SCR and PCR data width matches xLen
2015-09-25 12:13:22 -07:00
Howard Mao
0e67d824b4
fix NASTI interconnect bug
2015-09-25 12:12:34 -07:00
Howard Mao
308022210a
use updated NASTI channel constructors
2015-09-25 12:07:27 -07:00
Howard Mao
8c4ac0f4f3
make sure CSR/SCR data width matches xLen
2015-09-25 12:07:03 -07:00
Howard Mao
a9c6cced2d
fix bug in NASTIArbiter
2015-09-25 11:03:24 -07:00
Howard Mao
2e63fb291a
put sensible defaults for NASTI channel constructors
2015-09-25 10:09:25 -07:00
Howard Mao
0d763524ef
make sure conf address map scales with number of cores
2015-09-25 09:41:19 -07:00
Howard Mao
5e3f9115d3
make sure HTIF mem_mb doesn't exceed MMIOBase
2015-09-25 09:02:35 -07:00
Schuyler Eldridge
f200d0947a
Force C++ emulator to always use 1GB for MEM_SIZE
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Fixes #17
2015-09-24 23:56:41 -04:00
Howard Mao
c20ed350a0
even more Chisel3 compatability changes
2015-09-24 17:55:41 -07:00
Howard Mao
a66bdb1956
replace remaining uses of Vec.fill
2015-09-24 17:53:26 -07:00
Howard Mao
88b15dba60
replace remaining uses of Vec.fill
2015-09-24 17:51:38 -07:00
Howard Mao
d1f2d40a90
replace remaining uses of Vec.fill
2015-09-24 17:50:09 -07:00
Howard Mao
3ff830e118
ReorderQueue uses Vec of Bools instead of Bits for roq_free
2015-09-24 17:43:53 -07:00
Howard Mao
1c0111cc70
uncore merge commit
2015-09-24 17:10:45 -07:00
Howard Mao
83740dfaa5
Merge branch 'master' of github.com:ucb-bar/uncore
2015-09-24 17:10:09 -07:00
Howard Mao
8d4d8680bf
replace NASTIMasterIO and NASTISlaveIO with NASTIIO
2015-09-24 16:59:13 -07:00
Howard Mao
4a85c5a510
pull in hardfloat fixes
2015-09-24 16:58:49 -07:00
Howard Mao
3b86790c3f
replace NASTIMasterIO and NASTISlaveIO with NASTIIO
2015-09-24 16:58:20 -07:00
Howard Mao
e3d2207c72
Chisel3 compat: merge NASTIMasterIO and NASTISlaveIO so we do not depend on flip() modifying the object
2015-09-24 16:57:50 -07:00
ducky
ee6754daca
Fix clone -> cloneType
2015-09-24 16:18:25 -07:00
Scott Beamer
fbc6e695d3
remove bugs from float_fix
2015-09-23 16:11:47 -07:00
Scott Beamer
56daea793a
allow float_fix to take stdin (for piping)
2015-09-23 16:09:09 -07:00
Howard Mao
38a9b23ce7
add a flag to only log and dump after a certain number of cycles
2015-09-22 10:32:31 -07:00
Howard Mao
4496e8d4e2
make sure htif_emulator properly sets memory size
2015-09-22 10:32:31 -07:00
Howard Mao
56ecdff52d
Implement NASTI-based Mem/IO interconnect
2015-09-22 10:32:31 -07:00
Howard Mao
ee65f6a84d
get rid of Vec.fill in IOs
2015-09-22 10:30:09 -07:00
Howard Mao
9eb988a4c6
make sure access to invalid physical address treated as exception
2015-09-22 10:11:43 -07:00
Howard Mao
16c748576a
don't mux data_word_bypass between IOMSHR and cache
2015-09-22 10:10:57 -07:00
Howard Mao
d89bcd3922
modify csr file to bring in line with HTIF changes
2015-09-22 10:10:57 -07:00
Howard Mao
382faba4a6
Implement bypassing L1 data cache for MMIO
2015-09-22 10:10:57 -07:00
Howard Mao
b4d21148ec
get rid of NASTI error assertion
2015-09-22 09:43:42 -07:00
Howard Mao
64ab45e2e4
add RWX permission bits to address map
2015-09-22 09:43:22 -07:00
Howard Mao
27745204eb
ErrorSlave returns response of correct length for reads
2015-09-22 09:42:57 -07:00
Andrew Waterman
e72e5a34b5
Fix storage of SP values in DP registers
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The SFMA was zero-extending the SP value to 65 bits, rather than filling
the upper 32 bits with 1s. This meant that an FSD + FLD of that register
would not restore the value properly.
Also, minor code cleanup.
2015-09-21 12:20:44 -07:00
Andrew Waterman
c6bcc832a1
Chisel3: Don't use Vec.fill for IOs
2015-09-20 13:43:56 -07:00
Andrew Waterman
fd58c52250
Update to latest chisel
2015-09-20 13:37:53 -07:00
Howard Mao
4db6124b2a
NASTIErrorSlave should print address
2015-09-18 09:42:41 -07:00
Howard Mao
8b2341b1b1
use reorder queue instead of extra tag bit to determine TL g_type in NASTI -> TL converter
2015-09-18 09:41:37 -07:00
Colin Schmidt
6f85ed191e
Add rocketchip_addons to the list of chisel srcs requiring rebuild
2015-09-16 12:28:03 -07:00
