Christopher Celio
b55765f597
Bump riscv-tools
2015-08-26 16:08:45 -07:00
Christopher Celio
b1e845f370
Add space to README.md
2015-08-26 14:34:22 -07:00
Scott Beamer
b88c283b21
add travis support and tests
2015-08-25 13:29:20 -07:00
Scott Beamer
333c594d2a
respect environment's CXX
2015-08-25 13:26:14 -07:00
Scott Beamer
49ff021518
bump fpga repo
2015-08-21 15:39:59 -07:00
Albert Ou
3d6a060dc3
Bump Scala to 2.11.6
...
This change, originally part of commit b978083, was excluded from the
merge at commit 47494ec.
2015-08-10 23:52:58 -07:00
Henry Cook
bcf95b39e0
bump uncore
2015-08-10 20:08:50 -07:00
Henry Cook
005752e2a6
use the parameters used to create the original object
2015-08-10 14:43:17 -07:00
Colin Schmidt
cab12635f8
Merge master into rocc-fpu-port
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ebb33f2f4b658211960a4c6c023c139420c67212
2015-08-06 08:03:10 -07:00
Andrew Waterman
01fc61ba96
Don't construct so many Vecs
2015-08-05 18:43:59 -07:00
Howard Mao
a551a12d70
add missing Wire wrap in BasicCrossbar
2015-08-05 17:05:31 -07:00
Henry Cook
a3c9431ee2
bump all submodules for scala version
2015-08-05 16:50:38 -07:00
Andrew Waterman
eb6583d607
use cloneType in PhysicalNetworkIO
2015-08-05 16:47:49 -07:00
Andrew Waterman
9b038db34a
Upgrade scala to 2.11.6
2015-08-05 15:37:03 -07:00
Andrew Waterman
700910adff
Chisel3 compatibility fix for <>
2015-08-05 15:34:40 -07:00
Andrew Waterman
1718333f83
Don't use Vec as lvalue
2015-08-05 15:29:33 -07:00
Andrew Waterman
546205b174
Chisel3 compatibility: use >>Int instead of >>UInt
2015-08-05 15:29:03 -07:00
Andrew Waterman
798ddeb5f5
Chisel3 compatibility: use >>Int instead of >>UInt
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The latter doesn't contract widths anymore.
2015-08-04 13:15:17 -07:00
Andrew Waterman
2ff2b43c2c
Chisel3 compatibility: use >>Int instead of >>UInt
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The latter doesn't contract widths anymore.
2015-08-04 13:13:44 -07:00
Andrew Waterman
e469785f5e
bump scala to 2.11.6
2015-08-03 19:51:17 -07:00
Andrew Waterman
fb5524372d
bump scala to 2.11.6
2015-08-03 19:51:08 -07:00
Andrew Waterman
fb718f03c1
bump scala to 2.11.6
2015-08-03 19:50:58 -07:00
Andrew Waterman
d85c46bc60
Chisel3 bulk connect non-commutativity
2015-08-03 19:47:16 -07:00
Andrew Waterman
d4c94c6566
Chisel3 has different Vec semantics
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Vec(a, b) := c doesn't modify a and b in chisel3.
2015-08-03 19:08:00 -07:00
Andrew Waterman
34b9a7fdc5
Various Chisel3 compatibility changes
2015-08-03 18:54:56 -07:00
Andrew Waterman
77cf26aeba
Chisel3: Flip order of := and <>
2015-08-03 18:53:39 -07:00
Andrew Waterman
c345d72af4
Chisel3: Flip order of := and <>
2015-08-03 18:53:09 -07:00
Andrew Waterman
121e4fb511
Flip direction of some bulk connects
2015-08-03 18:01:14 -07:00
Andrew Waterman
a21979a2fa
Bits -> UInt
2015-08-03 18:01:06 -07:00
Andrew Waterman
ef319edc84
Bits -> UInt
2015-08-02 21:03:42 -07:00
Andrew Waterman
52fc34a138
Chisel3: bulk connect is not commutative
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We haven't decided if this is a FIRRTL limitation that we should relax,
or a backwards incompatibility we're forced to live with. Should make
for lively debate.
2015-08-01 21:11:25 -07:00
Andrew Waterman
9c7a41e8d3
Chisel3: bulk connect is not commutative
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We haven't decided if this is a FIRRTL limitation that we should relax,
or a backwards incompatibility we're forced to live with. Should make
for lively debate.
2015-08-01 21:09:00 -07:00
Andrew Waterman
6fc807f069
Chisel3: Avoid subword assignment
2015-08-01 21:08:35 -07:00
Andrew Waterman
6c0e1e33ab
Purge UInt := SInt assignments
2015-07-31 15:42:10 -07:00
Andrew Waterman
6d7cc37e87
Specify some uninferrable widths
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It's really scary that Chisel2 passed this stuff.
2015-07-31 14:23:52 -07:00
Andrew Waterman
45cf64dbd7
Use UInt instead of Vec[Bool]
2015-07-31 04:59:45 -07:00
Andrew Waterman
6d574f8c1b
Fix incompatible assignment
2015-07-31 00:59:34 -07:00
Andrew Waterman
377e17e811
Add Wire() wrap
2015-07-31 00:32:02 -07:00
Andrew Waterman
eb57433f43
Bits -> UInt
2015-07-30 23:57:53 -07:00
Andrew Waterman
57930e8a26
Chisel3 compatibility potpourri
2015-07-30 23:53:02 -07:00
Andrew Waterman
0686bdbe28
Avoid cross-module references
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You can't instantiate a Vec in one module and use it in another.
An idiosyncrasy of the Chisel2 implementation let this one slip by.
In this case, it's just a matter of using def instead of val.
2015-07-30 23:49:06 -07:00
Andrew Waterman
8f7b390353
UInt-> Bits; avoid mixed UInt/SInt code
2015-07-30 23:49:06 -07:00
Andrew Waterman
6c391e3b37
Use UInt(0), not UInt(width=0), for constant 0
2015-07-30 23:49:06 -07:00
Henry Cook
0c9a7817b6
Reduce outstanding mem accesses for FPGAConfig (to reduce MIFTagBits < 7)
2015-07-30 16:30:00 -07:00
Jim Lawson
db7258f887
Add junctions to the possible managed dependency list.
2015-07-30 15:11:23 -07:00
Jim Lawson
4c0f996808
Fix typo (juntion -> junctions).
2015-07-30 14:50:28 -07:00
Henry Cook
51c42083d0
Add new junctions repo as submodule (contains externally facing buses and peripherals).
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Bump all submodules.
2015-07-29 18:15:45 -07:00
Henry Cook
ee531dc97e
Add missing changes to emulator/Makefile
2015-07-29 18:15:21 -07:00
Henry Cook
d2a594fb57
new junctions repo has mem size constants
2015-07-29 18:05:54 -07:00
Henry Cook
c70b495f6d
moved buses to junctions repo
2015-07-29 18:04:30 -07:00
