riscv/rocket-chip
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Author SHA1 Message Date
Wesley W. Terpstra 11ec5b2cf4 bram: don't deal with multibeat; rely on the fragmenter 2016-07-22 14:51:05 -07:00
Wesley W. TerpstraandHoward Mao a52d418439 fragmenter: support multi-beat get/put via fragmenting to single-beat operations 2016-07-22 14:48:22 -07:00
Wesley W. TerpstraandHoward Mao 9ae23f18bd rocket: support asynchronous external busses 2016-07-19 14:52:56 -07:00
Wesley W. TerpstraandHoward Mao fa8317fec1 debug: add clock crossing primitives 2016-07-19 14:52:43 -07:00
Wesley W. Terpstra 46fc9744e2 rocket: add an AXI master port into the chip 2016-07-11 12:16:44 -07:00
Wesley W. Terpstra 8ac7fa5544 ext: support multiple external AHB/AXI ports 2016-07-11 12:16:39 -07:00
Wesley W. TerpstraandHoward Mao 39bee5198d Nasti Puts: decode wmask to determine addr_byte() and op_size() 
This change is TL0 specific; TL2 knows the op_size, and can use
this to do a much simpler one-hot decode of the address.
 2016-07-01 16:49:32 -07:00
Wesley W. TerpstraandHoward Mao 70d92995df TestConfigs: add comparator config 2016-06-09 15:43:13 -07:00
Wesley W. TerpstraandHoward Mao 3e51a8bb7a submodules: include new ComparatorTile 2016-06-09 15:43:13 -07:00
Wesley W. TerpstraandHenry Cook a1ebc73477 tilelink: don't accidentally make a malformed union 
Closes #55
 2016-06-09 10:44:00 -07:00
Wesley W. TerpstraandHenry Cook 31b72625aa ahb: allow no-ops to progress also when a slave is !hready 2016-06-09 10:41:12 -07:00
Wesley W. TerpstraandHenry Cook 7014eef339 ahb: fix bugs found using comparatortest 2016-06-09 10:41:11 -07:00
Wesley W. Terpstra 324cabc494 tilelink: wmask was double the width it should be 
When amo_offset = UInt(0), UIntToOH(amo_offset) = "b01", not b"1".
This meant that the amo wmask was double wide, making wmask() fat.
 2016-06-07 14:04:01 -07:00
Wesley W. TerpstraandAndrew Waterman 5495705acf Configs: enable AHB for FPGAs 2016-06-06 21:36:09 -07:00
Wesley W. TerpstraandAndrew Waterman ef27cc3a33 RocketChip: handle atomics only if needed 2016-06-06 21:36:03 -07:00
Wesley W. TerpstraandAndrew Waterman 3e0ec855cf RocketChip: add ahb mem interface 2016-06-06 21:35:59 -07:00
Wesley W. TerpstraandAndrew Waterman d2b505f2d2 RocketChip: rename mem to mem_axi in preparation for new bus type 2016-06-06 21:35:55 -07:00
Wesley W. TerpstraandAndrew Waterman 2086c0d603 Configs: add a parameter to control the memory subsystem interface 2016-06-06 21:35:43 -07:00
Wesley W. TerpstraandAndrew Waterman 2ddada1732 ahb: add mmio_ahb option 2016-06-06 21:35:39 -07:00
Wesley W. TerpstraandAndrew Waterman 31f1dcaf84 ahb: rename mmio outputs to mmio_axi 2016-06-06 21:35:34 -07:00
Wesley W. TerpstraandAndrew Waterman 7a24527448 ahb: make MMIO channels specifiy bus type (we will have more than one bridge) 2016-06-06 21:35:30 -07:00
Wesley W. TerpstraandAndrew Waterman f3a557b67b ahb: AHB parameters should be site specific 
Conflicts:
	src/main/scala/Configs.scala
 2016-06-06 21:35:24 -07:00
Wesley W. TerpstraandAndrew Waterman 11b3cee07a Ahb tweaks (#50) 
* ahb: handle tlDataBytes==1 and tlDataBeats==1 gracefully

I only now learned that chisel does not handle 0-width wires properly
and that log2Up and log2Ceil differ on 1. Fix-up code to handle this.

* ahb: optionally disable atomics => optimize to nothing

Trust the compiler the compiler to optimize away unused logic.
 2016-06-01 16:42:39 -07:00
Wesley W. TerpstraandAndrew Waterman 976d4d3184 ahb: AHB parameters should match TileLink parameters by default 
Closes #116
 2016-05-25 18:01:25 -07:00
Wesley W. TerpstraandAndrew Waterman 7f1792cba3 ahb: backport bridge to chisel2 
Closes #47
 2016-05-25 13:40:24 -07:00
Wesley W. TerpstraandAndrew Waterman da566e7d6a build: use local sbt when building firrtl 2016-05-25 11:48:03 -07:00
Wesley W. TerpstraandAndrew Waterman e19c5e5d2c IOMSHR: support atomic operations 2016-05-24 15:00:50 -07:00
Wesley W. Terpstra a012341d96 ahb: TileLink => AHB bridge, including atomics and bursts 2016-05-24 14:58:27 -07:00
Wesley W. Terpstra ace9362d81 ahb: amoalu does not need so many parameters! (i want to reuse it) 2016-05-24 14:58:27 -07:00
Wesley W. Terpstra 00d31dc5c5 bram: use new hasti definitions 2016-05-24 13:35:16 -07:00