Henry Cook
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a922b60152
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Merge branch 'master' of github.com:ucb-bar/reference-chip into network-refactor
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2013-01-07 14:23:49 -08:00 |
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Henry Cook
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f2cef8d8d2
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new IO names, set val/rdy low for unused network inputs, add src/dst setting for tiles, incoherent sig out of tilelink, bump chisel/rocket/uncore
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2013-01-07 14:19:55 -08:00 |
Andrew Waterman
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bbd010750f
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add missing #include
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2013-01-06 04:53:40 -08:00 |
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Andrew Waterman
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fd727bf8aa
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add some of the zedboard fpga infrastructure
you can elaborate the RTL in fpga/build/vcs-sim-rtl, but there's no harness
for VCS simulation yet.
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2013-01-06 03:58:10 -08:00 |
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Andrew Waterman
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03df2c3766
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update .gitignores
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2013-01-06 03:58:10 -08:00 |
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Henry Cook
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d0805359a5
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Refactored uncore conf
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2012-12-13 11:46:29 -08:00 |
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Henry Cook
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1d7f1a8182
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Removed dummy tile instances
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2012-12-12 16:44:03 -08:00 |
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Henry Cook
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0e73cc8c12
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Removed dummy tile instances
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2012-12-12 16:41:21 -08:00 |
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Henry Cook
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177909c955
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Initial version of phys/log network compiles
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2012-12-12 11:15:10 -08:00 |
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Henry Cook
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be4e5b8327
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Initial version of phys/log network compiles
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2012-12-12 00:06:14 -08:00 |
Yunsup Lee
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98c0ea9875
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push rocket, tests, and vt-libs
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2012-12-07 16:59:15 -08:00 |
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Andrew Waterman
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10a6a42a4a
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make vlsi use dram model by default
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2012-12-06 03:13:45 -08:00 |
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Andrew Waterman
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d911e635d6
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simplify c++ memory models; support +dramsim flag
works for both vlsi and emulator
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2012-12-04 07:04:26 -08:00 |
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Andrew Waterman
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5dfb388f03
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update to newest rocket
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2012-11-27 02:43:31 -08:00 |
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Andrew Waterman
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ea7029484e
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update to latest rocket
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2012-11-26 20:57:12 -08:00 |
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Andrew Waterman
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e12af07722
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update to newest rocket
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2012-11-25 04:40:46 -08:00 |
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Andrew Waterman
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9372912a9c
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update to newest rocket
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2012-11-20 05:42:44 -08:00 |
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Andrew Waterman
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6d47d18c2b
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catch sigterm to gracefully exit (fixes vcd)
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2012-11-20 05:40:44 -08:00 |
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Andrew Waterman
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7330deb13a
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print stack trace if elaboration fails
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2012-11-20 05:39:48 -08:00 |
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Yunsup Lee
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4d73e6e38a
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revamp vector yet again with new D$
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2012-11-18 03:14:22 -08:00 |
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Andrew Waterman
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7bcf59a18f
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support continous compilation via "make test"
for c++ emulator only, for now
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2012-11-17 19:58:18 -08:00 |
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Andrew Waterman
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b58214d7e3
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remove more global constants
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2012-11-17 17:25:43 -08:00 |
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Andrew Waterman
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cf05b604b3
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upgrade to new rocket; improve vlsi makefiles
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2012-11-17 07:21:29 -08:00 |
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Andrew Waterman
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672e904c86
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update to new rocket/uncore
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2012-11-16 02:41:50 -08:00 |
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Yunsup Lee
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1a91637673
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refactored vector queue interface
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2012-11-07 01:16:02 -08:00 |
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Yunsup Lee
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29d4c0b857
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refactored tlb
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2012-11-06 23:54:14 -08:00 |
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Andrew Waterman
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e2afae011a
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factor out global constants
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2012-11-06 08:18:40 -08:00 |
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Yunsup Lee
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1305372ce7
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refactor flush logic
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2012-11-05 23:01:08 -08:00 |
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Yunsup Lee
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9844ba1c1d
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revamp the vector unit with the new frontend
HAVE_PVFB is still broken, we need to multi-thread the frontend
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2012-11-05 01:44:02 -08:00 |
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Yunsup Lee
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dd6ee2571d
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add vector vm tests
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2012-11-04 19:29:56 -08:00 |
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Andrew Waterman
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0c372fc9ec
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refactor I$ config into RocketConfiguration
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2012-11-04 17:00:19 -08:00 |
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Andrew Waterman
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4ed2d614a2
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update to new rocket; retime fpu in dc-syn
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2012-11-04 16:43:02 -08:00 |
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Henry Cook
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538b23c223
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Initial version of using sbt tasks to elaborate chisel source and invoke backends' makefiles
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2012-10-23 12:52:59 -07:00 |
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Henry Cook
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17d2bd8926
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Initial version of sbt tasks (elaborate task with no parameters)
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2012-10-23 12:52:00 -07:00 |
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Yunsup Lee
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3edc1f42aa
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revamp the backup memory link in the vlsi backend
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2012-10-23 03:31:34 -07:00 |
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Andrew Waterman
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367b5489d1
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first crack at continuous compilation/testing flow
try it out: cd emulator; make test
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2012-10-19 04:09:07 -07:00 |
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Andrew Waterman
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1ad928cfe2
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directly integrate dramsim build
also, build it as a static library to simplify dependencies
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2012-10-18 18:59:37 -07:00 |
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Andrew Waterman
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edf0eeed01
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integrate updated rocket/uncore
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2012-10-18 17:51:41 -07:00 |
Miquel Moreto
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6d49dc51a0
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Fixed emulator Makefile + extra info in the README file
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2012-10-16 11:06:48 -07:00 |
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Miquel Moreto
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aa3dc422b4
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Added first README file
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2012-10-15 10:54:47 -07:00 |
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Miquel Moreto
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5d75ddc553
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Added dramsim2 memory model to the emulator backend
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2012-10-14 14:06:28 -07:00 |
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Yunsup Lee
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34da073077
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fix tab
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2012-10-11 12:09:49 -07:00 |
Huy Vo
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f67f8829e3
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new rocket + uncore tags, added uncore dependencies to Makefrag
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2012-10-10 15:44:19 -07:00 |
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Andrew Waterman
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7fd4eb6afd
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update uncore
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2012-10-09 18:05:32 -07:00 |
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Andrew Waterman
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c3236e6ee6
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add missing symlink and update uncore
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2012-10-09 17:51:33 -07:00 |
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Huy Vo
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24a49350cc
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reference chip design
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2012-10-09 13:05:56 -07:00 |
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Huy Vo
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93a0182b96
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everything to get emulator working
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2012-10-01 19:30:11 -07:00 |
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Huy Vo
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8560ea6e40
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rename hwacha -> riscv-hwacha, chisel, riscv-asm-tests-bmarks, and uncore tags
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2012-10-01 19:12:18 -07:00 |
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Huy Vo
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084a0d31c3
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initial commit, all the relevant submodules
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2012-09-26 17:46:17 -07:00 |