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Commit Graph

456 Commits

Author SHA1 Message Date
Andrew Waterman
a0378c5d2f remove faulting TLB entry after page fault
this vastly reduces the frequency with which the TLB must be flushed
2012-04-26 02:29:30 -07:00
Andrew Waterman
6d8fc74378 fix DTLB permissions bug 2012-04-26 02:29:30 -07:00
Henry Cook
1ed89f1cab Fixed abort bug: removed uneeded state, added mshr guard on xact_abort.valid and xact_init.ready on same cycle 2012-04-24 17:17:42 -07:00
Henry Cook
55e86b5cf4 Fixed coherence bug: probe counting for single tile 2012-04-24 17:17:13 -07:00
Henry Cook
a39080d0b1 Fixed abort bug: xact_abort.ready was not pinned high 2012-04-24 17:16:40 -07:00
Andrew Waterman
fb4408b150 fix AMO replay/coherence deadlock 2012-04-15 22:56:02 -07:00
Andrew Waterman
724735f13f fix writeback bug 2012-04-13 03:16:48 -07:00
Andrew Waterman
00d934cfac fix coherence bugs in cache 2012-04-12 21:57:37 -07:00
Henry Cook
fef58f1b3a Policy determined by constants. MSI policy added. 2012-04-11 17:56:59 -07:00
Andrew Waterman
c0ec3794bf coherence mostly works now 2012-04-10 02:22:45 -07:00
Henry Cook
3cdd166153 Refactored coherence as member rather than trait. MI and MEI protocols. 2012-04-10 00:09:58 -07:00
Henry Cook
9c8f849f50 defined abstract coherence traits in base trait, added Incoherent trait, cleaned up incoherent policy 2012-04-09 23:29:32 -07:00
Henry Cook
551e09c9d5 changed coherence type width names to represent max sizes for all protocols 2012-04-09 23:29:32 -07:00
Henry Cook
0b4937f70f changed coherence message type names 2012-04-09 23:29:31 -07:00
Henry Cook
ed79ec98f7 Refactored coherence better from uncore hub, better coherence function names 2012-04-09 23:29:31 -07:00
Andrew Waterman
aee9378712 fix coherence bug with multiple probe replies 2012-04-09 21:40:35 -07:00
Huy Vo
c9c3bd02bc kill mem stage if fpu nacks in mem stage 2012-04-01 17:02:32 -07:00
Andrew Waterman
7f254d9670 refine FP bugfixes 2012-04-01 14:52:33 -07:00
Huy Vo
c7c35322c2 two bug fixes to fpu 2012-03-31 22:23:51 -07:00
Andrew Waterman
a09e8d1c55 remove I$ prefetcher for now
there's a bug in it, and I don't have time to fix it at the moment.
2012-03-27 15:43:56 -07:00
Andrew Waterman
452876af37 fence on vvcfg; implement fence.v.g correctly 2012-03-27 14:49:00 -07:00
Yunsup Lee
bb704dc0c9 fix vector length calc bug, thanks chris and andrew 2012-03-27 12:04:07 -07:00
Andrew Waterman
6bda8674bd no dessert tonight :( 2012-03-26 23:50:09 -07:00
Yunsup Lee
a70f0414fa fix a workaroundable bug 2012-03-26 20:51:54 -07:00
Yunsup Lee
32d95e9594 fix -1:0 index problem for direct map case 2012-03-26 17:00:01 -07:00
Andrew Waterman
e2fe525fb6 remove bug from dessert 2012-03-26 14:18:57 -07:00
Yunsup Lee
e6b0e565de turn HAVE_VEC on 2012-03-26 01:21:39 -07:00
Andrew Waterman
5f53cd4ac1 reduce HTIF width 2012-03-25 23:49:59 -07:00
Andrew Waterman
ef505de017 reduce HTIF width 2012-03-25 23:49:45 -07:00
Andrew Waterman
31f0b600fd add dessert 2012-03-25 23:03:20 -07:00
Andrew Waterman
1666d3fbd7 loop host.in to host.out during reset 2012-03-25 21:45:10 -07:00
Andrew Waterman
f62a02ab54 remove dumb stuff in top.scala 2012-03-25 21:30:01 -07:00
Andrew Waterman
88bf8a4f23 add mem serdes unit 2012-03-25 17:03:58 -07:00
Andrew Waterman
7fa93da4f5 add backup memory port (disabled for now) 2012-03-25 15:49:32 -07:00
Yunsup Lee
1f33f6bb58 HAVE_VEC is on 2012-03-24 20:54:43 -07:00
Andrew Waterman
86d56ff67b refactor cpu/i$/d$ into Tile (rather than Top) 2012-03-24 16:57:28 -07:00
Andrew Waterman
3a487ac89b improve htif<->pcr interface 2012-03-24 16:57:28 -07:00
Andrew Waterman
54fa6f660d new supervisor mode 2012-03-24 13:03:31 -07:00
Yunsup Lee
65929a62e3 fix reset value for appvl 2012-03-22 15:32:04 -07:00
Yunsup Lee
aaed0241af get rid of vxcptwait 2012-03-21 15:09:04 -07:00
Yunsup Lee
023734175d now fence stalls in decode 2012-03-20 17:10:05 -07:00
Yunsup Lee
e450e3aa40 fix irt counter bug regarding vector stuff 2012-03-20 17:09:54 -07:00
Yunsup Lee
7d7d7f49f9 change the tlb arbiter to a round robing one 2012-03-20 15:21:36 -07:00
Yunsup Lee
1cddd5de56 fix amo locking up problem 2012-03-20 02:16:28 -07:00
Yunsup Lee
56cb9b7a63 fix bug in coherence hub, specifically in abort handling logic 2012-03-20 02:16:28 -07:00
Yunsup Lee
c036fff79c fix id interrupt signal 2012-03-19 15:13:57 -07:00
Yunsup Lee
0edea00166 now HAVE_VEC is true, since it passes the emulator 2012-03-19 03:10:00 -07:00
Yunsup Lee
264732556f fixes to match verilog X semantics 2012-03-19 03:10:00 -07:00
Andrew Waterman
bd27d0fab2 can now take interrupts on stalled instructions 2012-03-19 01:02:06 -07:00
Andrew Waterman
2ed0be65f9 fix RRArbiter 2012-03-19 00:19:33 -07:00
Yunsup Lee
ba06cd953e add chosen 2012-03-18 20:43:17 -07:00
Andrew Waterman
c4a91303fb update vector fence names and encoding 2012-03-18 20:42:38 -07:00
Yunsup Lee
2a01f558ba fix unmasked valid bug in ctrl_vec 2012-03-18 19:55:24 -07:00
Yunsup Lee
98e10ddc3c update vector exception instructions 2012-03-18 16:36:12 -07:00
Yunsup Lee
7493d55d3f add pf fault handling 2012-03-18 15:06:39 -07:00
Yunsup Lee
62ada5ea9e hookup vitlb ptw port 2012-03-17 23:01:06 -07:00
Yunsup Lee
b793d63182 no vector interrupt masking 2012-03-17 23:01:06 -07:00
Yunsup Lee
8a4f95e617 changes to xcpt handling 2012-03-17 17:50:37 -07:00
Yunsup Lee
8c50c81b81 drop vec_irq_aux pcr register, now everything goes through badvaddr 2012-03-17 14:03:57 -07:00
Yunsup Lee
3b4680a834 add vitlb exception port 2012-03-17 14:03:33 -07:00
Andrew Waterman
a47eeb9571 retime D$ bypass into beginning of EX stage 2012-03-16 18:35:54 -07:00
Andrew Waterman
6c26921766 reduce D$ critical path through page table walker
costs an extra cycle per page table level to resolve a TLB miss. too bad.
2012-03-16 18:35:54 -07:00
Yunsup Lee
d38603a4ee change number of tlb entries 2012-03-16 17:08:03 -07:00
Andrew Waterman
f0157b9e2a fix coherence bug
popping wrong store dependence queue
2012-03-16 01:24:07 -07:00
Andrew Waterman
cfca2d1411 clean up cache interfaces; avoid reserved keywords 2012-03-16 00:44:16 -07:00
Andrew Waterman
820884c7e6 fix probes for smaller cache sizes
address bits (pgidx_bits-1,taglsb) were omitted from tag checks.
2012-03-15 23:08:30 -07:00
Andrew Waterman
4684171ac6 fix fence.i for associative caches 2012-03-15 21:23:21 -07:00
Andrew Waterman
2b0bc8df2b use divided clk for htif. UDPATE YOUR FESVR
by default, we now load programs via a backdoor, because otherwise
it takes too long to simulate.
2012-03-15 18:36:51 -07:00
Yunsup Lee
ba566f246e change icache parameters 2012-03-15 15:35:12 -07:00
Yunsup Lee
72006160dc fix vxcptwait inst bug, it was incorrect when exception_valid was on before do_xcptwait 2012-03-15 02:10:21 -07:00
Yunsup Lee
f972977da1 refactored VMU, now uses one skid buffer 2012-03-15 01:10:17 -07:00
Henry Cook
b5fa86e844 4-way associative by default 2012-03-14 17:51:12 -07:00
Andrew Waterman
7dde7099d2 use broadcast hub and coherent HTIF 2012-03-14 16:44:35 -07:00
Yunsup Lee
b19d783fbd add vector irq handler 2012-03-14 14:15:28 -07:00
Yunsup Lee
040d62f372 refactored vector exception handling interface 2012-03-13 23:45:34 -07:00
Yunsup Lee
b100544b25 datapath to read out vector state 2012-03-13 23:45:34 -07:00
Yunsup Lee
5655dbd5da add vvcfg and vtcfg instructions 2012-03-13 23:45:34 -07:00
Andrew Waterman
ab6c9350db fix minor coherence bugs 2012-03-13 19:10:54 -07:00
Andrew Waterman
1788c34113 parameterize broadcast hub by # of tiles 2012-03-13 17:12:01 -07:00
Andrew Waterman
1492457df5 add probe replies to HTIF 2012-03-13 16:56:47 -07:00
Andrew Waterman
b0f798962c add probe unit 2012-03-13 16:43:51 -07:00
Huy Vo
fdffb124e3 Merge branch 'master' of github.com:ucb-bar/riscv-rocket 2012-03-13 12:34:39 -07:00
Huy Vo
6fd1527476 fix to rocket vec_dpath, updating makefiles to run xcpt test cases 2012-03-13 12:34:02 -07:00
Henry Cook
287bc1c262 Further refinement of tag_match/tag_hit signals 2012-03-13 11:48:12 -07:00
Andrew Waterman
d76b05bde1 fix way selection on D$ write upgrades 2012-03-13 02:21:02 -07:00
Andrew Waterman
fd29e00db0 support non-power-of-2 queue sizes
need to manually wrap queue pointers.
2012-03-13 01:58:28 -07:00
Henry Cook
cbf7b13341 fix hit logic for amos 2012-03-12 22:01:52 -07:00
Henry Cook
6229a33dc4 fixed cache controller flush unit deadlock 2012-03-12 22:01:52 -07:00
Henry Cook
ea0775643b fixed abort bug 2012-03-12 22:01:52 -07:00
Yunsup Lee
1ba5e7b865 changes to the vector exception interface 2012-03-11 21:38:47 -07:00
Yunsup Lee
113a94a21d add vector hold waits 2012-03-11 16:29:19 -07:00
Yunsup Lee
e42a4c767e don't stall on vector fences, keep replaying 2012-03-11 16:29:19 -07:00
Henry Cook
c5dd37ae80 bugfix in locking arbiter 2012-03-11 15:47:27 -07:00
Henry Cook
4ebf637642 More broadcast hub bugfixes 2012-03-11 14:17:27 -07:00
Henry Cook
a4d0025187 fix icache prefetch global_xact_id bug 2012-03-11 00:50:11 -08:00
Yunsup Lee
1aa4b0e93d going back to null coherence hub 2012-03-10 20:16:20 -08:00
Andrew Waterman
8ffdac9526 fix D$ store-upgrade bug
loads to the same address as stores that cause an upgrade
could return the old value
2012-03-10 15:50:10 -08:00
Andrew Waterman
4f4b990a4f fix null hub store ack bug 2012-03-10 15:19:12 -08:00
Yunsup Lee
44ff22a26f vector exception handler now handles prefetches correctly 2012-03-10 12:54:36 -08:00
Andrew Waterman
7eb73c325e fix signedness of zero fmul results
We were using the FMA unit to compute rs1 * rs2 + 0.0 for fmul,
which incorrectly computes +0.0 when rs1 * rs2 == -0.0.  Now we
add -0.0 if rs1*rs2 is negative.
2012-03-10 00:21:51 -08:00