new supervisor mode
This commit is contained in:
Andrew Waterman committed
1 parent
65929a62e3
commit
54fa6f660d
8 files changed
+287
-319
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@@ -63,7 +63,6 @@ object Constants
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val WB_X = UFix(0, 3);
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val WB_PC = UFix(0, 3);
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val WB_PCR = UFix(1, 3);
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val WB_ALU = UFix(2, 3);
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val WB_TSC = UFix(4, 3);
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val WB_IRT = UFix(5, 3);
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@@ -117,10 +116,12 @@ object Constants
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val M_XA_MAX = Bits("b1101", 4);
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val M_XA_MINU = Bits("b1110", 4);
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val M_XA_MAXU = Bits("b1111", 4);
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val I_X = Bits(0,2);
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val I_DI = Bits(1,2);
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val I_EI = Bits(2,2);
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val PCR_N = Bits(0,3)
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val PCR_F = Bits(1,3) // mfpcr
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val PCR_T = Bits(4,3) // mtpcr
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val PCR_C = Bits(6,3) // clearpcr
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val PCR_S = Bits(7,3) // setpcr
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val SYNC_N = Bits(0,2);
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val SYNC_D = Bits(1,2);
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@@ -137,12 +138,14 @@ object Constants
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val PCR_SEND_IPI = UFix( 8, 5);
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val PCR_CLR_IPI = UFix( 9, 5);
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val PCR_COREID = UFix(10, 5);
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val PCR_IMPL = UFix(11, 5);
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val PCR_K0 = UFix(12, 5);
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val PCR_K1 = UFix(13, 5);
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val PCR_TOHOST = UFix(16, 5);
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val PCR_FROMHOST = UFix(17, 5);
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val PCR_VECBANK = UFix(18, 5);
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val PCR_VECCFG = UFix(19, 5);
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val PCR_RESET = UFix(29, 5);
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val PCR_TOHOST = UFix(30, 5);
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val PCR_FROMHOST = UFix(31, 5);
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// definition of bits in PCR status reg
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val SR_ET = 0; // enable traps
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@@ -151,9 +154,15 @@ object Constants
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val SR_EC = 3; // enable compressed instruction encoding
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val SR_PS = 4; // mode stack bit
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val SR_S = 5; // user/supervisor mode
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val SR_UX = 6; // 64 bit user mode
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val SR_SX = 7; // 64 bit supervisor mode
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val SR_VM = 16; // VM enable
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val SR_U64 = 6; // 64 bit user mode
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val SR_S64 = 7; // 64 bit supervisor mode
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val SR_VM = 8 // VM enable
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val SR_IM = 16 // interrupt mask
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val SR_IM_WIDTH = 8
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val CAUSE_INTERRUPT = 32
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val IRQ_IPI = 5
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val IRQ_TIMER = 7
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val COREID = 0;
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val PADDR_BITS = 40;
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+219
-244
@@ -30,8 +30,7 @@ class ioCtrlDpath extends Bundle()
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val div_fn = UFix(2, OUTPUT);
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val sel_wa = Bool(OUTPUT);
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val sel_wb = UFix(3, OUTPUT);
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val ren_pcr = Bool(OUTPUT);
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val wen_pcr = Bool(OUTPUT);
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val pcr = UFix(3, OUTPUT)
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val id_eret = Bool(OUTPUT);
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val wb_eret = Bool(OUTPUT);
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val mem_load = Bool(OUTPUT);
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@@ -43,12 +42,9 @@ class ioCtrlDpath extends Bundle()
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val wb_valid = Bool(OUTPUT)
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val flush_inst = Bool(OUTPUT);
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val ex_mem_type = UFix(3,OUTPUT)
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// enable/disable interrupts
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val irq_enable = Bool(OUTPUT);
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val irq_disable = Bool(OUTPUT);
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// exception handling
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val exception = Bool(OUTPUT);
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val cause = UFix(5,OUTPUT);
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val cause = UFix(6,OUTPUT);
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val badvaddr_wen = Bool(OUTPUT); // high for a load/store access fault
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val vec_irq_aux_wen = Bool(OUTPUT)
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// inputs from datapath
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@@ -66,7 +62,7 @@ class ioCtrlDpath extends Bundle()
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val ex_waddr = UFix(5,INPUT); // write addr from execute stage
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val mem_waddr = UFix(5,INPUT); // write addr from memory stage
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val wb_waddr = UFix(5,INPUT); // write addr from writeback stage
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val status = Bits(17, INPUT);
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val status = Bits(32, INPUT);
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val sboard_clr = Bool(INPUT);
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val sboard_clra = UFix(5, INPUT);
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val fp_sboard_clr = Bool(INPUT);
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@@ -97,217 +93,217 @@ object rocketCtrlDecode
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val xpr64 = Y;
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val decode_default =
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// vfence
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// | eret
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// | | syscall
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// vec_val mem_val mul_val div_val renpcr | | | privileged
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// val | brtype renx2 renx1 s_alu2 dw alu | mem_cmd mem_type| mul_fn | div_fn wen s_wa s_wb | wenpcr irq sync | | | | replay_next
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// | | | | | | | | | | | | | | | | | | | | | | | | | | |
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List(N, N,BR_N, REN_N,REN_N,A2_X, DW_X, FN_X, M_N,M_X, MT_X, N,MUL_X, N,DIV_X, WEN_N,WA_X, WB_X, REN_N,WEN_N,I_X ,SYNC_N,N,N,N,N,N)
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// vfence
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// | eret
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// | | syscall
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// vec_val mem_val mul_val div_val pcr | | | privileged
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// val | brtype renx2 renx1 s_alu2 dw alu | mem_cmd mem_type| mul_fn | div_fn wen s_wa s_wb | sync | | | | replay_next
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// | | | | | | | | | | | | | | | | | | | | | | | | |
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List(N, N,BR_N, REN_N,REN_N,A2_X, DW_X, FN_X, M_N,M_X, MT_X, N,MUL_X, N,DIV_X, WEN_N,WA_X, WB_X, PCR_N,SYNC_N,N,N,N,N,N)
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val xdecode = Array(
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// vfence
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// | eret
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// | | syscall
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// vec_val mem_val mul_val div_val renpcr | | | privileged
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// val | brtype renx2 renx1 s_alu2 dw alu | mem_cmd mem_type| mul_fn | div_fn wen s_wa s_wb | wenpcr irq sync | | | | replay_next
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// | | | | | | | | | | | | | | | | | | | | | | | | | | |
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BNE-> List(Y, N,BR_NE, REN_Y,REN_Y,A2_BTYPE,DW_X, FN_ADD, M_N,M_X, MT_X, N,MUL_X, N,DIV_X, WEN_N,WA_X, WB_X, REN_N,WEN_N,I_X ,SYNC_N,N,N,N,N,N),
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BEQ-> List(Y, N,BR_EQ, REN_Y,REN_Y,A2_BTYPE,DW_X, FN_ADD, M_N,M_X, MT_X, N,MUL_X, N,DIV_X, WEN_N,WA_X, WB_X, REN_N,WEN_N,I_X ,SYNC_N,N,N,N,N,N),
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BLT-> List(Y, N,BR_LT, REN_Y,REN_Y,A2_BTYPE,DW_X, FN_ADD, M_N,M_X, MT_X, N,MUL_X, N,DIV_X, WEN_N,WA_X, WB_X, REN_N,WEN_N,I_X ,SYNC_N,N,N,N,N,N),
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BLTU-> List(Y, N,BR_LTU,REN_Y,REN_Y,A2_BTYPE,DW_X, FN_ADD, M_N,M_X, MT_X, N,MUL_X, N,DIV_X, WEN_N,WA_X, WB_X, REN_N,WEN_N,I_X ,SYNC_N,N,N,N,N,N),
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BGE-> List(Y, N,BR_GE, REN_Y,REN_Y,A2_BTYPE,DW_X, FN_ADD, M_N,M_X, MT_X, N,MUL_X, N,DIV_X, WEN_N,WA_X, WB_X, REN_N,WEN_N,I_X ,SYNC_N,N,N,N,N,N),
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BGEU-> List(Y, N,BR_GEU,REN_Y,REN_Y,A2_BTYPE,DW_X, FN_ADD, M_N,M_X, MT_X, N,MUL_X, N,DIV_X, WEN_N,WA_X, WB_X, REN_N,WEN_N,I_X ,SYNC_N,N,N,N,N,N),
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// vfence
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// | eret
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// | | syscall
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// vec_val mem_val mul_val div_val pcr | | | privileged
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// val | brtype renx2 renx1 s_alu2 dw alu | mem_cmd mem_type| mul_fn | div_fn wen s_wa s_wb | wsync | | | | replay_next
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// | | | | | | | | | | | | | | | | | | | | | | | | |
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BNE-> List(Y, N,BR_NE, REN_Y,REN_Y,A2_BTYPE,DW_X, FN_ADD, M_N,M_X, MT_X, N,MUL_X, N,DIV_X, WEN_N,WA_X, WB_X, PCR_N,SYNC_N,N,N,N,N,N),
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BEQ-> List(Y, N,BR_EQ, REN_Y,REN_Y,A2_BTYPE,DW_X, FN_ADD, M_N,M_X, MT_X, N,MUL_X, N,DIV_X, WEN_N,WA_X, WB_X, PCR_N,SYNC_N,N,N,N,N,N),
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BLT-> List(Y, N,BR_LT, REN_Y,REN_Y,A2_BTYPE,DW_X, FN_ADD, M_N,M_X, MT_X, N,MUL_X, N,DIV_X, WEN_N,WA_X, WB_X, PCR_N,SYNC_N,N,N,N,N,N),
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BLTU-> List(Y, N,BR_LTU,REN_Y,REN_Y,A2_BTYPE,DW_X, FN_ADD, M_N,M_X, MT_X, N,MUL_X, N,DIV_X, WEN_N,WA_X, WB_X, PCR_N,SYNC_N,N,N,N,N,N),
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BGE-> List(Y, N,BR_GE, REN_Y,REN_Y,A2_BTYPE,DW_X, FN_ADD, M_N,M_X, MT_X, N,MUL_X, N,DIV_X, WEN_N,WA_X, WB_X, PCR_N,SYNC_N,N,N,N,N,N),
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BGEU-> List(Y, N,BR_GEU,REN_Y,REN_Y,A2_BTYPE,DW_X, FN_ADD, M_N,M_X, MT_X, N,MUL_X, N,DIV_X, WEN_N,WA_X, WB_X, PCR_N,SYNC_N,N,N,N,N,N),
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J-> List(Y, N,BR_J, REN_N,REN_N,A2_JTYPE,DW_X, FN_ADD, M_N,M_X, MT_X, N,MUL_X, N,DIV_X, WEN_N,WA_X, WB_X, REN_N,WEN_N,I_X ,SYNC_N,N,N,N,N,N),
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JAL-> List(Y, N,BR_J, REN_N,REN_N,A2_JTYPE,DW_X, FN_ADD, M_N,M_X, MT_X, N,MUL_X, N,DIV_X, WEN_Y,WA_RA,WB_PC, REN_N,WEN_N,I_X ,SYNC_N,N,N,N,N,N),
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JALR_C-> List(Y, N,BR_JR, REN_N,REN_Y,A2_ITYPE,DW_XPR,FN_ADD, M_N,M_X, MT_X, N,MUL_X, N,DIV_X, WEN_Y,WA_RD,WB_PC, REN_N,WEN_N,I_X ,SYNC_N,N,N,N,N,N),
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JALR_J-> List(Y, N,BR_JR, REN_N,REN_Y,A2_ITYPE,DW_XPR,FN_ADD, M_N,M_X, MT_X, N,MUL_X, N,DIV_X, WEN_Y,WA_RD,WB_PC, REN_N,WEN_N,I_X ,SYNC_N,N,N,N,N,N),
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JALR_R-> List(Y, N,BR_JR, REN_N,REN_Y,A2_ITYPE,DW_XPR,FN_ADD, M_N,M_X, MT_X, N,MUL_X, N,DIV_X, WEN_Y,WA_RD,WB_PC, REN_N,WEN_N,I_X ,SYNC_N,N,N,N,N,N),
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RDNPC-> List(Y, N,BR_N, REN_N,REN_Y,A2_ITYPE,DW_XPR,FN_ADD, M_N,M_X, MT_X, N,MUL_X, N,DIV_X, WEN_Y,WA_RD,WB_PC, REN_N,WEN_N,I_X ,SYNC_N,N,N,N,N,N),
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J-> List(Y, N,BR_J, REN_N,REN_N,A2_JTYPE,DW_X, FN_ADD, M_N,M_X, MT_X, N,MUL_X, N,DIV_X, WEN_N,WA_X, WB_X, PCR_N,SYNC_N,N,N,N,N,N),
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JAL-> List(Y, N,BR_J, REN_N,REN_N,A2_JTYPE,DW_X, FN_ADD, M_N,M_X, MT_X, N,MUL_X, N,DIV_X, WEN_Y,WA_RA,WB_PC, PCR_N,SYNC_N,N,N,N,N,N),
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JALR_C-> List(Y, N,BR_JR, REN_N,REN_Y,A2_ITYPE,DW_XPR,FN_ADD, M_N,M_X, MT_X, N,MUL_X, N,DIV_X, WEN_Y,WA_RD,WB_PC, PCR_N,SYNC_N,N,N,N,N,N),
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JALR_J-> List(Y, N,BR_JR, REN_N,REN_Y,A2_ITYPE,DW_XPR,FN_ADD, M_N,M_X, MT_X, N,MUL_X, N,DIV_X, WEN_Y,WA_RD,WB_PC, PCR_N,SYNC_N,N,N,N,N,N),
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JALR_R-> List(Y, N,BR_JR, REN_N,REN_Y,A2_ITYPE,DW_XPR,FN_ADD, M_N,M_X, MT_X, N,MUL_X, N,DIV_X, WEN_Y,WA_RD,WB_PC, PCR_N,SYNC_N,N,N,N,N,N),
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RDNPC-> List(Y, N,BR_N, REN_N,REN_Y,A2_ITYPE,DW_XPR,FN_ADD, M_N,M_X, MT_X, N,MUL_X, N,DIV_X, WEN_Y,WA_RD,WB_PC, PCR_N,SYNC_N,N,N,N,N,N),
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LB-> List(Y, N,BR_N, REN_N,REN_Y,A2_ITYPE,DW_XPR,FN_ADD, M_Y,M_XRD, MT_B, N,MUL_X, N,DIV_X, WEN_Y,WA_RD,WB_ALU,REN_N,WEN_N,I_X ,SYNC_N,N,N,N,N,N),
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LH-> List(Y, N,BR_N, REN_N,REN_Y,A2_ITYPE,DW_XPR,FN_ADD, M_Y,M_XRD, MT_H, N,MUL_X, N,DIV_X, WEN_Y,WA_RD,WB_ALU,REN_N,WEN_N,I_X ,SYNC_N,N,N,N,N,N),
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LW-> List(Y, N,BR_N, REN_N,REN_Y,A2_ITYPE,DW_XPR,FN_ADD, M_Y,M_XRD, MT_W, N,MUL_X, N,DIV_X, WEN_Y,WA_RD,WB_ALU,REN_N,WEN_N,I_X ,SYNC_N,N,N,N,N,N),
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LD-> List(xpr64,N,BR_N, REN_N,REN_Y,A2_ITYPE,DW_XPR,FN_ADD, M_Y,M_XRD, MT_D, N,MUL_X, N,DIV_X, WEN_Y,WA_RD,WB_ALU,REN_N,WEN_N,I_X ,SYNC_N,N,N,N,N,N),
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LBU-> List(Y, N,BR_N, REN_N,REN_Y,A2_ITYPE,DW_XPR,FN_ADD, M_Y,M_XRD, MT_BU,N,MUL_X, N,DIV_X, WEN_Y,WA_RD,WB_ALU,REN_N,WEN_N,I_X ,SYNC_N,N,N,N,N,N),
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LHU-> List(Y, N,BR_N, REN_N,REN_Y,A2_ITYPE,DW_XPR,FN_ADD, M_Y,M_XRD, MT_HU,N,MUL_X, N,DIV_X, WEN_Y,WA_RD,WB_ALU,REN_N,WEN_N,I_X ,SYNC_N,N,N,N,N,N),
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LWU-> List(xpr64,N,BR_N, REN_N,REN_Y,A2_ITYPE,DW_XPR,FN_ADD, M_Y,M_XRD, MT_WU,N,MUL_X, N,DIV_X, WEN_Y,WA_RD,WB_ALU,REN_N,WEN_N,I_X ,SYNC_N,N,N,N,N,N),
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SB-> List(Y, N,BR_N, REN_Y,REN_Y,A2_BTYPE,DW_XPR,FN_ADD, M_Y,M_XWR, MT_B, N,MUL_X, N,DIV_X, WEN_N,WA_X, WB_ALU,REN_N,WEN_N,I_X ,SYNC_N,N,N,N,N,N),
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SH-> List(Y, N,BR_N, REN_Y,REN_Y,A2_BTYPE,DW_XPR,FN_ADD, M_Y,M_XWR, MT_H, N,MUL_X, N,DIV_X, WEN_N,WA_X, WB_ALU,REN_N,WEN_N,I_X ,SYNC_N,N,N,N,N,N),
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SW-> List(Y, N,BR_N, REN_Y,REN_Y,A2_BTYPE,DW_XPR,FN_ADD, M_Y,M_XWR, MT_W, N,MUL_X, N,DIV_X, WEN_N,WA_X, WB_ALU,REN_N,WEN_N,I_X ,SYNC_N,N,N,N,N,N),
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SD-> List(xpr64,N,BR_N, REN_Y,REN_Y,A2_BTYPE,DW_XPR,FN_ADD, M_Y,M_XWR, MT_D, N,MUL_X, N,DIV_X, WEN_N,WA_X, WB_ALU,REN_N,WEN_N,I_X ,SYNC_N,N,N,N,N,N),
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LB-> List(Y, N,BR_N, REN_N,REN_Y,A2_ITYPE,DW_XPR,FN_ADD, M_Y,M_XRD, MT_B, N,MUL_X, N,DIV_X, WEN_Y,WA_RD,WB_ALU,PCR_N,SYNC_N,N,N,N,N,N),
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LH-> List(Y, N,BR_N, REN_N,REN_Y,A2_ITYPE,DW_XPR,FN_ADD, M_Y,M_XRD, MT_H, N,MUL_X, N,DIV_X, WEN_Y,WA_RD,WB_ALU,PCR_N,SYNC_N,N,N,N,N,N),
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LW-> List(Y, N,BR_N, REN_N,REN_Y,A2_ITYPE,DW_XPR,FN_ADD, M_Y,M_XRD, MT_W, N,MUL_X, N,DIV_X, WEN_Y,WA_RD,WB_ALU,PCR_N,SYNC_N,N,N,N,N,N),
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LD-> List(xpr64,N,BR_N, REN_N,REN_Y,A2_ITYPE,DW_XPR,FN_ADD, M_Y,M_XRD, MT_D, N,MUL_X, N,DIV_X, WEN_Y,WA_RD,WB_ALU,PCR_N,SYNC_N,N,N,N,N,N),
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LBU-> List(Y, N,BR_N, REN_N,REN_Y,A2_ITYPE,DW_XPR,FN_ADD, M_Y,M_XRD, MT_BU,N,MUL_X, N,DIV_X, WEN_Y,WA_RD,WB_ALU,PCR_N,SYNC_N,N,N,N,N,N),
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LHU-> List(Y, N,BR_N, REN_N,REN_Y,A2_ITYPE,DW_XPR,FN_ADD, M_Y,M_XRD, MT_HU,N,MUL_X, N,DIV_X, WEN_Y,WA_RD,WB_ALU,PCR_N,SYNC_N,N,N,N,N,N),
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LWU-> List(xpr64,N,BR_N, REN_N,REN_Y,A2_ITYPE,DW_XPR,FN_ADD, M_Y,M_XRD, MT_WU,N,MUL_X, N,DIV_X, WEN_Y,WA_RD,WB_ALU,PCR_N,SYNC_N,N,N,N,N,N),
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SB-> List(Y, N,BR_N, REN_Y,REN_Y,A2_BTYPE,DW_XPR,FN_ADD, M_Y,M_XWR, MT_B, N,MUL_X, N,DIV_X, WEN_N,WA_X, WB_ALU,PCR_N,SYNC_N,N,N,N,N,N),
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SH-> List(Y, N,BR_N, REN_Y,REN_Y,A2_BTYPE,DW_XPR,FN_ADD, M_Y,M_XWR, MT_H, N,MUL_X, N,DIV_X, WEN_N,WA_X, WB_ALU,PCR_N,SYNC_N,N,N,N,N,N),
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SW-> List(Y, N,BR_N, REN_Y,REN_Y,A2_BTYPE,DW_XPR,FN_ADD, M_Y,M_XWR, MT_W, N,MUL_X, N,DIV_X, WEN_N,WA_X, WB_ALU,PCR_N,SYNC_N,N,N,N,N,N),
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SD-> List(xpr64,N,BR_N, REN_Y,REN_Y,A2_BTYPE,DW_XPR,FN_ADD, M_Y,M_XWR, MT_D, N,MUL_X, N,DIV_X, WEN_N,WA_X, WB_ALU,PCR_N,SYNC_N,N,N,N,N,N),
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AMOADD_W-> List(Y, N,BR_N, REN_Y,REN_Y,A2_ZERO, DW_XPR,FN_ADD, M_Y,M_XA_ADD, MT_W, N,MUL_X, N,DIV_X, WEN_Y,WA_RD,WB_ALU,REN_N,WEN_N,I_X ,SYNC_N,N,N,N,N,N),
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AMOSWAP_W-> List(Y, N,BR_N, REN_Y,REN_Y,A2_ZERO, DW_XPR,FN_ADD, M_Y,M_XA_SWAP,MT_W, N,MUL_X, N,DIV_X, WEN_Y,WA_RD,WB_ALU,REN_N,WEN_N,I_X ,SYNC_N,N,N,N,N,N),
|
||||
AMOAND_W-> List(Y, N,BR_N, REN_Y,REN_Y,A2_ZERO, DW_XPR,FN_ADD, M_Y,M_XA_AND, MT_W, N,MUL_X, N,DIV_X, WEN_Y,WA_RD,WB_ALU,REN_N,WEN_N,I_X ,SYNC_N,N,N,N,N,N),
|
||||
AMOOR_W-> List(Y, N,BR_N, REN_Y,REN_Y,A2_ZERO, DW_XPR,FN_ADD, M_Y,M_XA_OR, MT_W, N,MUL_X, N,DIV_X, WEN_Y,WA_RD,WB_ALU,REN_N,WEN_N,I_X ,SYNC_N,N,N,N,N,N),
|
||||
AMOMIN_W-> List(Y, N,BR_N, REN_Y,REN_Y,A2_ZERO, DW_XPR,FN_ADD, M_Y,M_XA_MIN, MT_W, N,MUL_X, N,DIV_X, WEN_Y,WA_RD,WB_ALU,REN_N,WEN_N,I_X ,SYNC_N,N,N,N,N,N),
|
||||
AMOMINU_W-> List(Y, N,BR_N, REN_Y,REN_Y,A2_ZERO, DW_XPR,FN_ADD, M_Y,M_XA_MINU,MT_W, N,MUL_X, N,DIV_X, WEN_Y,WA_RD,WB_ALU,REN_N,WEN_N,I_X ,SYNC_N,N,N,N,N,N),
|
||||
AMOMAX_W-> List(Y, N,BR_N, REN_Y,REN_Y,A2_ZERO, DW_XPR,FN_ADD, M_Y,M_XA_MAX, MT_W, N,MUL_X, N,DIV_X, WEN_Y,WA_RD,WB_ALU,REN_N,WEN_N,I_X ,SYNC_N,N,N,N,N,N),
|
||||
AMOMAXU_W-> List(Y, N,BR_N, REN_Y,REN_Y,A2_ZERO, DW_XPR,FN_ADD, M_Y,M_XA_MAXU,MT_W, N,MUL_X, N,DIV_X, WEN_Y,WA_RD,WB_ALU,REN_N,WEN_N,I_X ,SYNC_N,N,N,N,N,N),
|
||||
AMOADD_D-> List(xpr64,N,BR_N, REN_Y,REN_Y,A2_ZERO, DW_XPR,FN_ADD, M_Y,M_XA_ADD, MT_D, N,MUL_X, N,DIV_X, WEN_Y,WA_RD,WB_ALU,REN_N,WEN_N,I_X ,SYNC_N,N,N,N,N,N),
|
||||
AMOSWAP_D-> List(xpr64,N,BR_N, REN_Y,REN_Y,A2_ZERO, DW_XPR,FN_ADD, M_Y,M_XA_SWAP,MT_D, N,MUL_X, N,DIV_X, WEN_Y,WA_RD,WB_ALU,REN_N,WEN_N,I_X ,SYNC_N,N,N,N,N,N),
|
||||
AMOAND_D-> List(xpr64,N,BR_N, REN_Y,REN_Y,A2_ZERO, DW_XPR,FN_ADD, M_Y,M_XA_AND, MT_D, N,MUL_X, N,DIV_X, WEN_Y,WA_RD,WB_ALU,REN_N,WEN_N,I_X ,SYNC_N,N,N,N,N,N),
|
||||
AMOOR_D-> List(xpr64,N,BR_N, REN_Y,REN_Y,A2_ZERO, DW_XPR,FN_ADD, M_Y,M_XA_OR, MT_D, N,MUL_X, N,DIV_X, WEN_Y,WA_RD,WB_ALU,REN_N,WEN_N,I_X ,SYNC_N,N,N,N,N,N),
|
||||
AMOMIN_D-> List(xpr64,N,BR_N, REN_Y,REN_Y,A2_ZERO, DW_XPR,FN_ADD, M_Y,M_XA_MIN, MT_D, N,MUL_X, N,DIV_X, WEN_Y,WA_RD,WB_ALU,REN_N,WEN_N,I_X ,SYNC_N,N,N,N,N,N),
|
||||
AMOMINU_D-> List(xpr64,N,BR_N, REN_Y,REN_Y,A2_ZERO, DW_XPR,FN_ADD, M_Y,M_XA_MINU,MT_D, N,MUL_X, N,DIV_X, WEN_Y,WA_RD,WB_ALU,REN_N,WEN_N,I_X ,SYNC_N,N,N,N,N,N),
|
||||
AMOMAX_D-> List(xpr64,N,BR_N, REN_Y,REN_Y,A2_ZERO, DW_XPR,FN_ADD, M_Y,M_XA_MAX, MT_D, N,MUL_X, N,DIV_X, WEN_Y,WA_RD,WB_ALU,REN_N,WEN_N,I_X ,SYNC_N,N,N,N,N,N),
|
||||
AMOMAXU_D-> List(xpr64,N,BR_N, REN_Y,REN_Y,A2_ZERO, DW_XPR,FN_ADD, M_Y,M_XA_MAXU,MT_D, N,MUL_X, N,DIV_X, WEN_Y,WA_RD,WB_ALU,REN_N,WEN_N,I_X ,SYNC_N,N,N,N,N,N),
|
||||
AMOADD_W-> List(Y, N,BR_N, REN_Y,REN_Y,A2_ZERO, DW_XPR,FN_ADD, M_Y,M_XA_ADD, MT_W, N,MUL_X, N,DIV_X, WEN_Y,WA_RD,WB_ALU,PCR_N,SYNC_N,N,N,N,N,N),
|
||||
AMOSWAP_W-> List(Y, N,BR_N, REN_Y,REN_Y,A2_ZERO, DW_XPR,FN_ADD, M_Y,M_XA_SWAP,MT_W, N,MUL_X, N,DIV_X, WEN_Y,WA_RD,WB_ALU,PCR_N,SYNC_N,N,N,N,N,N),
|
||||
AMOAND_W-> List(Y, N,BR_N, REN_Y,REN_Y,A2_ZERO, DW_XPR,FN_ADD, M_Y,M_XA_AND, MT_W, N,MUL_X, N,DIV_X, WEN_Y,WA_RD,WB_ALU,PCR_N,SYNC_N,N,N,N,N,N),
|
||||
AMOOR_W-> List(Y, N,BR_N, REN_Y,REN_Y,A2_ZERO, DW_XPR,FN_ADD, M_Y,M_XA_OR, MT_W, N,MUL_X, N,DIV_X, WEN_Y,WA_RD,WB_ALU,PCR_N,SYNC_N,N,N,N,N,N),
|
||||
AMOMIN_W-> List(Y, N,BR_N, REN_Y,REN_Y,A2_ZERO, DW_XPR,FN_ADD, M_Y,M_XA_MIN, MT_W, N,MUL_X, N,DIV_X, WEN_Y,WA_RD,WB_ALU,PCR_N,SYNC_N,N,N,N,N,N),
|
||||
AMOMINU_W-> List(Y, N,BR_N, REN_Y,REN_Y,A2_ZERO, DW_XPR,FN_ADD, M_Y,M_XA_MINU,MT_W, N,MUL_X, N,DIV_X, WEN_Y,WA_RD,WB_ALU,PCR_N,SYNC_N,N,N,N,N,N),
|
||||
AMOMAX_W-> List(Y, N,BR_N, REN_Y,REN_Y,A2_ZERO, DW_XPR,FN_ADD, M_Y,M_XA_MAX, MT_W, N,MUL_X, N,DIV_X, WEN_Y,WA_RD,WB_ALU,PCR_N,SYNC_N,N,N,N,N,N),
|
||||
AMOMAXU_W-> List(Y, N,BR_N, REN_Y,REN_Y,A2_ZERO, DW_XPR,FN_ADD, M_Y,M_XA_MAXU,MT_W, N,MUL_X, N,DIV_X, WEN_Y,WA_RD,WB_ALU,PCR_N,SYNC_N,N,N,N,N,N),
|
||||
AMOADD_D-> List(xpr64,N,BR_N, REN_Y,REN_Y,A2_ZERO, DW_XPR,FN_ADD, M_Y,M_XA_ADD, MT_D, N,MUL_X, N,DIV_X, WEN_Y,WA_RD,WB_ALU,PCR_N,SYNC_N,N,N,N,N,N),
|
||||
AMOSWAP_D-> List(xpr64,N,BR_N, REN_Y,REN_Y,A2_ZERO, DW_XPR,FN_ADD, M_Y,M_XA_SWAP,MT_D, N,MUL_X, N,DIV_X, WEN_Y,WA_RD,WB_ALU,PCR_N,SYNC_N,N,N,N,N,N),
|
||||
AMOAND_D-> List(xpr64,N,BR_N, REN_Y,REN_Y,A2_ZERO, DW_XPR,FN_ADD, M_Y,M_XA_AND, MT_D, N,MUL_X, N,DIV_X, WEN_Y,WA_RD,WB_ALU,PCR_N,SYNC_N,N,N,N,N,N),
|
||||
AMOOR_D-> List(xpr64,N,BR_N, REN_Y,REN_Y,A2_ZERO, DW_XPR,FN_ADD, M_Y,M_XA_OR, MT_D, N,MUL_X, N,DIV_X, WEN_Y,WA_RD,WB_ALU,PCR_N,SYNC_N,N,N,N,N,N),
|
||||
AMOMIN_D-> List(xpr64,N,BR_N, REN_Y,REN_Y,A2_ZERO, DW_XPR,FN_ADD, M_Y,M_XA_MIN, MT_D, N,MUL_X, N,DIV_X, WEN_Y,WA_RD,WB_ALU,PCR_N,SYNC_N,N,N,N,N,N),
|
||||
AMOMINU_D-> List(xpr64,N,BR_N, REN_Y,REN_Y,A2_ZERO, DW_XPR,FN_ADD, M_Y,M_XA_MINU,MT_D, N,MUL_X, N,DIV_X, WEN_Y,WA_RD,WB_ALU,PCR_N,SYNC_N,N,N,N,N,N),
|
||||
AMOMAX_D-> List(xpr64,N,BR_N, REN_Y,REN_Y,A2_ZERO, DW_XPR,FN_ADD, M_Y,M_XA_MAX, MT_D, N,MUL_X, N,DIV_X, WEN_Y,WA_RD,WB_ALU,PCR_N,SYNC_N,N,N,N,N,N),
|
||||
AMOMAXU_D-> List(xpr64,N,BR_N, REN_Y,REN_Y,A2_ZERO, DW_XPR,FN_ADD, M_Y,M_XA_MAXU,MT_D, N,MUL_X, N,DIV_X, WEN_Y,WA_RD,WB_ALU,PCR_N,SYNC_N,N,N,N,N,N),
|
||||
|
||||
LUI-> List(Y, N,BR_N, REN_N,REN_N,A2_LTYPE,DW_XPR,FN_OP2, M_N,M_X, MT_X, N,MUL_X, N,DIV_X, WEN_Y,WA_RD,WB_ALU,REN_N,WEN_N,I_X ,SYNC_N,N,N,N,N,N),
|
||||
ADDI-> List(Y, N,BR_N, REN_N,REN_Y,A2_ITYPE,DW_XPR,FN_ADD, M_N,M_X, MT_X, N,MUL_X, N,DIV_X, WEN_Y,WA_RD,WB_ALU,REN_N,WEN_N,I_X ,SYNC_N,N,N,N,N,N),
|
||||
SLTI -> List(Y, N,BR_N, REN_N,REN_Y,A2_ITYPE,DW_XPR,FN_SLT, M_N,M_X, MT_X, N,MUL_X, N,DIV_X, WEN_Y,WA_RD,WB_ALU,REN_N,WEN_N,I_X ,SYNC_N,N,N,N,N,N),
|
||||
SLTIU-> List(Y, N,BR_N, REN_N,REN_Y,A2_ITYPE,DW_XPR,FN_SLTU,M_N,M_X, MT_X, N,MUL_X, N,DIV_X, WEN_Y,WA_RD,WB_ALU,REN_N,WEN_N,I_X ,SYNC_N,N,N,N,N,N),
|
||||
ANDI-> List(Y, N,BR_N, REN_N,REN_Y,A2_ITYPE,DW_XPR,FN_AND, M_N,M_X, MT_X, N,MUL_X, N,DIV_X, WEN_Y,WA_RD,WB_ALU,REN_N,WEN_N,I_X ,SYNC_N,N,N,N,N,N),
|
||||
ORI-> List(Y, N,BR_N, REN_N,REN_Y,A2_ITYPE,DW_XPR,FN_OR, M_N,M_X, MT_X, N,MUL_X, N,DIV_X, WEN_Y,WA_RD,WB_ALU,REN_N,WEN_N,I_X ,SYNC_N,N,N,N,N,N),
|
||||
XORI-> List(Y, N,BR_N, REN_N,REN_Y,A2_ITYPE,DW_XPR,FN_XOR, M_N,M_X, MT_X, N,MUL_X, N,DIV_X, WEN_Y,WA_RD,WB_ALU,REN_N,WEN_N,I_X ,SYNC_N,N,N,N,N,N),
|
||||
SLLI-> List(Y, N,BR_N, REN_N,REN_Y,A2_ITYPE,DW_XPR,FN_SL, M_N,M_X, MT_X, N,MUL_X, N,DIV_X, WEN_Y,WA_RD,WB_ALU,REN_N,WEN_N,I_X ,SYNC_N,N,N,N,N,N),
|
||||
SRLI-> List(Y, N,BR_N, REN_N,REN_Y,A2_ITYPE,DW_XPR,FN_SR, M_N,M_X, MT_X, N,MUL_X, N,DIV_X, WEN_Y,WA_RD,WB_ALU,REN_N,WEN_N,I_X ,SYNC_N,N,N,N,N,N),
|
||||
SRAI-> List(Y, N,BR_N, REN_N,REN_Y,A2_ITYPE,DW_XPR,FN_SRA, M_N,M_X, MT_X, N,MUL_X, N,DIV_X, WEN_Y,WA_RD,WB_ALU,REN_N,WEN_N,I_X ,SYNC_N,N,N,N,N,N),
|
||||
ADD-> List(Y, N,BR_N, REN_Y,REN_Y,A2_RTYPE,DW_XPR,FN_ADD, M_N,M_X, MT_X, N,MUL_X, N,DIV_X, WEN_Y,WA_RD,WB_ALU,REN_N,WEN_N,I_X ,SYNC_N,N,N,N,N,N),
|
||||
SUB-> List(Y, N,BR_N, REN_Y,REN_Y,A2_RTYPE,DW_XPR,FN_SUB, M_N,M_X, MT_X, N,MUL_X, N,DIV_X, WEN_Y,WA_RD,WB_ALU,REN_N,WEN_N,I_X ,SYNC_N,N,N,N,N,N),
|
||||
SLT-> List(Y, N,BR_N, REN_Y,REN_Y,A2_RTYPE,DW_XPR,FN_SLT, M_N,M_X, MT_X, N,MUL_X, N,DIV_X, WEN_Y,WA_RD,WB_ALU,REN_N,WEN_N,I_X ,SYNC_N,N,N,N,N,N),
|
||||
SLTU-> List(Y, N,BR_N, REN_Y,REN_Y,A2_RTYPE,DW_XPR,FN_SLTU,M_N,M_X, MT_X, N,MUL_X, N,DIV_X, WEN_Y,WA_RD,WB_ALU,REN_N,WEN_N,I_X ,SYNC_N,N,N,N,N,N),
|
||||
riscvAND-> List(Y, N,BR_N, REN_Y,REN_Y,A2_RTYPE,DW_XPR,FN_AND, M_N,M_X, MT_X, N,MUL_X, N,DIV_X, WEN_Y,WA_RD,WB_ALU,REN_N,WEN_N,I_X ,SYNC_N,N,N,N,N,N),
|
||||
riscvOR-> List(Y, N,BR_N, REN_Y,REN_Y,A2_RTYPE,DW_XPR,FN_OR, M_N,M_X, MT_X, N,MUL_X, N,DIV_X, WEN_Y,WA_RD,WB_ALU,REN_N,WEN_N,I_X ,SYNC_N,N,N,N,N,N),
|
||||
riscvXOR-> List(Y, N,BR_N, REN_Y,REN_Y,A2_RTYPE,DW_XPR,FN_XOR, M_N,M_X, MT_X, N,MUL_X, N,DIV_X, WEN_Y,WA_RD,WB_ALU,REN_N,WEN_N,I_X ,SYNC_N,N,N,N,N,N),
|
||||
SLL-> List(Y, N,BR_N, REN_Y,REN_Y,A2_RTYPE,DW_XPR,FN_SL, M_N,M_X, MT_X, N,MUL_X, N,DIV_X, WEN_Y,WA_RD,WB_ALU,REN_N,WEN_N,I_X ,SYNC_N,N,N,N,N,N),
|
||||
SRL-> List(Y, N,BR_N, REN_Y,REN_Y,A2_RTYPE,DW_XPR,FN_SR, M_N,M_X, MT_X, N,MUL_X, N,DIV_X, WEN_Y,WA_RD,WB_ALU,REN_N,WEN_N,I_X ,SYNC_N,N,N,N,N,N),
|
||||
SRA-> List(Y, N,BR_N, REN_Y,REN_Y,A2_RTYPE,DW_XPR,FN_SRA, M_N,M_X, MT_X, N,MUL_X, N,DIV_X, WEN_Y,WA_RD,WB_ALU,REN_N,WEN_N,I_X ,SYNC_N,N,N,N,N,N),
|
||||
LUI-> List(Y, N,BR_N, REN_N,REN_N,A2_LTYPE,DW_XPR,FN_OP2, M_N,M_X, MT_X, N,MUL_X, N,DIV_X, WEN_Y,WA_RD,WB_ALU,PCR_N,SYNC_N,N,N,N,N,N),
|
||||
ADDI-> List(Y, N,BR_N, REN_N,REN_Y,A2_ITYPE,DW_XPR,FN_ADD, M_N,M_X, MT_X, N,MUL_X, N,DIV_X, WEN_Y,WA_RD,WB_ALU,PCR_N,SYNC_N,N,N,N,N,N),
|
||||
SLTI -> List(Y, N,BR_N, REN_N,REN_Y,A2_ITYPE,DW_XPR,FN_SLT, M_N,M_X, MT_X, N,MUL_X, N,DIV_X, WEN_Y,WA_RD,WB_ALU,PCR_N,SYNC_N,N,N,N,N,N),
|
||||
SLTIU-> List(Y, N,BR_N, REN_N,REN_Y,A2_ITYPE,DW_XPR,FN_SLTU,M_N,M_X, MT_X, N,MUL_X, N,DIV_X, WEN_Y,WA_RD,WB_ALU,PCR_N,SYNC_N,N,N,N,N,N),
|
||||
ANDI-> List(Y, N,BR_N, REN_N,REN_Y,A2_ITYPE,DW_XPR,FN_AND, M_N,M_X, MT_X, N,MUL_X, N,DIV_X, WEN_Y,WA_RD,WB_ALU,PCR_N,SYNC_N,N,N,N,N,N),
|
||||
ORI-> List(Y, N,BR_N, REN_N,REN_Y,A2_ITYPE,DW_XPR,FN_OR, M_N,M_X, MT_X, N,MUL_X, N,DIV_X, WEN_Y,WA_RD,WB_ALU,PCR_N,SYNC_N,N,N,N,N,N),
|
||||
XORI-> List(Y, N,BR_N, REN_N,REN_Y,A2_ITYPE,DW_XPR,FN_XOR, M_N,M_X, MT_X, N,MUL_X, N,DIV_X, WEN_Y,WA_RD,WB_ALU,PCR_N,SYNC_N,N,N,N,N,N),
|
||||
SLLI-> List(Y, N,BR_N, REN_N,REN_Y,A2_ITYPE,DW_XPR,FN_SL, M_N,M_X, MT_X, N,MUL_X, N,DIV_X, WEN_Y,WA_RD,WB_ALU,PCR_N,SYNC_N,N,N,N,N,N),
|
||||
SRLI-> List(Y, N,BR_N, REN_N,REN_Y,A2_ITYPE,DW_XPR,FN_SR, M_N,M_X, MT_X, N,MUL_X, N,DIV_X, WEN_Y,WA_RD,WB_ALU,PCR_N,SYNC_N,N,N,N,N,N),
|
||||
SRAI-> List(Y, N,BR_N, REN_N,REN_Y,A2_ITYPE,DW_XPR,FN_SRA, M_N,M_X, MT_X, N,MUL_X, N,DIV_X, WEN_Y,WA_RD,WB_ALU,PCR_N,SYNC_N,N,N,N,N,N),
|
||||
ADD-> List(Y, N,BR_N, REN_Y,REN_Y,A2_RTYPE,DW_XPR,FN_ADD, M_N,M_X, MT_X, N,MUL_X, N,DIV_X, WEN_Y,WA_RD,WB_ALU,PCR_N,SYNC_N,N,N,N,N,N),
|
||||
SUB-> List(Y, N,BR_N, REN_Y,REN_Y,A2_RTYPE,DW_XPR,FN_SUB, M_N,M_X, MT_X, N,MUL_X, N,DIV_X, WEN_Y,WA_RD,WB_ALU,PCR_N,SYNC_N,N,N,N,N,N),
|
||||
SLT-> List(Y, N,BR_N, REN_Y,REN_Y,A2_RTYPE,DW_XPR,FN_SLT, M_N,M_X, MT_X, N,MUL_X, N,DIV_X, WEN_Y,WA_RD,WB_ALU,PCR_N,SYNC_N,N,N,N,N,N),
|
||||
SLTU-> List(Y, N,BR_N, REN_Y,REN_Y,A2_RTYPE,DW_XPR,FN_SLTU,M_N,M_X, MT_X, N,MUL_X, N,DIV_X, WEN_Y,WA_RD,WB_ALU,PCR_N,SYNC_N,N,N,N,N,N),
|
||||
riscvAND-> List(Y, N,BR_N, REN_Y,REN_Y,A2_RTYPE,DW_XPR,FN_AND, M_N,M_X, MT_X, N,MUL_X, N,DIV_X, WEN_Y,WA_RD,WB_ALU,PCR_N,SYNC_N,N,N,N,N,N),
|
||||
riscvOR-> List(Y, N,BR_N, REN_Y,REN_Y,A2_RTYPE,DW_XPR,FN_OR, M_N,M_X, MT_X, N,MUL_X, N,DIV_X, WEN_Y,WA_RD,WB_ALU,PCR_N,SYNC_N,N,N,N,N,N),
|
||||
riscvXOR-> List(Y, N,BR_N, REN_Y,REN_Y,A2_RTYPE,DW_XPR,FN_XOR, M_N,M_X, MT_X, N,MUL_X, N,DIV_X, WEN_Y,WA_RD,WB_ALU,PCR_N,SYNC_N,N,N,N,N,N),
|
||||
SLL-> List(Y, N,BR_N, REN_Y,REN_Y,A2_RTYPE,DW_XPR,FN_SL, M_N,M_X, MT_X, N,MUL_X, N,DIV_X, WEN_Y,WA_RD,WB_ALU,PCR_N,SYNC_N,N,N,N,N,N),
|
||||
SRL-> List(Y, N,BR_N, REN_Y,REN_Y,A2_RTYPE,DW_XPR,FN_SR, M_N,M_X, MT_X, N,MUL_X, N,DIV_X, WEN_Y,WA_RD,WB_ALU,PCR_N,SYNC_N,N,N,N,N,N),
|
||||
SRA-> List(Y, N,BR_N, REN_Y,REN_Y,A2_RTYPE,DW_XPR,FN_SRA, M_N,M_X, MT_X, N,MUL_X, N,DIV_X, WEN_Y,WA_RD,WB_ALU,PCR_N,SYNC_N,N,N,N,N,N),
|
||||
|
||||
ADDIW-> List(xpr64,N,BR_N, REN_N,REN_Y,A2_ITYPE,DW_32,FN_ADD, M_N,M_X, MT_X, N,MUL_X, N,DIV_X, WEN_Y,WA_RD,WB_ALU,REN_N,WEN_N,I_X ,SYNC_N,N,N,N,N,N),
|
||||
SLLIW-> List(xpr64,N,BR_N, REN_N,REN_Y,A2_ITYPE,DW_32,FN_SL, M_N,M_X, MT_X, N,MUL_X, N,DIV_X, WEN_Y,WA_RD,WB_ALU,REN_N,WEN_N,I_X ,SYNC_N,N,N,N,N,N),
|
||||
SRLIW-> List(xpr64,N,BR_N, REN_N,REN_Y,A2_ITYPE,DW_32,FN_SR, M_N,M_X, MT_X, N,MUL_X, N,DIV_X, WEN_Y,WA_RD,WB_ALU,REN_N,WEN_N,I_X ,SYNC_N,N,N,N,N,N),
|
||||
SRAIW-> List(xpr64,N,BR_N, REN_N,REN_Y,A2_ITYPE,DW_32,FN_SRA, M_N,M_X, MT_X, N,MUL_X, N,DIV_X, WEN_Y,WA_RD,WB_ALU,REN_N,WEN_N,I_X ,SYNC_N,N,N,N,N,N),
|
||||
ADDW-> List(xpr64,N,BR_N, REN_Y,REN_Y,A2_RTYPE,DW_32,FN_ADD, M_N,M_X, MT_X, N,MUL_X, N,DIV_X, WEN_Y,WA_RD,WB_ALU,REN_N,WEN_N,I_X ,SYNC_N,N,N,N,N,N),
|
||||
SUBW-> List(xpr64,N,BR_N, REN_Y,REN_Y,A2_RTYPE,DW_32,FN_SUB, M_N,M_X, MT_X, N,MUL_X, N,DIV_X, WEN_Y,WA_RD,WB_ALU,REN_N,WEN_N,I_X ,SYNC_N,N,N,N,N,N),
|
||||
SLLW-> List(xpr64,N,BR_N, REN_Y,REN_Y,A2_RTYPE,DW_32,FN_SL, M_N,M_X, MT_X, N,MUL_X, N,DIV_X, WEN_Y,WA_RD,WB_ALU,REN_N,WEN_N,I_X ,SYNC_N,N,N,N,N,N),
|
||||
SRLW-> List(xpr64,N,BR_N, REN_Y,REN_Y,A2_RTYPE,DW_32,FN_SR, M_N,M_X, MT_X, N,MUL_X, N,DIV_X, WEN_Y,WA_RD,WB_ALU,REN_N,WEN_N,I_X ,SYNC_N,N,N,N,N,N),
|
||||
SRAW-> List(xpr64,N,BR_N, REN_Y,REN_Y,A2_RTYPE,DW_32,FN_SRA, M_N,M_X, MT_X, N,MUL_X, N,DIV_X, WEN_Y,WA_RD,WB_ALU,REN_N,WEN_N,I_X ,SYNC_N,N,N,N,N,N),
|
||||
ADDIW-> List(xpr64,N,BR_N, REN_N,REN_Y,A2_ITYPE,DW_32,FN_ADD, M_N,M_X, MT_X, N,MUL_X, N,DIV_X, WEN_Y,WA_RD,WB_ALU,PCR_N,SYNC_N,N,N,N,N,N),
|
||||
SLLIW-> List(xpr64,N,BR_N, REN_N,REN_Y,A2_ITYPE,DW_32,FN_SL, M_N,M_X, MT_X, N,MUL_X, N,DIV_X, WEN_Y,WA_RD,WB_ALU,PCR_N,SYNC_N,N,N,N,N,N),
|
||||
SRLIW-> List(xpr64,N,BR_N, REN_N,REN_Y,A2_ITYPE,DW_32,FN_SR, M_N,M_X, MT_X, N,MUL_X, N,DIV_X, WEN_Y,WA_RD,WB_ALU,PCR_N,SYNC_N,N,N,N,N,N),
|
||||
SRAIW-> List(xpr64,N,BR_N, REN_N,REN_Y,A2_ITYPE,DW_32,FN_SRA, M_N,M_X, MT_X, N,MUL_X, N,DIV_X, WEN_Y,WA_RD,WB_ALU,PCR_N,SYNC_N,N,N,N,N,N),
|
||||
ADDW-> List(xpr64,N,BR_N, REN_Y,REN_Y,A2_RTYPE,DW_32,FN_ADD, M_N,M_X, MT_X, N,MUL_X, N,DIV_X, WEN_Y,WA_RD,WB_ALU,PCR_N,SYNC_N,N,N,N,N,N),
|
||||
SUBW-> List(xpr64,N,BR_N, REN_Y,REN_Y,A2_RTYPE,DW_32,FN_SUB, M_N,M_X, MT_X, N,MUL_X, N,DIV_X, WEN_Y,WA_RD,WB_ALU,PCR_N,SYNC_N,N,N,N,N,N),
|
||||
SLLW-> List(xpr64,N,BR_N, REN_Y,REN_Y,A2_RTYPE,DW_32,FN_SL, M_N,M_X, MT_X, N,MUL_X, N,DIV_X, WEN_Y,WA_RD,WB_ALU,PCR_N,SYNC_N,N,N,N,N,N),
|
||||
SRLW-> List(xpr64,N,BR_N, REN_Y,REN_Y,A2_RTYPE,DW_32,FN_SR, M_N,M_X, MT_X, N,MUL_X, N,DIV_X, WEN_Y,WA_RD,WB_ALU,PCR_N,SYNC_N,N,N,N,N,N),
|
||||
SRAW-> List(xpr64,N,BR_N, REN_Y,REN_Y,A2_RTYPE,DW_32,FN_SRA, M_N,M_X, MT_X, N,MUL_X, N,DIV_X, WEN_Y,WA_RD,WB_ALU,PCR_N,SYNC_N,N,N,N,N,N),
|
||||
|
||||
MUL-> List(Y, N,BR_N, REN_Y,REN_Y,A2_X, DW_XPR,FN_X, M_N,M_X, MT_X, Y,MUL_LO, N,DIV_X, WEN_Y,WA_RD,WB_X, REN_N,WEN_N,I_X ,SYNC_N,N,N,N,N,N),
|
||||
MULH-> List(Y, N,BR_N, REN_Y,REN_Y,A2_X, DW_XPR,FN_X, M_N,M_X, MT_X, Y,MUL_H, N,DIV_X, WEN_Y,WA_RD,WB_X, REN_N,WEN_N,I_X ,SYNC_N,N,N,N,N,N),
|
||||
MULHU-> List(Y, N,BR_N, REN_Y,REN_Y,A2_X, DW_XPR,FN_X, M_N,M_X, MT_X, Y,MUL_HU, N,DIV_X, WEN_Y,WA_RD,WB_X, REN_N,WEN_N,I_X ,SYNC_N,N,N,N,N,N),
|
||||
MULHSU-> List(Y, N,BR_N, REN_Y,REN_Y,A2_X, DW_XPR,FN_X, M_N,M_X, MT_X, Y,MUL_HSU,N,DIV_X, WEN_Y,WA_RD,WB_X, REN_N,WEN_N,I_X ,SYNC_N,N,N,N,N,N),
|
||||
MULW-> List(xpr64,N,BR_N, REN_Y,REN_Y,A2_X, DW_32, FN_X, M_N,M_X, MT_X, Y,MUL_LO, N,DIV_X, WEN_Y,WA_RD,WB_X, REN_N,WEN_N,I_X ,SYNC_N,N,N,N,N,N),
|
||||
MUL-> List(Y, N,BR_N, REN_Y,REN_Y,A2_X, DW_XPR,FN_X, M_N,M_X, MT_X, Y,MUL_LO, N,DIV_X, WEN_Y,WA_RD,WB_X, PCR_N,SYNC_N,N,N,N,N,N),
|
||||
MULH-> List(Y, N,BR_N, REN_Y,REN_Y,A2_X, DW_XPR,FN_X, M_N,M_X, MT_X, Y,MUL_H, N,DIV_X, WEN_Y,WA_RD,WB_X, PCR_N,SYNC_N,N,N,N,N,N),
|
||||
MULHU-> List(Y, N,BR_N, REN_Y,REN_Y,A2_X, DW_XPR,FN_X, M_N,M_X, MT_X, Y,MUL_HU, N,DIV_X, WEN_Y,WA_RD,WB_X, PCR_N,SYNC_N,N,N,N,N,N),
|
||||
MULHSU-> List(Y, N,BR_N, REN_Y,REN_Y,A2_X, DW_XPR,FN_X, M_N,M_X, MT_X, Y,MUL_HSU,N,DIV_X, WEN_Y,WA_RD,WB_X, PCR_N,SYNC_N,N,N,N,N,N),
|
||||
MULW-> List(xpr64,N,BR_N, REN_Y,REN_Y,A2_X, DW_32, FN_X, M_N,M_X, MT_X, Y,MUL_LO, N,DIV_X, WEN_Y,WA_RD,WB_X, PCR_N,SYNC_N,N,N,N,N,N),
|
||||
|
||||
DIV-> List(Y, N,BR_N, REN_Y,REN_Y,A2_X, DW_XPR,FN_X, M_N,M_X, MT_X, N,MUL_X, Y,DIV_D, WEN_Y,WA_RD,WB_X, REN_N,WEN_N,I_X ,SYNC_N,N,N,N,N,N),
|
||||
DIVU-> List(Y, N,BR_N, REN_Y,REN_Y,A2_X, DW_XPR,FN_X, M_N,M_X, MT_X, N,MUL_X, Y,DIV_DU,WEN_Y,WA_RD,WB_X, REN_N,WEN_N,I_X ,SYNC_N,N,N,N,N,N),
|
||||
REM-> List(Y, N,BR_N, REN_Y,REN_Y,A2_X, DW_XPR,FN_X, M_N,M_X, MT_X, N,MUL_X, Y,DIV_R, WEN_Y,WA_RD,WB_X, REN_N,WEN_N,I_X ,SYNC_N,N,N,N,N,N),
|
||||
REMU-> List(Y, N,BR_N, REN_Y,REN_Y,A2_X, DW_XPR,FN_X, M_N,M_X, MT_X, N,MUL_X, Y,DIV_RU,WEN_Y,WA_RD,WB_X, REN_N,WEN_N,I_X ,SYNC_N,N,N,N,N,N),
|
||||
DIVW-> List(xpr64,N,BR_N, REN_Y,REN_Y,A2_X, DW_32, FN_X, M_N,M_X, MT_X, N,MUL_X, Y,DIV_D, WEN_Y,WA_RD,WB_X, REN_N,WEN_N,I_X ,SYNC_N,N,N,N,N,N),
|
||||
DIVUW-> List(xpr64,N,BR_N, REN_Y,REN_Y,A2_X, DW_32, FN_X, M_N,M_X, MT_X, N,MUL_X, Y,DIV_DU,WEN_Y,WA_RD,WB_X, REN_N,WEN_N,I_X ,SYNC_N,N,N,N,N,N),
|
||||
REMW-> List(xpr64,N,BR_N, REN_Y,REN_Y,A2_X, DW_32, FN_X, M_N,M_X, MT_X, N,MUL_X, Y,DIV_R, WEN_Y,WA_RD,WB_X, REN_N,WEN_N,I_X ,SYNC_N,N,N,N,N,N),
|
||||
REMUW-> List(xpr64,N,BR_N, REN_Y,REN_Y,A2_X, DW_32, FN_X, M_N,M_X, MT_X, N,MUL_X, Y,DIV_RU,WEN_Y,WA_RD,WB_X, REN_N,WEN_N,I_X ,SYNC_N,N,N,N,N,N),
|
||||
DIV-> List(Y, N,BR_N, REN_Y,REN_Y,A2_X, DW_XPR,FN_X, M_N,M_X, MT_X, N,MUL_X, Y,DIV_D, WEN_Y,WA_RD,WB_X, PCR_N,SYNC_N,N,N,N,N,N),
|
||||
DIVU-> List(Y, N,BR_N, REN_Y,REN_Y,A2_X, DW_XPR,FN_X, M_N,M_X, MT_X, N,MUL_X, Y,DIV_DU,WEN_Y,WA_RD,WB_X, PCR_N,SYNC_N,N,N,N,N,N),
|
||||
REM-> List(Y, N,BR_N, REN_Y,REN_Y,A2_X, DW_XPR,FN_X, M_N,M_X, MT_X, N,MUL_X, Y,DIV_R, WEN_Y,WA_RD,WB_X, PCR_N,SYNC_N,N,N,N,N,N),
|
||||
REMU-> List(Y, N,BR_N, REN_Y,REN_Y,A2_X, DW_XPR,FN_X, M_N,M_X, MT_X, N,MUL_X, Y,DIV_RU,WEN_Y,WA_RD,WB_X, PCR_N,SYNC_N,N,N,N,N,N),
|
||||
DIVW-> List(xpr64,N,BR_N, REN_Y,REN_Y,A2_X, DW_32, FN_X, M_N,M_X, MT_X, N,MUL_X, Y,DIV_D, WEN_Y,WA_RD,WB_X, PCR_N,SYNC_N,N,N,N,N,N),
|
||||
DIVUW-> List(xpr64,N,BR_N, REN_Y,REN_Y,A2_X, DW_32, FN_X, M_N,M_X, MT_X, N,MUL_X, Y,DIV_DU,WEN_Y,WA_RD,WB_X, PCR_N,SYNC_N,N,N,N,N,N),
|
||||
REMW-> List(xpr64,N,BR_N, REN_Y,REN_Y,A2_X, DW_32, FN_X, M_N,M_X, MT_X, N,MUL_X, Y,DIV_R, WEN_Y,WA_RD,WB_X, PCR_N,SYNC_N,N,N,N,N,N),
|
||||
REMUW-> List(xpr64,N,BR_N, REN_Y,REN_Y,A2_X, DW_32, FN_X, M_N,M_X, MT_X, N,MUL_X, Y,DIV_RU,WEN_Y,WA_RD,WB_X, PCR_N,SYNC_N,N,N,N,N,N),
|
||||
|
||||
SYSCALL-> List(Y, N,BR_N, REN_N,REN_N,A2_X, DW_X, FN_X, M_N,M_X, MT_X, N,MUL_X, N,DIV_X, WEN_N,WA_X, WB_X, REN_N,WEN_N,I_X ,SYNC_N,N,N,Y,N,N),
|
||||
EI-> List(Y, N,BR_N, REN_N,REN_N,A2_X, DW_X, FN_X, M_N,M_X, MT_X, N,MUL_X, N,DIV_X, WEN_N,WA_X, WB_X, REN_N,WEN_N,I_EI,SYNC_N,N,N,N,Y,Y),
|
||||
DI-> List(Y, N,BR_N, REN_N,REN_N,A2_X, DW_X, FN_X, M_N,M_X, MT_X, N,MUL_X, N,DIV_X, WEN_N,WA_X, WB_X, REN_N,WEN_N,I_DI,SYNC_N,N,N,N,Y,Y),
|
||||
ERET-> List(Y, N,BR_N, REN_N,REN_N,A2_X, DW_X, FN_X, M_N,M_X, MT_X, N,MUL_X, N,DIV_X, WEN_N,WA_X, WB_PCR,REN_N,WEN_N,I_X ,SYNC_N,N,Y,N,Y,N),
|
||||
FENCE-> List(Y, N,BR_N, REN_N,REN_N,A2_X, DW_X, FN_X, M_Y,M_FENCE, MT_X, N,MUL_X, N,DIV_X, WEN_N,WA_X, WB_X, REN_N,WEN_N,I_X ,SYNC_D,N,N,N,N,N),
|
||||
FENCE_I-> List(Y, N,BR_N, REN_N,REN_N,A2_X, DW_X, FN_X, M_Y,M_FLA, MT_X, N,MUL_X, N,DIV_X, WEN_N,WA_X, WB_X, REN_N,WEN_N,I_X ,SYNC_I,N,N,N,N,Y),
|
||||
CFLUSH-> List(Y, N,BR_N, REN_N,REN_N,A2_X, DW_X, FN_X, M_Y,M_FLA, MT_X, N,MUL_X, N,DIV_X, WEN_N,WA_X, WB_X, REN_N,WEN_N,I_X ,SYNC_N,N,N,N,Y,Y),
|
||||
MFPCR-> List(Y, N,BR_N, REN_N,REN_N,A2_X, DW_X, FN_X, M_N,M_X, MT_X, N,MUL_X, N,DIV_X, WEN_Y,WA_RD,WB_PCR,REN_Y,WEN_N,I_X ,SYNC_N,N,N,N,Y,N),
|
||||
MTPCR-> List(Y, N,BR_N, REN_N,REN_Y,A2_ZERO, DW_XPR,FN_ADD, M_N,M_X, MT_X, N,MUL_X, N,DIV_X, WEN_N,WA_X, WB_ALU,REN_N,WEN_Y,I_X ,SYNC_N,N,N,N,Y,Y),
|
||||
RDTIME-> List(Y, N,BR_N, REN_N,REN_N,A2_X, DW_XPR,FN_X, M_N,M_X, MT_X, N,MUL_X, N,DIV_X, WEN_Y,WA_RD,WB_TSC,REN_N,WEN_N,I_X ,SYNC_N,N,N,N,N,N),
|
||||
RDCYCLE-> List(Y, N,BR_N, REN_N,REN_N,A2_X, DW_XPR,FN_X, M_N,M_X, MT_X, N,MUL_X, N,DIV_X, WEN_Y,WA_RD,WB_TSC,REN_N,WEN_N,I_X ,SYNC_N,N,N,N,N,N),
|
||||
RDINSTRET-> List(Y, N,BR_N, REN_N,REN_N,A2_X, DW_XPR,FN_X, M_N,M_X, MT_X, N,MUL_X, N,DIV_X, WEN_Y,WA_RD,WB_IRT,REN_N,WEN_N,I_X ,SYNC_N,N,N,N,N,N))
|
||||
SYSCALL-> List(Y, N,BR_N, REN_N,REN_N,A2_X, DW_X, FN_X, M_N,M_X, MT_X, N,MUL_X, N,DIV_X, WEN_N,WA_X, WB_X, PCR_N,SYNC_N,N,N,Y,N,N),
|
||||
SETPCR-> List(Y, N,BR_N, REN_N,REN_N,A2_ITYPE,DW_XPR,FN_OP2, M_N,M_X, MT_X, N,MUL_X, N,DIV_X, WEN_N,WA_X, WB_ALU,PCR_S,SYNC_N,N,N,N,Y,Y),
|
||||
CLEARPCR-> List(Y, N,BR_N, REN_N,REN_N,A2_ITYPE,DW_XPR,FN_OP2, M_N,M_X, MT_X, N,MUL_X, N,DIV_X, WEN_N,WA_X, WB_ALU,PCR_C,SYNC_N,N,N,N,Y,Y),
|
||||
ERET-> List(Y, N,BR_N, REN_N,REN_N,A2_X, DW_X, FN_X, M_N,M_X, MT_X, N,MUL_X, N,DIV_X, WEN_N,WA_X, WB_X, PCR_N,SYNC_N,N,Y,N,Y,N),
|
||||
FENCE-> List(Y, N,BR_N, REN_N,REN_N,A2_X, DW_X, FN_X, M_Y,M_FENCE, MT_X, N,MUL_X, N,DIV_X, WEN_N,WA_X, WB_X, PCR_N,SYNC_D,N,N,N,N,N),
|
||||
FENCE_I-> List(Y, N,BR_N, REN_N,REN_N,A2_X, DW_X, FN_X, M_Y,M_FLA, MT_X, N,MUL_X, N,DIV_X, WEN_N,WA_X, WB_X, PCR_N,SYNC_I,N,N,N,N,Y),
|
||||
CFLUSH-> List(Y, N,BR_N, REN_N,REN_N,A2_X, DW_X, FN_X, M_Y,M_FLA, MT_X, N,MUL_X, N,DIV_X, WEN_N,WA_X, WB_X, PCR_N,SYNC_N,N,N,N,Y,Y),
|
||||
MFPCR-> List(Y, N,BR_N, REN_N,REN_N,A2_X, DW_X, FN_X, M_N,M_X, MT_X, N,MUL_X, N,DIV_X, WEN_Y,WA_RD,WB_X, PCR_F,SYNC_N,N,N,N,Y,Y),
|
||||
MTPCR-> List(Y, N,BR_N, REN_Y,REN_N,A2_RTYPE,DW_XPR,FN_OP2, M_N,M_X, MT_X, N,MUL_X, N,DIV_X, WEN_Y,WA_RD,WB_ALU,PCR_T,SYNC_N,N,N,N,Y,Y),
|
||||
RDTIME-> List(Y, N,BR_N, REN_N,REN_N,A2_X, DW_XPR,FN_X, M_N,M_X, MT_X, N,MUL_X, N,DIV_X, WEN_Y,WA_RD,WB_TSC,PCR_N,SYNC_N,N,N,N,N,N),
|
||||
RDCYCLE-> List(Y, N,BR_N, REN_N,REN_N,A2_X, DW_XPR,FN_X, M_N,M_X, MT_X, N,MUL_X, N,DIV_X, WEN_Y,WA_RD,WB_TSC,PCR_N,SYNC_N,N,N,N,N,N),
|
||||
RDINSTRET-> List(Y, N,BR_N, REN_N,REN_N,A2_X, DW_XPR,FN_X, M_N,M_X, MT_X, N,MUL_X, N,DIV_X, WEN_Y,WA_RD,WB_IRT,PCR_N,SYNC_N,N,N,N,N,N))
|
||||
|
||||
val fdecode = Array(
|
||||
// vfence
|
||||
// | eret
|
||||
// | | syscall
|
||||
// vec_val mem_val mul_val div_val renpcr | | | privileged
|
||||
// val | brtype renx2 renx1 s_alu2 dw alu | mem_cmd mem_type| mul_fn | div_fn wen s_wa s_wb | wenpcr irq sync | | | | replay_next
|
||||
// | | | | | | | | | | | | | | | | | | | | | | | | | | |
|
||||
MFTX_S-> List(FPU_Y,N,BR_N, REN_N,REN_N,A2_X, DW_X, FN_X, M_N,M_X, MT_X, N,MUL_X, N,DIV_X, WEN_Y,WA_X, WB_X, REN_N,WEN_N,I_X ,SYNC_N,N,N,N,N,N),
|
||||
MFTX_D-> List(FPU_Y,N,BR_N, REN_N,REN_N,A2_X, DW_X, FN_X, M_N,M_X, MT_X, N,MUL_X, N,DIV_X, WEN_Y,WA_X, WB_X, REN_N,WEN_N,I_X ,SYNC_N,N,N,N,N,N),
|
||||
FCVT_W_S-> List(FPU_Y,N,BR_N, REN_N,REN_N,A2_X, DW_X, FN_X, M_N,M_X, MT_X, N,MUL_X, N,DIV_X, WEN_Y,WA_X, WB_X, REN_N,WEN_N,I_X ,SYNC_N,N,N,N,N,N),
|
||||
FCVT_W_D-> List(FPU_Y,N,BR_N, REN_N,REN_N,A2_X, DW_X, FN_X, M_N,M_X, MT_X, N,MUL_X, N,DIV_X, WEN_Y,WA_X, WB_X, REN_N,WEN_N,I_X ,SYNC_N,N,N,N,N,N),
|
||||
FCVT_WU_S-> List(FPU_Y,N,BR_N, REN_N,REN_N,A2_X, DW_X, FN_X, M_N,M_X, MT_X, N,MUL_X, N,DIV_X, WEN_Y,WA_X, WB_X, REN_N,WEN_N,I_X ,SYNC_N,N,N,N,N,N),
|
||||
FCVT_WU_D-> List(FPU_Y,N,BR_N, REN_N,REN_N,A2_X, DW_X, FN_X, M_N,M_X, MT_X, N,MUL_X, N,DIV_X, WEN_Y,WA_X, WB_X, REN_N,WEN_N,I_X ,SYNC_N,N,N,N,N,N),
|
||||
FCVT_L_S-> List(FPU_Y,N,BR_N, REN_N,REN_N,A2_X, DW_X, FN_X, M_N,M_X, MT_X, N,MUL_X, N,DIV_X, WEN_Y,WA_X, WB_X, REN_N,WEN_N,I_X ,SYNC_N,N,N,N,N,N),
|
||||
FCVT_L_D-> List(FPU_Y,N,BR_N, REN_N,REN_N,A2_X, DW_X, FN_X, M_N,M_X, MT_X, N,MUL_X, N,DIV_X, WEN_Y,WA_X, WB_X, REN_N,WEN_N,I_X ,SYNC_N,N,N,N,N,N),
|
||||
FCVT_LU_S-> List(FPU_Y,N,BR_N, REN_N,REN_N,A2_X, DW_X, FN_X, M_N,M_X, MT_X, N,MUL_X, N,DIV_X, WEN_Y,WA_X, WB_X, REN_N,WEN_N,I_X ,SYNC_N,N,N,N,N,N),
|
||||
FCVT_LU_D-> List(FPU_Y,N,BR_N, REN_N,REN_N,A2_X, DW_X, FN_X, M_N,M_X, MT_X, N,MUL_X, N,DIV_X, WEN_Y,WA_X, WB_X, REN_N,WEN_N,I_X ,SYNC_N,N,N,N,N,N),
|
||||
FEQ_S-> List(FPU_Y,N,BR_N, REN_N,REN_N,A2_X, DW_X, FN_X, M_N,M_X, MT_X, N,MUL_X, N,DIV_X, WEN_Y,WA_X, WB_X, REN_N,WEN_N,I_X ,SYNC_N,N,N,N,N,N),
|
||||
FEQ_D-> List(FPU_Y,N,BR_N, REN_N,REN_N,A2_X, DW_X, FN_X, M_N,M_X, MT_X, N,MUL_X, N,DIV_X, WEN_Y,WA_X, WB_X, REN_N,WEN_N,I_X ,SYNC_N,N,N,N,N,N),
|
||||
FLT_S-> List(FPU_Y,N,BR_N, REN_N,REN_N,A2_X, DW_X, FN_X, M_N,M_X, MT_X, N,MUL_X, N,DIV_X, WEN_Y,WA_X, WB_X, REN_N,WEN_N,I_X ,SYNC_N,N,N,N,N,N),
|
||||
FLT_D-> List(FPU_Y,N,BR_N, REN_N,REN_N,A2_X, DW_X, FN_X, M_N,M_X, MT_X, N,MUL_X, N,DIV_X, WEN_Y,WA_X, WB_X, REN_N,WEN_N,I_X ,SYNC_N,N,N,N,N,N),
|
||||
FLE_S-> List(FPU_Y,N,BR_N, REN_N,REN_N,A2_X, DW_X, FN_X, M_N,M_X, MT_X, N,MUL_X, N,DIV_X, WEN_Y,WA_X, WB_X, REN_N,WEN_N,I_X ,SYNC_N,N,N,N,N,N),
|
||||
FLE_D-> List(FPU_Y,N,BR_N, REN_N,REN_N,A2_X, DW_X, FN_X, M_N,M_X, MT_X, N,MUL_X, N,DIV_X, WEN_Y,WA_X, WB_X, REN_N,WEN_N,I_X ,SYNC_N,N,N,N,N,N),
|
||||
MXTF_S-> List(FPU_Y,N,BR_N, REN_N,REN_Y,A2_X, DW_X, FN_X, M_N,M_X, MT_X, N,MUL_X, N,DIV_X, WEN_N,WA_X, WB_X, REN_N,WEN_N,I_X ,SYNC_N,N,N,N,N,N),
|
||||
MXTF_D-> List(FPU_Y,N,BR_N, REN_N,REN_Y,A2_X, DW_X, FN_X, M_N,M_X, MT_X, N,MUL_X, N,DIV_X, WEN_N,WA_X, WB_X, REN_N,WEN_N,I_X ,SYNC_N,N,N,N,N,N),
|
||||
FCVT_S_W-> List(FPU_Y,N,BR_N, REN_N,REN_Y,A2_X, DW_X, FN_X, M_N,M_X, MT_X, N,MUL_X, N,DIV_X, WEN_N,WA_X, WB_X, REN_N,WEN_N,I_X ,SYNC_N,N,N,N,N,N),
|
||||
FCVT_D_W-> List(FPU_Y,N,BR_N, REN_N,REN_Y,A2_X, DW_X, FN_X, M_N,M_X, MT_X, N,MUL_X, N,DIV_X, WEN_N,WA_X, WB_X, REN_N,WEN_N,I_X ,SYNC_N,N,N,N,N,N),
|
||||
FCVT_S_WU-> List(FPU_Y,N,BR_N, REN_N,REN_Y,A2_X, DW_X, FN_X, M_N,M_X, MT_X, N,MUL_X, N,DIV_X, WEN_N,WA_X, WB_X, REN_N,WEN_N,I_X ,SYNC_N,N,N,N,N,N),
|
||||
FCVT_D_WU-> List(FPU_Y,N,BR_N, REN_N,REN_Y,A2_X, DW_X, FN_X, M_N,M_X, MT_X, N,MUL_X, N,DIV_X, WEN_N,WA_X, WB_X, REN_N,WEN_N,I_X ,SYNC_N,N,N,N,N,N),
|
||||
FCVT_S_L-> List(FPU_Y,N,BR_N, REN_N,REN_Y,A2_X, DW_X, FN_X, M_N,M_X, MT_X, N,MUL_X, N,DIV_X, WEN_N,WA_X, WB_X, REN_N,WEN_N,I_X ,SYNC_N,N,N,N,N,N),
|
||||
FCVT_D_L-> List(FPU_Y,N,BR_N, REN_N,REN_Y,A2_X, DW_X, FN_X, M_N,M_X, MT_X, N,MUL_X, N,DIV_X, WEN_N,WA_X, WB_X, REN_N,WEN_N,I_X ,SYNC_N,N,N,N,N,N),
|
||||
FCVT_S_LU-> List(FPU_Y,N,BR_N, REN_N,REN_Y,A2_X, DW_X, FN_X, M_N,M_X, MT_X, N,MUL_X, N,DIV_X, WEN_N,WA_X, WB_X, REN_N,WEN_N,I_X ,SYNC_N,N,N,N,N,N),
|
||||
FCVT_D_LU-> List(FPU_Y,N,BR_N, REN_N,REN_Y,A2_X, DW_X, FN_X, M_N,M_X, MT_X, N,MUL_X, N,DIV_X, WEN_N,WA_X, WB_X, REN_N,WEN_N,I_X ,SYNC_N,N,N,N,N,N),
|
||||
MFFSR-> List(FPU_Y,N,BR_N, REN_N,REN_N,A2_X, DW_X, FN_X, M_N,M_X, MT_X, N,MUL_X, N,DIV_X, WEN_Y,WA_X, WB_X, REN_N,WEN_N,I_X ,SYNC_N,N,N,N,N,N),
|
||||
MTFSR-> List(FPU_Y,N,BR_N, REN_N,REN_Y,A2_X, DW_X, FN_X, M_N,M_X, MT_X, N,MUL_X, N,DIV_X, WEN_Y,WA_X, WB_X, REN_N,WEN_N,I_X ,SYNC_N,N,N,N,N,N),
|
||||
FLW-> List(FPU_Y,N,BR_N, REN_N,REN_Y,A2_ITYPE,DW_XPR,FN_ADD, M_Y,M_XRD, MT_W, N,MUL_X, N,DIV_X, WEN_N,WA_X, WB_ALU,REN_N,WEN_N,I_X ,SYNC_N,N,N,N,N,N),
|
||||
FLD-> List(FPU_Y,N,BR_N, REN_N,REN_Y,A2_ITYPE,DW_XPR,FN_ADD, M_Y,M_XRD, MT_D, N,MUL_X, N,DIV_X, WEN_N,WA_X, WB_ALU,REN_N,WEN_N,I_X ,SYNC_N,N,N,N,N,N),
|
||||
FSW-> List(FPU_Y,N,BR_N, REN_N,REN_Y,A2_BTYPE,DW_XPR,FN_ADD, M_Y,M_XWR, MT_W, N,MUL_X, N,DIV_X, WEN_N,WA_X, WB_ALU,REN_N,WEN_N,I_X ,SYNC_N,N,N,N,N,N),
|
||||
FSD-> List(FPU_Y,N,BR_N, REN_N,REN_Y,A2_BTYPE,DW_XPR,FN_ADD, M_Y,M_XWR, MT_D, N,MUL_X, N,DIV_X, WEN_N,WA_X, WB_ALU,REN_N,WEN_N,I_X ,SYNC_N,N,N,N,N,N))
|
||||
// vfence
|
||||
// | eret
|
||||
// | | syscall
|
||||
// vec_val mem_val mul_val div_val pcr | | | privileged
|
||||
// val | brtype renx2 renx1 s_alu2 dw alu | mem_cmd mem_type| mul_fn | div_fn wen s_wa s_wb | sync | | | | replay_next
|
||||
// | | | | | | | | | | | | | | | | | | | | | | | | |
|
||||
MFTX_S-> List(FPU_Y,N,BR_N, REN_N,REN_N,A2_X, DW_X, FN_X, M_N,M_X, MT_X, N,MUL_X, N,DIV_X, WEN_Y,WA_X, WB_X, PCR_N,SYNC_N,N,N,N,N,N),
|
||||
MFTX_D-> List(FPU_Y,N,BR_N, REN_N,REN_N,A2_X, DW_X, FN_X, M_N,M_X, MT_X, N,MUL_X, N,DIV_X, WEN_Y,WA_X, WB_X, PCR_N,SYNC_N,N,N,N,N,N),
|
||||
FCVT_W_S-> List(FPU_Y,N,BR_N, REN_N,REN_N,A2_X, DW_X, FN_X, M_N,M_X, MT_X, N,MUL_X, N,DIV_X, WEN_Y,WA_X, WB_X, PCR_N,SYNC_N,N,N,N,N,N),
|
||||
FCVT_W_D-> List(FPU_Y,N,BR_N, REN_N,REN_N,A2_X, DW_X, FN_X, M_N,M_X, MT_X, N,MUL_X, N,DIV_X, WEN_Y,WA_X, WB_X, PCR_N,SYNC_N,N,N,N,N,N),
|
||||
FCVT_WU_S-> List(FPU_Y,N,BR_N, REN_N,REN_N,A2_X, DW_X, FN_X, M_N,M_X, MT_X, N,MUL_X, N,DIV_X, WEN_Y,WA_X, WB_X, PCR_N,SYNC_N,N,N,N,N,N),
|
||||
FCVT_WU_D-> List(FPU_Y,N,BR_N, REN_N,REN_N,A2_X, DW_X, FN_X, M_N,M_X, MT_X, N,MUL_X, N,DIV_X, WEN_Y,WA_X, WB_X, PCR_N,SYNC_N,N,N,N,N,N),
|
||||
FCVT_L_S-> List(FPU_Y,N,BR_N, REN_N,REN_N,A2_X, DW_X, FN_X, M_N,M_X, MT_X, N,MUL_X, N,DIV_X, WEN_Y,WA_X, WB_X, PCR_N,SYNC_N,N,N,N,N,N),
|
||||
FCVT_L_D-> List(FPU_Y,N,BR_N, REN_N,REN_N,A2_X, DW_X, FN_X, M_N,M_X, MT_X, N,MUL_X, N,DIV_X, WEN_Y,WA_X, WB_X, PCR_N,SYNC_N,N,N,N,N,N),
|
||||
FCVT_LU_S-> List(FPU_Y,N,BR_N, REN_N,REN_N,A2_X, DW_X, FN_X, M_N,M_X, MT_X, N,MUL_X, N,DIV_X, WEN_Y,WA_X, WB_X, PCR_N,SYNC_N,N,N,N,N,N),
|
||||
FCVT_LU_D-> List(FPU_Y,N,BR_N, REN_N,REN_N,A2_X, DW_X, FN_X, M_N,M_X, MT_X, N,MUL_X, N,DIV_X, WEN_Y,WA_X, WB_X, PCR_N,SYNC_N,N,N,N,N,N),
|
||||
FEQ_S-> List(FPU_Y,N,BR_N, REN_N,REN_N,A2_X, DW_X, FN_X, M_N,M_X, MT_X, N,MUL_X, N,DIV_X, WEN_Y,WA_X, WB_X, PCR_N,SYNC_N,N,N,N,N,N),
|
||||
FEQ_D-> List(FPU_Y,N,BR_N, REN_N,REN_N,A2_X, DW_X, FN_X, M_N,M_X, MT_X, N,MUL_X, N,DIV_X, WEN_Y,WA_X, WB_X, PCR_N,SYNC_N,N,N,N,N,N),
|
||||
FLT_S-> List(FPU_Y,N,BR_N, REN_N,REN_N,A2_X, DW_X, FN_X, M_N,M_X, MT_X, N,MUL_X, N,DIV_X, WEN_Y,WA_X, WB_X, PCR_N,SYNC_N,N,N,N,N,N),
|
||||
FLT_D-> List(FPU_Y,N,BR_N, REN_N,REN_N,A2_X, DW_X, FN_X, M_N,M_X, MT_X, N,MUL_X, N,DIV_X, WEN_Y,WA_X, WB_X, PCR_N,SYNC_N,N,N,N,N,N),
|
||||
FLE_S-> List(FPU_Y,N,BR_N, REN_N,REN_N,A2_X, DW_X, FN_X, M_N,M_X, MT_X, N,MUL_X, N,DIV_X, WEN_Y,WA_X, WB_X, PCR_N,SYNC_N,N,N,N,N,N),
|
||||
FLE_D-> List(FPU_Y,N,BR_N, REN_N,REN_N,A2_X, DW_X, FN_X, M_N,M_X, MT_X, N,MUL_X, N,DIV_X, WEN_Y,WA_X, WB_X, PCR_N,SYNC_N,N,N,N,N,N),
|
||||
MXTF_S-> List(FPU_Y,N,BR_N, REN_N,REN_Y,A2_X, DW_X, FN_X, M_N,M_X, MT_X, N,MUL_X, N,DIV_X, WEN_N,WA_X, WB_X, PCR_N,SYNC_N,N,N,N,N,N),
|
||||
MXTF_D-> List(FPU_Y,N,BR_N, REN_N,REN_Y,A2_X, DW_X, FN_X, M_N,M_X, MT_X, N,MUL_X, N,DIV_X, WEN_N,WA_X, WB_X, PCR_N,SYNC_N,N,N,N,N,N),
|
||||
FCVT_S_W-> List(FPU_Y,N,BR_N, REN_N,REN_Y,A2_X, DW_X, FN_X, M_N,M_X, MT_X, N,MUL_X, N,DIV_X, WEN_N,WA_X, WB_X, PCR_N,SYNC_N,N,N,N,N,N),
|
||||
FCVT_D_W-> List(FPU_Y,N,BR_N, REN_N,REN_Y,A2_X, DW_X, FN_X, M_N,M_X, MT_X, N,MUL_X, N,DIV_X, WEN_N,WA_X, WB_X, PCR_N,SYNC_N,N,N,N,N,N),
|
||||
FCVT_S_WU-> List(FPU_Y,N,BR_N, REN_N,REN_Y,A2_X, DW_X, FN_X, M_N,M_X, MT_X, N,MUL_X, N,DIV_X, WEN_N,WA_X, WB_X, PCR_N,SYNC_N,N,N,N,N,N),
|
||||
FCVT_D_WU-> List(FPU_Y,N,BR_N, REN_N,REN_Y,A2_X, DW_X, FN_X, M_N,M_X, MT_X, N,MUL_X, N,DIV_X, WEN_N,WA_X, WB_X, PCR_N,SYNC_N,N,N,N,N,N),
|
||||
FCVT_S_L-> List(FPU_Y,N,BR_N, REN_N,REN_Y,A2_X, DW_X, FN_X, M_N,M_X, MT_X, N,MUL_X, N,DIV_X, WEN_N,WA_X, WB_X, PCR_N,SYNC_N,N,N,N,N,N),
|
||||
FCVT_D_L-> List(FPU_Y,N,BR_N, REN_N,REN_Y,A2_X, DW_X, FN_X, M_N,M_X, MT_X, N,MUL_X, N,DIV_X, WEN_N,WA_X, WB_X, PCR_N,SYNC_N,N,N,N,N,N),
|
||||
FCVT_S_LU-> List(FPU_Y,N,BR_N, REN_N,REN_Y,A2_X, DW_X, FN_X, M_N,M_X, MT_X, N,MUL_X, N,DIV_X, WEN_N,WA_X, WB_X, PCR_N,SYNC_N,N,N,N,N,N),
|
||||
FCVT_D_LU-> List(FPU_Y,N,BR_N, REN_N,REN_Y,A2_X, DW_X, FN_X, M_N,M_X, MT_X, N,MUL_X, N,DIV_X, WEN_N,WA_X, WB_X, PCR_N,SYNC_N,N,N,N,N,N),
|
||||
MFFSR-> List(FPU_Y,N,BR_N, REN_N,REN_N,A2_X, DW_X, FN_X, M_N,M_X, MT_X, N,MUL_X, N,DIV_X, WEN_Y,WA_X, WB_X, PCR_N,SYNC_N,N,N,N,N,N),
|
||||
MTFSR-> List(FPU_Y,N,BR_N, REN_N,REN_Y,A2_X, DW_X, FN_X, M_N,M_X, MT_X, N,MUL_X, N,DIV_X, WEN_Y,WA_X, WB_X, PCR_N,SYNC_N,N,N,N,N,N),
|
||||
FLW-> List(FPU_Y,N,BR_N, REN_N,REN_Y,A2_ITYPE,DW_XPR,FN_ADD, M_Y,M_XRD, MT_W, N,MUL_X, N,DIV_X, WEN_N,WA_X, WB_ALU,PCR_N,SYNC_N,N,N,N,N,N),
|
||||
FLD-> List(FPU_Y,N,BR_N, REN_N,REN_Y,A2_ITYPE,DW_XPR,FN_ADD, M_Y,M_XRD, MT_D, N,MUL_X, N,DIV_X, WEN_N,WA_X, WB_ALU,PCR_N,SYNC_N,N,N,N,N,N),
|
||||
FSW-> List(FPU_Y,N,BR_N, REN_N,REN_Y,A2_BTYPE,DW_XPR,FN_ADD, M_Y,M_XWR, MT_W, N,MUL_X, N,DIV_X, WEN_N,WA_X, WB_ALU,PCR_N,SYNC_N,N,N,N,N,N),
|
||||
FSD-> List(FPU_Y,N,BR_N, REN_N,REN_Y,A2_BTYPE,DW_XPR,FN_ADD, M_Y,M_XWR, MT_D, N,MUL_X, N,DIV_X, WEN_N,WA_X, WB_ALU,PCR_N,SYNC_N,N,N,N,N,N))
|
||||
|
||||
val vdecode = Array(
|
||||
// vfence
|
||||
// | eret
|
||||
// | | syscall
|
||||
// vec_val mem_val mul_val div_val renpcr | | | privileged
|
||||
// val | brtype renx2 renx1 s_alu2 dw alu | mem_cmd mem_type| mul_fn | div_fn wen s_wa s_wb | wenpcr irq sync | | | | replay_next
|
||||
// | | | | | | | | | | | | | | | | | | | | | | | | | | |
|
||||
VVCFGIVL-> List(VEC_Y,Y,BR_N, REN_N,REN_Y,A2_ZERO, DW_XPR,FN_ADD, M_N,M_X, MT_X, N,MUL_X, N,DIV_X, WEN_Y,WA_RD,WB_ALU,REN_N,WEN_N,I_X, SYNC_N,N,N,N,N,Y),
|
||||
VVCFG-> List(VEC_Y,Y,BR_N, REN_Y,REN_Y,A2_ZERO, DW_XPR,FN_ADD, M_N,M_X, MT_X, N,MUL_X, N,DIV_X, WEN_N,WA_RD,WB_ALU,REN_N,WEN_N,I_X, SYNC_N,N,N,N,N,Y),
|
||||
VSETVL-> List(VEC_Y,Y,BR_N, REN_N,REN_Y,A2_ZERO, DW_XPR,FN_ADD, M_N,M_X, MT_X, N,MUL_X, N,DIV_X, WEN_Y,WA_RD,WB_ALU,REN_N,WEN_N,I_X, SYNC_N,N,N,N,N,Y),
|
||||
VF-> List(VEC_Y,Y,BR_N, REN_N,REN_Y,A2_ITYPE,DW_XPR,FN_ADD, M_N,M_X, MT_X, N,MUL_X, N,DIV_X, WEN_N,WA_X, WB_ALU,REN_N,WEN_N,I_X, SYNC_N,N,N,N,N,N),
|
||||
VMVV-> List(VEC_Y,Y,BR_N, REN_N,REN_N,A2_X, DW_X, FN_X, M_N,M_X, MT_X, N,MUL_X, N,DIV_X, WEN_N,WA_RD,WB_X, REN_N,WEN_N,I_X, SYNC_N,N,N,N,N,N),
|
||||
VMSV-> List(VEC_Y,Y,BR_N, REN_N,REN_Y,A2_ZERO, DW_XPR,FN_ADD, M_N,M_X, MT_X, N,MUL_X, N,DIV_X, WEN_N,WA_RD,WB_ALU,REN_N,WEN_N,I_X, SYNC_N,N,N,N,N,N),
|
||||
VFMVV-> List(VEC_Y,Y,BR_N, REN_N,REN_N,A2_X, DW_X, FN_X, M_N,M_X, MT_X, N,MUL_X, N,DIV_X, WEN_N,WA_RD,WB_X, REN_N,WEN_N,I_X, SYNC_N,N,N,N,N,N),
|
||||
FENCE_V_L-> List(VEC_Y,Y,BR_N, REN_N,REN_N,A2_X, DW_X, FN_X, M_N,M_X, MT_X, N,MUL_X, N,DIV_X, WEN_N,WA_X, WB_X, REN_N,WEN_N,I_X, SYNC_N,Y,N,N,N,N),
|
||||
FENCE_V_G-> List(VEC_Y,Y,BR_N, REN_N,REN_N,A2_X, DW_X, FN_X, M_N,M_X, MT_X, N,MUL_X, N,DIV_X, WEN_N,WA_X, WB_X, REN_N,WEN_N,I_X, SYNC_N,Y,N,N,N,N),
|
||||
VLD-> List(VEC_Y,Y,BR_N, REN_N,REN_Y,A2_ZERO, DW_XPR,FN_ADD, M_N,M_X, MT_X, N,MUL_X, N,DIV_X, WEN_N,WA_RD,WB_ALU,REN_N,WEN_N,I_X, SYNC_N,N,N,N,N,N),
|
||||
VLW-> List(VEC_Y,Y,BR_N, REN_N,REN_Y,A2_ZERO, DW_XPR,FN_ADD, M_N,M_X, MT_X, N,MUL_X, N,DIV_X, WEN_N,WA_RD,WB_ALU,REN_N,WEN_N,I_X, SYNC_N,N,N,N,N,N),
|
||||
VLWU-> List(VEC_Y,Y,BR_N, REN_N,REN_Y,A2_ZERO, DW_XPR,FN_ADD, M_N,M_X, MT_X, N,MUL_X, N,DIV_X, WEN_N,WA_RD,WB_ALU,REN_N,WEN_N,I_X, SYNC_N,N,N,N,N,N),
|
||||
VLH-> List(VEC_Y,Y,BR_N, REN_N,REN_Y,A2_ZERO, DW_XPR,FN_ADD, M_N,M_X, MT_X, N,MUL_X, N,DIV_X, WEN_N,WA_RD,WB_ALU,REN_N,WEN_N,I_X, SYNC_N,N,N,N,N,N),
|
||||
VLHU-> List(VEC_Y,Y,BR_N, REN_N,REN_Y,A2_ZERO, DW_XPR,FN_ADD, M_N,M_X, MT_X, N,MUL_X, N,DIV_X, WEN_N,WA_RD,WB_ALU,REN_N,WEN_N,I_X, SYNC_N,N,N,N,N,N),
|
||||
VLB-> List(VEC_Y,Y,BR_N, REN_N,REN_Y,A2_ZERO, DW_XPR,FN_ADD, M_N,M_X, MT_X, N,MUL_X, N,DIV_X, WEN_N,WA_RD,WB_ALU,REN_N,WEN_N,I_X, SYNC_N,N,N,N,N,N),
|
||||
VLBU-> List(VEC_Y,Y,BR_N, REN_N,REN_Y,A2_ZERO, DW_XPR,FN_ADD, M_N,M_X, MT_X, N,MUL_X, N,DIV_X, WEN_N,WA_RD,WB_ALU,REN_N,WEN_N,I_X, SYNC_N,N,N,N,N,N),
|
||||
VSD-> List(VEC_Y,Y,BR_N, REN_N,REN_Y,A2_ZERO, DW_XPR,FN_ADD, M_N,M_X, MT_X, N,MUL_X, N,DIV_X, WEN_N,WA_RD,WB_ALU,REN_N,WEN_N,I_X, SYNC_N,N,N,N,N,N),
|
||||
VSW-> List(VEC_Y,Y,BR_N, REN_N,REN_Y,A2_ZERO, DW_XPR,FN_ADD, M_N,M_X, MT_X, N,MUL_X, N,DIV_X, WEN_N,WA_RD,WB_ALU,REN_N,WEN_N,I_X, SYNC_N,N,N,N,N,N),
|
||||
VSH-> List(VEC_Y,Y,BR_N, REN_N,REN_Y,A2_ZERO, DW_XPR,FN_ADD, M_N,M_X, MT_X, N,MUL_X, N,DIV_X, WEN_N,WA_RD,WB_ALU,REN_N,WEN_N,I_X, SYNC_N,N,N,N,N,N),
|
||||
VSB-> List(VEC_Y,Y,BR_N, REN_N,REN_Y,A2_ZERO, DW_XPR,FN_ADD, M_N,M_X, MT_X, N,MUL_X, N,DIV_X, WEN_N,WA_RD,WB_ALU,REN_N,WEN_N,I_X, SYNC_N,N,N,N,N,N),
|
||||
VFLD-> List(VEC_Y,Y,BR_N, REN_N,REN_Y,A2_ZERO, DW_XPR,FN_ADD, M_N,M_X, MT_X, N,MUL_X, N,DIV_X, WEN_N,WA_RD,WB_ALU,REN_N,WEN_N,I_X, SYNC_N,N,N,N,N,N),
|
||||
VFLW-> List(VEC_Y,Y,BR_N, REN_N,REN_Y,A2_ZERO, DW_XPR,FN_ADD, M_N,M_X, MT_X, N,MUL_X, N,DIV_X, WEN_N,WA_RD,WB_ALU,REN_N,WEN_N,I_X, SYNC_N,N,N,N,N,N),
|
||||
VFSD-> List(VEC_Y,Y,BR_N, REN_N,REN_Y,A2_ZERO, DW_XPR,FN_ADD, M_N,M_X, MT_X, N,MUL_X, N,DIV_X, WEN_N,WA_RD,WB_ALU,REN_N,WEN_N,I_X, SYNC_N,N,N,N,N,N),
|
||||
VFSW-> List(VEC_Y,Y,BR_N, REN_N,REN_Y,A2_ZERO, DW_XPR,FN_ADD, M_N,M_X, MT_X, N,MUL_X, N,DIV_X, WEN_N,WA_RD,WB_ALU,REN_N,WEN_N,I_X, SYNC_N,N,N,N,N,N),
|
||||
VLSTD-> List(VEC_Y,Y,BR_N, REN_Y,REN_Y,A2_ZERO, DW_XPR,FN_ADD, M_N,M_X, MT_D, N,MUL_X, N,DIV_X, WEN_N,WA_RD,WB_ALU,REN_N,WEN_N,I_X, SYNC_N,N,N,N,N,N),
|
||||
VLSTW-> List(VEC_Y,Y,BR_N, REN_Y,REN_Y,A2_ZERO, DW_XPR,FN_ADD, M_N,M_X, MT_D, N,MUL_X, N,DIV_X, WEN_N,WA_RD,WB_ALU,REN_N,WEN_N,I_X, SYNC_N,N,N,N,N,N),
|
||||
VLSTWU-> List(VEC_Y,Y,BR_N, REN_Y,REN_Y,A2_ZERO, DW_XPR,FN_ADD, M_N,M_X, MT_D, N,MUL_X, N,DIV_X, WEN_N,WA_RD,WB_ALU,REN_N,WEN_N,I_X, SYNC_N,N,N,N,N,N),
|
||||
VLSTH-> List(VEC_Y,Y,BR_N, REN_Y,REN_Y,A2_ZERO, DW_XPR,FN_ADD, M_N,M_X, MT_D, N,MUL_X, N,DIV_X, WEN_N,WA_RD,WB_ALU,REN_N,WEN_N,I_X, SYNC_N,N,N,N,N,N),
|
||||
VLSTHU-> List(VEC_Y,Y,BR_N, REN_Y,REN_Y,A2_ZERO, DW_XPR,FN_ADD, M_N,M_X, MT_D, N,MUL_X, N,DIV_X, WEN_N,WA_RD,WB_ALU,REN_N,WEN_N,I_X, SYNC_N,N,N,N,N,N),
|
||||
VLSTB-> List(VEC_Y,Y,BR_N, REN_Y,REN_Y,A2_ZERO, DW_XPR,FN_ADD, M_N,M_X, MT_D, N,MUL_X, N,DIV_X, WEN_N,WA_RD,WB_ALU,REN_N,WEN_N,I_X, SYNC_N,N,N,N,N,N),
|
||||
VLSTBU-> List(VEC_Y,Y,BR_N, REN_Y,REN_Y,A2_ZERO, DW_XPR,FN_ADD, M_N,M_X, MT_D, N,MUL_X, N,DIV_X, WEN_N,WA_RD,WB_ALU,REN_N,WEN_N,I_X, SYNC_N,N,N,N,N,N),
|
||||
VSSTD-> List(VEC_Y,Y,BR_N, REN_Y,REN_Y,A2_ZERO, DW_XPR,FN_ADD, M_N,M_X, MT_D, N,MUL_X, N,DIV_X, WEN_N,WA_RD,WB_ALU,REN_N,WEN_N,I_X, SYNC_N,N,N,N,N,N),
|
||||
VSSTW-> List(VEC_Y,Y,BR_N, REN_Y,REN_Y,A2_ZERO, DW_XPR,FN_ADD, M_N,M_X, MT_D, N,MUL_X, N,DIV_X, WEN_N,WA_RD,WB_ALU,REN_N,WEN_N,I_X, SYNC_N,N,N,N,N,N),
|
||||
VSSTH-> List(VEC_Y,Y,BR_N, REN_Y,REN_Y,A2_ZERO, DW_XPR,FN_ADD, M_N,M_X, MT_D, N,MUL_X, N,DIV_X, WEN_N,WA_RD,WB_ALU,REN_N,WEN_N,I_X, SYNC_N,N,N,N,N,N),
|
||||
VSSTB-> List(VEC_Y,Y,BR_N, REN_Y,REN_Y,A2_ZERO, DW_XPR,FN_ADD, M_N,M_X, MT_D, N,MUL_X, N,DIV_X, WEN_N,WA_RD,WB_ALU,REN_N,WEN_N,I_X, SYNC_N,N,N,N,N,N),
|
||||
VFLSTD-> List(VEC_Y,Y,BR_N, REN_Y,REN_Y,A2_ZERO, DW_XPR,FN_ADD, M_N,M_X, MT_D, N,MUL_X, N,DIV_X, WEN_N,WA_RD,WB_ALU,REN_N,WEN_N,I_X, SYNC_N,N,N,N,N,N),
|
||||
VFLSTW-> List(VEC_Y,Y,BR_N, REN_Y,REN_Y,A2_ZERO, DW_XPR,FN_ADD, M_N,M_X, MT_D, N,MUL_X, N,DIV_X, WEN_N,WA_RD,WB_ALU,REN_N,WEN_N,I_X, SYNC_N,N,N,N,N,N),
|
||||
VFSSTD-> List(VEC_Y,Y,BR_N, REN_Y,REN_Y,A2_ZERO, DW_XPR,FN_ADD, M_N,M_X, MT_D, N,MUL_X, N,DIV_X, WEN_N,WA_RD,WB_ALU,REN_N,WEN_N,I_X, SYNC_N,N,N,N,N,N),
|
||||
VFSSTW-> List(VEC_Y,Y,BR_N, REN_Y,REN_Y,A2_ZERO, DW_XPR,FN_ADD, M_N,M_X, MT_D, N,MUL_X, N,DIV_X, WEN_N,WA_RD,WB_ALU,REN_N,WEN_N,I_X, SYNC_N,N,N,N,N,N),
|
||||
// vfence
|
||||
// | eret
|
||||
// | | syscall
|
||||
// vec_val mem_val mul_val div_val pcr | | | privileged
|
||||
// val | brtype renx2 renx1 s_alu2 dw alu | mem_cmd mem_type| mul_fn | div_fn wen s_wa s_wb | sync | | | | replay_next
|
||||
// | | | | | | | | | | | | | | | | | | | | | | | | |
|
||||
VVCFGIVL-> List(VEC_Y,Y,BR_N, REN_N,REN_Y,A2_ZERO, DW_XPR,FN_ADD, M_N,M_X, MT_X, N,MUL_X, N,DIV_X, WEN_Y,WA_RD,WB_ALU,PCR_N,SYNC_N,N,N,N,N,Y),
|
||||
VVCFG-> List(VEC_Y,Y,BR_N, REN_Y,REN_Y,A2_ZERO, DW_XPR,FN_ADD, M_N,M_X, MT_X, N,MUL_X, N,DIV_X, WEN_N,WA_RD,WB_ALU,PCR_N,SYNC_N,N,N,N,N,Y),
|
||||
VSETVL-> List(VEC_Y,Y,BR_N, REN_N,REN_Y,A2_ZERO, DW_XPR,FN_ADD, M_N,M_X, MT_X, N,MUL_X, N,DIV_X, WEN_Y,WA_RD,WB_ALU,PCR_N,SYNC_N,N,N,N,N,Y),
|
||||
VF-> List(VEC_Y,Y,BR_N, REN_N,REN_Y,A2_ITYPE,DW_XPR,FN_ADD, M_N,M_X, MT_X, N,MUL_X, N,DIV_X, WEN_N,WA_X, WB_ALU,PCR_N,SYNC_N,N,N,N,N,N),
|
||||
VMVV-> List(VEC_Y,Y,BR_N, REN_N,REN_N,A2_X, DW_X, FN_X, M_N,M_X, MT_X, N,MUL_X, N,DIV_X, WEN_N,WA_RD,WB_X, PCR_N,SYNC_N,N,N,N,N,N),
|
||||
VMSV-> List(VEC_Y,Y,BR_N, REN_N,REN_Y,A2_ZERO, DW_XPR,FN_ADD, M_N,M_X, MT_X, N,MUL_X, N,DIV_X, WEN_N,WA_RD,WB_ALU,PCR_N,SYNC_N,N,N,N,N,N),
|
||||
VFMVV-> List(VEC_Y,Y,BR_N, REN_N,REN_N,A2_X, DW_X, FN_X, M_N,M_X, MT_X, N,MUL_X, N,DIV_X, WEN_N,WA_RD,WB_X, PCR_N,SYNC_N,N,N,N,N,N),
|
||||
FENCE_V_L-> List(VEC_Y,Y,BR_N, REN_N,REN_N,A2_X, DW_X, FN_X, M_N,M_X, MT_X, N,MUL_X, N,DIV_X, WEN_N,WA_X, WB_X, PCR_N,SYNC_N,Y,N,N,N,N),
|
||||
FENCE_V_G-> List(VEC_Y,Y,BR_N, REN_N,REN_N,A2_X, DW_X, FN_X, M_N,M_X, MT_X, N,MUL_X, N,DIV_X, WEN_N,WA_X, WB_X, PCR_N,SYNC_N,Y,N,N,N,N),
|
||||
VLD-> List(VEC_Y,Y,BR_N, REN_N,REN_Y,A2_ZERO, DW_XPR,FN_ADD, M_N,M_X, MT_X, N,MUL_X, N,DIV_X, WEN_N,WA_RD,WB_ALU,PCR_N,SYNC_N,N,N,N,N,N),
|
||||
VLW-> List(VEC_Y,Y,BR_N, REN_N,REN_Y,A2_ZERO, DW_XPR,FN_ADD, M_N,M_X, MT_X, N,MUL_X, N,DIV_X, WEN_N,WA_RD,WB_ALU,PCR_N,SYNC_N,N,N,N,N,N),
|
||||
VLWU-> List(VEC_Y,Y,BR_N, REN_N,REN_Y,A2_ZERO, DW_XPR,FN_ADD, M_N,M_X, MT_X, N,MUL_X, N,DIV_X, WEN_N,WA_RD,WB_ALU,PCR_N,SYNC_N,N,N,N,N,N),
|
||||
VLH-> List(VEC_Y,Y,BR_N, REN_N,REN_Y,A2_ZERO, DW_XPR,FN_ADD, M_N,M_X, MT_X, N,MUL_X, N,DIV_X, WEN_N,WA_RD,WB_ALU,PCR_N,SYNC_N,N,N,N,N,N),
|
||||
VLHU-> List(VEC_Y,Y,BR_N, REN_N,REN_Y,A2_ZERO, DW_XPR,FN_ADD, M_N,M_X, MT_X, N,MUL_X, N,DIV_X, WEN_N,WA_RD,WB_ALU,PCR_N,SYNC_N,N,N,N,N,N),
|
||||
VLB-> List(VEC_Y,Y,BR_N, REN_N,REN_Y,A2_ZERO, DW_XPR,FN_ADD, M_N,M_X, MT_X, N,MUL_X, N,DIV_X, WEN_N,WA_RD,WB_ALU,PCR_N,SYNC_N,N,N,N,N,N),
|
||||
VLBU-> List(VEC_Y,Y,BR_N, REN_N,REN_Y,A2_ZERO, DW_XPR,FN_ADD, M_N,M_X, MT_X, N,MUL_X, N,DIV_X, WEN_N,WA_RD,WB_ALU,PCR_N,SYNC_N,N,N,N,N,N),
|
||||
VSD-> List(VEC_Y,Y,BR_N, REN_N,REN_Y,A2_ZERO, DW_XPR,FN_ADD, M_N,M_X, MT_X, N,MUL_X, N,DIV_X, WEN_N,WA_RD,WB_ALU,PCR_N,SYNC_N,N,N,N,N,N),
|
||||
VSW-> List(VEC_Y,Y,BR_N, REN_N,REN_Y,A2_ZERO, DW_XPR,FN_ADD, M_N,M_X, MT_X, N,MUL_X, N,DIV_X, WEN_N,WA_RD,WB_ALU,PCR_N,SYNC_N,N,N,N,N,N),
|
||||
VSH-> List(VEC_Y,Y,BR_N, REN_N,REN_Y,A2_ZERO, DW_XPR,FN_ADD, M_N,M_X, MT_X, N,MUL_X, N,DIV_X, WEN_N,WA_RD,WB_ALU,PCR_N,SYNC_N,N,N,N,N,N),
|
||||
VSB-> List(VEC_Y,Y,BR_N, REN_N,REN_Y,A2_ZERO, DW_XPR,FN_ADD, M_N,M_X, MT_X, N,MUL_X, N,DIV_X, WEN_N,WA_RD,WB_ALU,PCR_N,SYNC_N,N,N,N,N,N),
|
||||
VFLD-> List(VEC_Y,Y,BR_N, REN_N,REN_Y,A2_ZERO, DW_XPR,FN_ADD, M_N,M_X, MT_X, N,MUL_X, N,DIV_X, WEN_N,WA_RD,WB_ALU,PCR_N,SYNC_N,N,N,N,N,N),
|
||||
VFLW-> List(VEC_Y,Y,BR_N, REN_N,REN_Y,A2_ZERO, DW_XPR,FN_ADD, M_N,M_X, MT_X, N,MUL_X, N,DIV_X, WEN_N,WA_RD,WB_ALU,PCR_N,SYNC_N,N,N,N,N,N),
|
||||
VFSD-> List(VEC_Y,Y,BR_N, REN_N,REN_Y,A2_ZERO, DW_XPR,FN_ADD, M_N,M_X, MT_X, N,MUL_X, N,DIV_X, WEN_N,WA_RD,WB_ALU,PCR_N,SYNC_N,N,N,N,N,N),
|
||||
VFSW-> List(VEC_Y,Y,BR_N, REN_N,REN_Y,A2_ZERO, DW_XPR,FN_ADD, M_N,M_X, MT_X, N,MUL_X, N,DIV_X, WEN_N,WA_RD,WB_ALU,PCR_N,SYNC_N,N,N,N,N,N),
|
||||
VLSTD-> List(VEC_Y,Y,BR_N, REN_Y,REN_Y,A2_ZERO, DW_XPR,FN_ADD, M_N,M_X, MT_D, N,MUL_X, N,DIV_X, WEN_N,WA_RD,WB_ALU,PCR_N,SYNC_N,N,N,N,N,N),
|
||||
VLSTW-> List(VEC_Y,Y,BR_N, REN_Y,REN_Y,A2_ZERO, DW_XPR,FN_ADD, M_N,M_X, MT_D, N,MUL_X, N,DIV_X, WEN_N,WA_RD,WB_ALU,PCR_N,SYNC_N,N,N,N,N,N),
|
||||
VLSTWU-> List(VEC_Y,Y,BR_N, REN_Y,REN_Y,A2_ZERO, DW_XPR,FN_ADD, M_N,M_X, MT_D, N,MUL_X, N,DIV_X, WEN_N,WA_RD,WB_ALU,PCR_N,SYNC_N,N,N,N,N,N),
|
||||
VLSTH-> List(VEC_Y,Y,BR_N, REN_Y,REN_Y,A2_ZERO, DW_XPR,FN_ADD, M_N,M_X, MT_D, N,MUL_X, N,DIV_X, WEN_N,WA_RD,WB_ALU,PCR_N,SYNC_N,N,N,N,N,N),
|
||||
VLSTHU-> List(VEC_Y,Y,BR_N, REN_Y,REN_Y,A2_ZERO, DW_XPR,FN_ADD, M_N,M_X, MT_D, N,MUL_X, N,DIV_X, WEN_N,WA_RD,WB_ALU,PCR_N,SYNC_N,N,N,N,N,N),
|
||||
VLSTB-> List(VEC_Y,Y,BR_N, REN_Y,REN_Y,A2_ZERO, DW_XPR,FN_ADD, M_N,M_X, MT_D, N,MUL_X, N,DIV_X, WEN_N,WA_RD,WB_ALU,PCR_N,SYNC_N,N,N,N,N,N),
|
||||
VLSTBU-> List(VEC_Y,Y,BR_N, REN_Y,REN_Y,A2_ZERO, DW_XPR,FN_ADD, M_N,M_X, MT_D, N,MUL_X, N,DIV_X, WEN_N,WA_RD,WB_ALU,PCR_N,SYNC_N,N,N,N,N,N),
|
||||
VSSTD-> List(VEC_Y,Y,BR_N, REN_Y,REN_Y,A2_ZERO, DW_XPR,FN_ADD, M_N,M_X, MT_D, N,MUL_X, N,DIV_X, WEN_N,WA_RD,WB_ALU,PCR_N,SYNC_N,N,N,N,N,N),
|
||||
VSSTW-> List(VEC_Y,Y,BR_N, REN_Y,REN_Y,A2_ZERO, DW_XPR,FN_ADD, M_N,M_X, MT_D, N,MUL_X, N,DIV_X, WEN_N,WA_RD,WB_ALU,PCR_N,SYNC_N,N,N,N,N,N),
|
||||
VSSTH-> List(VEC_Y,Y,BR_N, REN_Y,REN_Y,A2_ZERO, DW_XPR,FN_ADD, M_N,M_X, MT_D, N,MUL_X, N,DIV_X, WEN_N,WA_RD,WB_ALU,PCR_N,SYNC_N,N,N,N,N,N),
|
||||
VSSTB-> List(VEC_Y,Y,BR_N, REN_Y,REN_Y,A2_ZERO, DW_XPR,FN_ADD, M_N,M_X, MT_D, N,MUL_X, N,DIV_X, WEN_N,WA_RD,WB_ALU,PCR_N,SYNC_N,N,N,N,N,N),
|
||||
VFLSTD-> List(VEC_Y,Y,BR_N, REN_Y,REN_Y,A2_ZERO, DW_XPR,FN_ADD, M_N,M_X, MT_D, N,MUL_X, N,DIV_X, WEN_N,WA_RD,WB_ALU,PCR_N,SYNC_N,N,N,N,N,N),
|
||||
VFLSTW-> List(VEC_Y,Y,BR_N, REN_Y,REN_Y,A2_ZERO, DW_XPR,FN_ADD, M_N,M_X, MT_D, N,MUL_X, N,DIV_X, WEN_N,WA_RD,WB_ALU,PCR_N,SYNC_N,N,N,N,N,N),
|
||||
VFSSTD-> List(VEC_Y,Y,BR_N, REN_Y,REN_Y,A2_ZERO, DW_XPR,FN_ADD, M_N,M_X, MT_D, N,MUL_X, N,DIV_X, WEN_N,WA_RD,WB_ALU,PCR_N,SYNC_N,N,N,N,N,N),
|
||||
VFSSTW-> List(VEC_Y,Y,BR_N, REN_Y,REN_Y,A2_ZERO, DW_XPR,FN_ADD, M_N,M_X, MT_D, N,MUL_X, N,DIV_X, WEN_N,WA_RD,WB_ALU,PCR_N,SYNC_N,N,N,N,N,N),
|
||||
|
||||
VENQCMD-> List(VEC_Y,Y,BR_N, REN_Y,REN_Y,A2_ZERO, DW_XPR,FN_ADD, M_N,M_X, MT_X, N,MUL_X, N,DIV_X, WEN_N,WA_RD,WB_ALU,REN_N,WEN_N,I_X, SYNC_N,N,N,N,Y,N),
|
||||
VENQIMM1-> List(VEC_Y,Y,BR_N, REN_Y,REN_Y,A2_ZERO, DW_XPR,FN_ADD, M_N,M_X, MT_X, N,MUL_X, N,DIV_X, WEN_N,WA_RD,WB_ALU,REN_N,WEN_N,I_X, SYNC_N,N,N,N,Y,N),
|
||||
VENQIMM2-> List(VEC_Y,Y,BR_N, REN_Y,REN_Y,A2_ZERO, DW_XPR,FN_ADD, M_N,M_X, MT_X, N,MUL_X, N,DIV_X, WEN_N,WA_RD,WB_ALU,REN_N,WEN_N,I_X, SYNC_N,N,N,N,Y,N),
|
||||
VENQCNT-> List(VEC_Y,Y,BR_N, REN_Y,REN_Y,A2_ZERO, DW_XPR,FN_ADD, M_N,M_X, MT_X, N,MUL_X, N,DIV_X, WEN_N,WA_RD,WB_ALU,REN_N,WEN_N,I_X, SYNC_N,N,N,N,Y,N),
|
||||
VXCPTEVAC-> List(VEC_Y,Y,BR_N, REN_N,REN_Y,A2_ZERO, DW_XPR,FN_ADD, M_N,M_X, MT_X, N,MUL_X, N,DIV_X, WEN_N,WA_RD,WB_ALU,REN_N,WEN_N,I_X, SYNC_N,N,N,N,Y,N),
|
||||
VXCPTKILL-> List(VEC_Y,Y,BR_N, REN_N,REN_N,A2_X, DW_X, FN_X, M_N,M_X, MT_X, N,MUL_X, N,DIV_X, WEN_N,WA_X, WB_X, REN_N,WEN_N,I_X, SYNC_N,N,N,N,Y,N),
|
||||
VXCPTHOLD-> List(VEC_Y,Y,BR_N, REN_N,REN_N,A2_X, DW_X, FN_X, M_N,M_X, MT_X, N,MUL_X, N,DIV_X, WEN_N,WA_X, WB_X, REN_N,WEN_N,I_X, SYNC_N,N,N,N,Y,N))
|
||||
VENQCMD-> List(VEC_Y,Y,BR_N, REN_Y,REN_Y,A2_ZERO, DW_XPR,FN_ADD, M_N,M_X, MT_X, N,MUL_X, N,DIV_X, WEN_N,WA_RD,WB_ALU,PCR_N,SYNC_N,N,N,N,Y,N),
|
||||
VENQIMM1-> List(VEC_Y,Y,BR_N, REN_Y,REN_Y,A2_ZERO, DW_XPR,FN_ADD, M_N,M_X, MT_X, N,MUL_X, N,DIV_X, WEN_N,WA_RD,WB_ALU,PCR_N,SYNC_N,N,N,N,Y,N),
|
||||
VENQIMM2-> List(VEC_Y,Y,BR_N, REN_Y,REN_Y,A2_ZERO, DW_XPR,FN_ADD, M_N,M_X, MT_X, N,MUL_X, N,DIV_X, WEN_N,WA_RD,WB_ALU,PCR_N,SYNC_N,N,N,N,Y,N),
|
||||
VENQCNT-> List(VEC_Y,Y,BR_N, REN_Y,REN_Y,A2_ZERO, DW_XPR,FN_ADD, M_N,M_X, MT_X, N,MUL_X, N,DIV_X, WEN_N,WA_RD,WB_ALU,PCR_N,SYNC_N,N,N,N,Y,N),
|
||||
VXCPTEVAC-> List(VEC_Y,Y,BR_N, REN_N,REN_Y,A2_ZERO, DW_XPR,FN_ADD, M_N,M_X, MT_X, N,MUL_X, N,DIV_X, WEN_N,WA_RD,WB_ALU,PCR_N,SYNC_N,N,N,N,Y,N),
|
||||
VXCPTKILL-> List(VEC_Y,Y,BR_N, REN_N,REN_N,A2_X, DW_X, FN_X, M_N,M_X, MT_X, N,MUL_X, N,DIV_X, WEN_N,WA_X, WB_X, PCR_N,SYNC_N,N,N,N,Y,N),
|
||||
VXCPTHOLD-> List(VEC_Y,Y,BR_N, REN_N,REN_N,A2_X, DW_X, FN_X, M_N,M_X, MT_X, N,MUL_X, N,DIV_X, WEN_N,WA_X, WB_X, PCR_N,SYNC_N,N,N,N,Y,N))
|
||||
}
|
||||
|
||||
class rocketCtrl extends Component
|
||||
@@ -322,7 +318,7 @@ class rocketCtrl extends Component
|
||||
|
||||
val id_int_val :: id_vec_val :: id_br_type :: id_renx2 :: id_renx1 :: id_sel_alu2 :: id_fn_dw :: id_fn_alu :: cs0 = cs
|
||||
val id_mem_val :: id_mem_cmd :: id_mem_type :: id_mul_val :: id_mul_fn :: id_div_val :: id_div_fn :: id_wen :: id_sel_wa :: id_sel_wb :: cs1 = cs0
|
||||
val id_ren_pcr :: id_wen_pcr :: id_irq :: id_sync :: id_vfence :: id_eret :: id_syscall :: id_privileged :: id_replay_next :: Nil = cs1
|
||||
val id_pcr :: id_sync :: id_vfence :: id_eret :: id_syscall :: id_privileged :: id_replay_next :: Nil = cs1
|
||||
|
||||
val if_reg_xcpt_ma_inst = Reg(io.dpath.xcpt_ma_inst, resetVal = Bool(false));
|
||||
|
||||
@@ -350,12 +346,10 @@ class rocketCtrl extends Component
|
||||
val ex_reg_mem_cmd = Reg(){UFix(width = 4)};
|
||||
val ex_reg_mem_type = Reg(){UFix(width = 3)};
|
||||
val ex_reg_valid = Reg(resetVal = Bool(false));
|
||||
val ex_reg_wen_pcr = Reg(resetVal = Bool(false));
|
||||
val ex_reg_pcr = Reg(resetVal = PCR_N);
|
||||
val ex_reg_wen = Reg(resetVal = Bool(false));
|
||||
val ex_reg_fp_wen = Reg(resetVal = Bool(false));
|
||||
val ex_reg_eret = Reg(resetVal = Bool(false));
|
||||
val ex_reg_inst_di = Reg(resetVal = Bool(false));
|
||||
val ex_reg_inst_ei = Reg(resetVal = Bool(false));
|
||||
val ex_reg_flush_inst = Reg(resetVal = Bool(false));
|
||||
val ex_reg_xcpt_interrupt = Reg(resetVal = Bool(false));
|
||||
val ex_reg_cause = Reg(){UFix()}
|
||||
@@ -371,11 +365,9 @@ class rocketCtrl extends Component
|
||||
val ex_reg_load_use = Reg(resetVal = Bool(false));
|
||||
|
||||
val mem_reg_valid = Reg(resetVal = Bool(false));
|
||||
val mem_reg_wen_pcr = Reg(resetVal = Bool(false));
|
||||
val mem_reg_pcr = Reg(resetVal = PCR_N);
|
||||
val mem_reg_wen = Reg(resetVal = Bool(false));
|
||||
val mem_reg_fp_wen = Reg(resetVal = Bool(false));
|
||||
val mem_reg_inst_di = Reg(resetVal = Bool(false));
|
||||
val mem_reg_inst_ei = Reg(resetVal = Bool(false));
|
||||
val mem_reg_flush_inst = Reg(resetVal = Bool(false));
|
||||
val mem_reg_xcpt_interrupt = Reg(resetVal = Bool(false));
|
||||
val mem_reg_cause = Reg(){UFix()}
|
||||
@@ -392,11 +384,9 @@ class rocketCtrl extends Component
|
||||
val mem_reg_fp_sboard_set = Reg(resetVal = Bool(false));
|
||||
|
||||
val wb_reg_valid = Reg(resetVal = Bool(false));
|
||||
val wb_reg_wen_pcr = Reg(resetVal = Bool(false));
|
||||
val wb_reg_pcr = Reg(resetVal = PCR_N);
|
||||
val wb_reg_wen = Reg(resetVal = Bool(false));
|
||||
val wb_reg_fp_wen = Reg(resetVal = Bool(false));
|
||||
val wb_reg_inst_di = Reg(resetVal = Bool(false));
|
||||
val wb_reg_inst_ei = Reg(resetVal = Bool(false));
|
||||
val wb_reg_flush_inst = Reg(resetVal = Bool(false));
|
||||
val wb_reg_eret = Reg(resetVal = Bool(false));
|
||||
val wb_reg_exception = Reg(resetVal = Bool(false));
|
||||
@@ -429,7 +419,7 @@ class rocketCtrl extends Component
|
||||
var vec_replay = Bool(false)
|
||||
var vec_stalld = Bool(false)
|
||||
var vec_irq = Bool(false)
|
||||
var vec_irq_cause = UFix(23,5) // don't care
|
||||
var vec_irq_cause = UFix(CAUSE_INTERRUPT+IRQ_IPI) // don't care
|
||||
if (HAVE_VEC)
|
||||
{
|
||||
// vector control
|
||||
@@ -473,16 +463,16 @@ class rocketCtrl extends Component
|
||||
!(id_int_val.toBool || io.fpu.dec.valid || id_vec_val.toBool) ||
|
||||
(id_eret.toBool && io.dpath.status(SR_ET).toBool);
|
||||
|
||||
val p_irq_timer = (io.dpath.status(15).toBool && io.dpath.irq_timer);
|
||||
val p_irq_ipi = (io.dpath.status(13).toBool && io.dpath.irq_ipi);
|
||||
val p_irq_timer = (io.dpath.status(SR_IM+IRQ_TIMER).toBool && io.dpath.irq_timer);
|
||||
val p_irq_ipi = (io.dpath.status(SR_IM+IRQ_IPI).toBool && io.dpath.irq_ipi);
|
||||
val id_interrupt =
|
||||
io.dpath.status(SR_ET).toBool &&
|
||||
((io.dpath.status(15).toBool && io.dpath.irq_timer) ||
|
||||
(io.dpath.status(13).toBool && io.dpath.irq_ipi) ||
|
||||
((io.dpath.status(SR_IM+IRQ_TIMER).toBool && io.dpath.irq_timer) ||
|
||||
(io.dpath.status(SR_IM+IRQ_IPI).toBool && io.dpath.irq_ipi) ||
|
||||
vec_irq);
|
||||
val id_cause =
|
||||
Mux(p_irq_ipi, UFix(21,5),
|
||||
Mux(p_irq_timer, UFix(23,5),
|
||||
Mux(p_irq_ipi, UFix(CAUSE_INTERRUPT+IRQ_IPI,6),
|
||||
Mux(p_irq_timer, UFix(CAUSE_INTERRUPT+IRQ_IPI,6),
|
||||
vec_irq_cause))
|
||||
|
||||
when (reset.toBool || io.dpath.killd) {
|
||||
@@ -492,12 +482,10 @@ class rocketCtrl extends Component
|
||||
ex_reg_mul_val := Bool(false);
|
||||
ex_reg_mem_val := Bool(false);
|
||||
ex_reg_valid := Bool(false);
|
||||
ex_reg_wen_pcr := Bool(false)
|
||||
ex_reg_pcr := PCR_N
|
||||
ex_reg_wen := Bool(false);
|
||||
ex_reg_fp_wen := Bool(false);
|
||||
ex_reg_eret := Bool(false);
|
||||
ex_reg_inst_di := Bool(false);
|
||||
ex_reg_inst_ei := Bool(false);
|
||||
ex_reg_flush_inst := Bool(false);
|
||||
ex_reg_xcpt_ma_inst := Bool(false);
|
||||
ex_reg_xcpt_itlb := Bool(false);
|
||||
@@ -517,12 +505,10 @@ class rocketCtrl extends Component
|
||||
ex_reg_mul_val := id_mul_val.toBool && id_waddr != UFix(0);
|
||||
ex_reg_mem_val := id_mem_val.toBool;
|
||||
ex_reg_valid := id_reg_valid
|
||||
ex_reg_wen_pcr := id_wen_pcr
|
||||
ex_reg_pcr := id_pcr
|
||||
ex_reg_wen := id_wen.toBool && id_waddr != UFix(0);
|
||||
ex_reg_fp_wen := io.fpu.dec.wen;
|
||||
ex_reg_eret := id_eret.toBool;
|
||||
ex_reg_inst_di := (id_irq === I_DI);
|
||||
ex_reg_inst_ei := (id_irq === I_EI);
|
||||
ex_reg_flush_inst := (id_sync === SYNC_I);
|
||||
ex_reg_xcpt_ma_inst := id_reg_xcpt_ma_inst;
|
||||
ex_reg_xcpt_itlb := id_reg_xcpt_itlb;
|
||||
@@ -565,14 +551,12 @@ class rocketCtrl extends Component
|
||||
|
||||
when (reset.toBool || io.dpath.killx) {
|
||||
mem_reg_valid := Bool(false);
|
||||
mem_reg_wen_pcr := Bool(false)
|
||||
mem_reg_pcr := PCR_N
|
||||
mem_reg_div_mul_val := Bool(false);
|
||||
mem_reg_wen := Bool(false);
|
||||
mem_reg_fp_wen := Bool(false);
|
||||
mem_reg_eret := Bool(false);
|
||||
mem_reg_mem_val := Bool(false);
|
||||
mem_reg_inst_di := Bool(false);
|
||||
mem_reg_inst_ei := Bool(false);
|
||||
mem_reg_flush_inst := Bool(false);
|
||||
mem_reg_xcpt_ma_inst := Bool(false);
|
||||
mem_reg_xcpt_itlb := Bool(false);
|
||||
@@ -586,14 +570,12 @@ class rocketCtrl extends Component
|
||||
}
|
||||
.otherwise {
|
||||
mem_reg_valid := ex_reg_valid
|
||||
mem_reg_wen_pcr := ex_reg_wen_pcr
|
||||
mem_reg_pcr := ex_reg_pcr
|
||||
mem_reg_div_mul_val := ex_reg_div_val || ex_reg_mul_val;
|
||||
mem_reg_wen := ex_reg_wen;
|
||||
mem_reg_fp_wen := ex_reg_fp_wen;
|
||||
mem_reg_eret := ex_reg_eret;
|
||||
mem_reg_mem_val := ex_reg_mem_val;
|
||||
mem_reg_inst_di := ex_reg_inst_di;
|
||||
mem_reg_inst_ei := ex_reg_inst_ei;
|
||||
mem_reg_flush_inst := ex_reg_flush_inst;
|
||||
mem_reg_xcpt_ma_inst := ex_reg_xcpt_ma_inst;
|
||||
mem_reg_xcpt_itlb := ex_reg_xcpt_itlb;
|
||||
@@ -612,12 +594,10 @@ class rocketCtrl extends Component
|
||||
|
||||
when (io.dpath.killm) {
|
||||
wb_reg_valid := Bool(false)
|
||||
wb_reg_wen_pcr := Bool(false)
|
||||
wb_reg_pcr := PCR_N
|
||||
wb_reg_wen := Bool(false);
|
||||
wb_reg_fp_wen := Bool(false);
|
||||
wb_reg_eret := Bool(false);
|
||||
wb_reg_inst_di := Bool(false);
|
||||
wb_reg_inst_ei := Bool(false);
|
||||
wb_reg_flush_inst := Bool(false);
|
||||
wb_reg_div_mul_val := Bool(false);
|
||||
wb_reg_fp_val := Bool(false)
|
||||
@@ -625,12 +605,10 @@ class rocketCtrl extends Component
|
||||
}
|
||||
.otherwise {
|
||||
wb_reg_valid := mem_reg_valid
|
||||
wb_reg_wen_pcr := mem_reg_wen_pcr
|
||||
wb_reg_pcr := mem_reg_pcr
|
||||
wb_reg_wen := mem_reg_wen;
|
||||
wb_reg_fp_wen := mem_reg_fp_wen;
|
||||
wb_reg_eret := mem_reg_eret;
|
||||
wb_reg_inst_di := mem_reg_inst_di;
|
||||
wb_reg_inst_ei := mem_reg_inst_ei;
|
||||
wb_reg_flush_inst := mem_reg_flush_inst;
|
||||
wb_reg_div_mul_val := mem_reg_div_mul_val;
|
||||
wb_reg_fp_val := mem_reg_fp_val
|
||||
@@ -752,10 +730,10 @@ class rocketCtrl extends Component
|
||||
io.dpath.exception := wb_reg_exception;
|
||||
io.dpath.cause := wb_reg_cause;
|
||||
io.dpath.badvaddr_wen := wb_badvaddr_wen;
|
||||
io.dpath.vec_irq_aux_wen := wb_reg_exception && wb_reg_cause >= UFix(24)
|
||||
io.dpath.vec_irq_aux_wen := wb_reg_exception && wb_reg_cause >= UFix(24) && wb_reg_cause < UFix(32)
|
||||
|
||||
io.dpath.sel_pc :=
|
||||
Mux(wb_reg_exception, PC_EVEC, // exception
|
||||
Mux(wb_reg_exception, PC_PCR, // exception
|
||||
Mux(replay_wb, PC_WB, // replay
|
||||
Mux(wb_reg_eret, PC_PCR, // eret instruction
|
||||
Mux(ex_reg_btb_hit && !br_taken, PC_EX4, // mispredicted not taken branch
|
||||
@@ -853,12 +831,9 @@ class rocketCtrl extends Component
|
||||
io.dpath.wb_valid := wb_reg_valid && !vec_replay
|
||||
io.dpath.sel_wa := id_sel_wa.toBool;
|
||||
io.dpath.sel_wb := id_sel_wb;
|
||||
io.dpath.ren_pcr := id_ren_pcr.toBool;
|
||||
io.dpath.wen_pcr := wb_reg_wen_pcr
|
||||
io.dpath.pcr := wb_reg_pcr.toUFix
|
||||
io.dpath.id_eret := id_eret.toBool;
|
||||
io.dpath.wb_eret := wb_reg_eret;
|
||||
io.dpath.irq_disable := wb_reg_inst_di;
|
||||
io.dpath.irq_enable := wb_reg_inst_ei;
|
||||
io.dpath.ex_mem_type := ex_reg_mem_type
|
||||
|
||||
io.fpu.valid := !io.dpath.killd && io.fpu.dec.valid
|
||||
|
||||
@@ -71,7 +71,6 @@ class rocketDpath extends Component
|
||||
val ex_reg_ctrl_div_val = Reg(resetVal = Bool(false));
|
||||
val ex_reg_ctrl_div_fn = Reg() { UFix() };
|
||||
val ex_reg_ctrl_sel_wb = Reg() { UFix() };
|
||||
val ex_reg_ctrl_ren_pcr = Reg(resetVal = Bool(false));
|
||||
val ex_wdata = Wire() { Bits() };
|
||||
|
||||
// memory definitions
|
||||
@@ -116,10 +115,9 @@ class rocketDpath extends Component
|
||||
Mux(io.ctrl.sel_pc === PC_EX4, ex_pc_plus4,
|
||||
Mux(io.ctrl.sel_pc === PC_BR, ex_branch_target,
|
||||
Mux(io.ctrl.sel_pc === PC_JR, ex_effective_address,
|
||||
Mux(io.ctrl.sel_pc === PC_PCR, wb_reg_wdata(VADDR_BITS,0), // only used for ERET
|
||||
Mux(io.ctrl.sel_pc === PC_EVEC, Cat(pcr.io.evec(VADDR_BITS-1), pcr.io.evec),
|
||||
Mux(io.ctrl.sel_pc === PC_PCR, Cat(pcr.io.evec(VADDR_BITS-1), pcr.io.evec),
|
||||
Mux(io.ctrl.sel_pc === PC_WB, wb_reg_pc,
|
||||
if_pc_plus4))))))); // PC_4
|
||||
if_pc_plus4)))))) // PC_4
|
||||
|
||||
when (!io.ctrl.stallf) {
|
||||
if_reg_pc := if_next_pc.toUFix;
|
||||
@@ -219,7 +217,6 @@ class rocketDpath extends Component
|
||||
ex_reg_ctrl_mul_fn := io.ctrl.mul_fn;
|
||||
ex_reg_ctrl_div_fn := io.ctrl.div_fn;
|
||||
ex_reg_ctrl_sel_wb := io.ctrl.sel_wb;
|
||||
ex_reg_ctrl_ren_pcr := io.ctrl.ren_pcr;
|
||||
|
||||
when(io.ctrl.killd) {
|
||||
ex_reg_ctrl_div_val := Bool(false);
|
||||
@@ -284,10 +281,8 @@ class rocketDpath extends Component
|
||||
io.dtlb.vpn := ex_effective_address >> UFix(PGIDX_BITS)
|
||||
|
||||
// processor control regfile read
|
||||
pcr.io.r.en := ex_reg_ctrl_ren_pcr | ex_reg_ctrl_eret;
|
||||
pcr.io.r.addr :=
|
||||
Mux(ex_reg_ctrl_eret, PCR_EPC,
|
||||
ex_reg_raddr2);
|
||||
pcr.io.r.en := io.ctrl.pcr != PCR_N
|
||||
pcr.io.r.addr := wb_reg_raddr1
|
||||
|
||||
pcr.io.host <> io.host
|
||||
|
||||
@@ -315,10 +310,9 @@ class rocketDpath extends Component
|
||||
// writeback select mux
|
||||
ex_wdata :=
|
||||
Mux(ex_reg_ctrl_sel_wb === WB_PC, Cat(Fill(64-VADDR_BITS, ex_pc_plus4(VADDR_BITS-1)), ex_pc_plus4),
|
||||
Mux(ex_reg_ctrl_sel_wb === WB_PCR, ex_pcr,
|
||||
Mux(ex_reg_ctrl_sel_wb === WB_TSC, tsc_reg,
|
||||
Mux(ex_reg_ctrl_sel_wb === WB_IRT, irt_reg,
|
||||
ex_alu_out)))).toBits; // WB_ALU
|
||||
ex_alu_out))).toBits // WB_ALU
|
||||
|
||||
// subword store data generation
|
||||
val storegen = new StoreDataGen
|
||||
@@ -420,7 +414,7 @@ class rocketDpath extends Component
|
||||
|
||||
rfile.io.w0.addr := wb_reg_waddr
|
||||
rfile.io.w0.en := io.ctrl.wb_wen || wb_reg_ll_wb
|
||||
rfile.io.w0.data := wb_wdata
|
||||
rfile.io.w0.data := Mux(io.ctrl.pcr != PCR_N, pcr.io.r.data, wb_wdata)
|
||||
|
||||
io.ctrl.wb_waddr := wb_reg_waddr
|
||||
io.ctrl.mem_wb := dmem_resp_replay;
|
||||
@@ -432,12 +426,12 @@ class rocketDpath extends Component
|
||||
io.ctrl.fp_sboard_clra := r_dmem_resp_waddr
|
||||
|
||||
// processor control regfile write
|
||||
pcr.io.w.addr := wb_reg_raddr2;
|
||||
pcr.io.w.en := io.ctrl.wen_pcr
|
||||
pcr.io.w.data := wb_reg_wdata
|
||||
pcr.io.w.addr := wb_reg_raddr1
|
||||
pcr.io.w.en := io.ctrl.pcr === PCR_T || io.ctrl.pcr === PCR_S || io.ctrl.pcr === PCR_C
|
||||
pcr.io.w.data := Mux(io.ctrl.pcr === PCR_S, pcr.io.r.data | wb_reg_wdata,
|
||||
Mux(io.ctrl.pcr === PCR_C, pcr.io.r.data & ~wb_reg_wdata,
|
||||
wb_reg_wdata))
|
||||
|
||||
pcr.io.di := io.ctrl.irq_disable;
|
||||
pcr.io.ei := io.ctrl.irq_enable;
|
||||
pcr.io.eret := io.ctrl.wb_eret;
|
||||
pcr.io.exception := io.ctrl.exception;
|
||||
pcr.io.cause := io.ctrl.cause;
|
||||
|
||||
@@ -64,11 +64,11 @@ class ioDpathPCR extends Bundle()
|
||||
val r = new ioReadPort();
|
||||
val w = new ioWritePort();
|
||||
|
||||
val status = Bits(17, OUTPUT);
|
||||
val status = Bits(32, OUTPUT);
|
||||
val ptbr = UFix(PADDR_BITS, OUTPUT);
|
||||
val evec = UFix(VADDR_BITS, OUTPUT);
|
||||
val exception = Bool(INPUT);
|
||||
val cause = UFix(5, INPUT);
|
||||
val cause = UFix(6, INPUT);
|
||||
val badvaddr_wen = Bool(INPUT);
|
||||
val vec_irq_aux = Bits(64, INPUT)
|
||||
val vec_irq_aux_wen = Bool(INPUT)
|
||||
@@ -105,7 +105,7 @@ class rocketDpathPCR extends Component
|
||||
|
||||
val reg_error_mode = Reg(resetVal = Bool(false));
|
||||
val reg_status_vm = Reg(resetVal = Bool(false));
|
||||
val reg_status_im = Reg(resetVal = Bits(0,8));
|
||||
val reg_status_im = Reg(resetVal = Bits(0,SR_IM_WIDTH));
|
||||
val reg_status_sx = Reg(resetVal = Bool(true));
|
||||
val reg_status_ux = Reg(resetVal = Bool(true));
|
||||
val reg_status_ec = Reg(resetVal = Bool(false));
|
||||
@@ -118,7 +118,6 @@ class rocketDpathPCR extends Component
|
||||
val r_irq_timer = Reg(resetVal = Bool(false));
|
||||
val r_irq_ipi = Reg(resetVal = Bool(false));
|
||||
|
||||
val reg_status = Cat(reg_status_sx, reg_status_ux, reg_status_s, reg_status_ps, reg_status_ec, reg_status_ev, reg_status_ef, reg_status_et);
|
||||
val rdata = Wire() { Bits() };
|
||||
|
||||
val ren = io.r.en || io.host.pcr_ren
|
||||
@@ -131,8 +130,8 @@ class rocketDpathPCR extends Component
|
||||
io.host.pcr_rdy := Mux(io.host.pcr_wen, !io.w.en, !io.r.en)
|
||||
|
||||
io.ptbr_wen := reg_status_vm.toBool && wen && (waddr === PCR_PTBR);
|
||||
io.status := Cat(reg_status_vm, reg_status_im, reg_status);
|
||||
io.evec := reg_ebase;
|
||||
io.status := Cat(reg_status_im, Bits(0,7), reg_status_vm, reg_status_sx, reg_status_ux, reg_status_s, reg_status_ps, reg_status_ec, reg_status_ev, reg_status_ef, reg_status_et);
|
||||
io.evec := Mux(io.exception, reg_ebase, reg_epc)
|
||||
io.ptbr := reg_ptbr;
|
||||
io.debug.error_mode := reg_error_mode;
|
||||
io.r.data := rdata;
|
||||
@@ -164,14 +163,6 @@ class rocketDpathPCR extends Component
|
||||
}
|
||||
}
|
||||
|
||||
when (io.di) {
|
||||
reg_status_et := Bool(false);
|
||||
}
|
||||
|
||||
when (io.ei) {
|
||||
reg_status_et := Bool(true);
|
||||
}
|
||||
|
||||
when (io.eret) {
|
||||
reg_status_s := reg_status_ps;
|
||||
reg_status_et := Bool(true);
|
||||
@@ -188,9 +179,9 @@ class rocketDpathPCR extends Component
|
||||
when (wen) {
|
||||
when (waddr === PCR_STATUS) {
|
||||
reg_status_vm := wdata(SR_VM).toBool;
|
||||
reg_status_im := wdata(15,8);
|
||||
reg_status_sx := wdata(SR_SX).toBool;
|
||||
reg_status_ux := wdata(SR_UX).toBool;
|
||||
reg_status_im := wdata(SR_IM_WIDTH+SR_IM,SR_IM);
|
||||
reg_status_sx := wdata(SR_S64).toBool;
|
||||
reg_status_ux := wdata(SR_U64).toBool;
|
||||
reg_status_s := wdata(SR_S).toBool;
|
||||
reg_status_ps := wdata(SR_PS).toBool;
|
||||
reg_status_ev := Bool(HAVE_VEC) && wdata(SR_EV).toBool;
|
||||
@@ -198,33 +189,32 @@ class rocketDpathPCR extends Component
|
||||
reg_status_ec := Bool(HAVE_RVC) && wdata(SR_EC).toBool;
|
||||
reg_status_et := wdata(SR_ET).toBool;
|
||||
}
|
||||
when (waddr === PCR_EPC) { reg_epc := wdata(VADDR_BITS,0).toUFix; }
|
||||
when (waddr === PCR_BADVADDR) { reg_badvaddr := wdata(VADDR_BITS,0).toUFix; }
|
||||
when (waddr === PCR_EVEC) { reg_ebase := wdata(VADDR_BITS-1,0).toUFix; }
|
||||
when (waddr === PCR_COUNT) { reg_count := wdata(31,0).toUFix; }
|
||||
when (waddr === PCR_COMPARE) { reg_compare := wdata(31,0).toUFix; r_irq_timer := Bool(false); }
|
||||
when (waddr === PCR_CAUSE) { reg_cause := wdata(4,0); }
|
||||
when (waddr === PCR_TOHOST) { reg_tohost := wdata; reg_fromhost := Bits(0) }
|
||||
when (waddr === PCR_FROMHOST) { reg_fromhost := wdata; reg_tohost := Bits(0) }
|
||||
when (waddr === PCR_SEND_IPI) { r_irq_ipi := Bool(true); }
|
||||
when (waddr === PCR_CLR_IPI) { r_irq_ipi := Bool(false); }
|
||||
when (waddr === PCR_K0) { reg_k0 := wdata; }
|
||||
when (waddr === PCR_K1) { reg_k1 := wdata; }
|
||||
when (waddr === PCR_PTBR) { reg_ptbr := Cat(wdata(PADDR_BITS-1, PGIDX_BITS), Bits(0, PGIDX_BITS)).toUFix; }
|
||||
when (waddr === PCR_VECBANK) { reg_vecbank := wdata(7,0) }
|
||||
when (waddr === PCR_EPC) { reg_epc := wdata(VADDR_BITS,0).toUFix; }
|
||||
when (waddr === PCR_EVEC) { reg_ebase := wdata(VADDR_BITS-1,0).toUFix; }
|
||||
when (waddr === PCR_COUNT) { reg_count := wdata(31,0).toUFix; }
|
||||
when (waddr === PCR_COMPARE) { reg_compare := wdata(31,0).toUFix; r_irq_timer := Bool(false); }
|
||||
when (waddr === PCR_FROMHOST) { reg_fromhost := wdata; reg_tohost := Bits(0) }
|
||||
when (waddr === PCR_TOHOST) { reg_tohost := wdata; reg_fromhost := Bits(0) }
|
||||
when (waddr === PCR_SEND_IPI) { r_irq_ipi := Bool(true); }
|
||||
when (waddr === PCR_CLR_IPI) { r_irq_ipi := Bool(false); }
|
||||
when (waddr === PCR_K0) { reg_k0 := wdata; }
|
||||
when (waddr === PCR_K1) { reg_k1 := wdata; }
|
||||
when (waddr === PCR_PTBR) { reg_ptbr := Cat(wdata(PADDR_BITS-1, PGIDX_BITS), Bits(0, PGIDX_BITS)).toUFix; }
|
||||
when (waddr === PCR_VECBANK) { reg_vecbank:= wdata(7,0) }
|
||||
}
|
||||
|
||||
rdata := Bits(0, 64)
|
||||
when (ren) {
|
||||
switch (raddr) {
|
||||
is (PCR_STATUS) { rdata := Cat(Bits(0,47), reg_status_vm, reg_status_im, reg_status); }
|
||||
is (PCR_STATUS) { rdata := io.status }
|
||||
is (PCR_EPC) { rdata := Cat(Fill(64-VADDR_BITS-1, reg_epc(VADDR_BITS)), reg_epc); }
|
||||
is (PCR_BADVADDR) { rdata := Cat(Fill(64-VADDR_BITS-1, reg_badvaddr(VADDR_BITS)), reg_badvaddr); }
|
||||
is (PCR_EVEC) { rdata := Cat(Fill(64-VADDR_BITS, reg_ebase(VADDR_BITS-1)), reg_ebase); }
|
||||
is (PCR_COUNT) { rdata := Cat(Fill(32, reg_count(31)), reg_count); }
|
||||
is (PCR_COMPARE) { rdata := Cat(Fill(32, reg_compare(31)), reg_compare); }
|
||||
is (PCR_CAUSE) { rdata := Cat(Bits(0,59), reg_cause); }
|
||||
is (PCR_CAUSE) { rdata := Cat(reg_cause(5), Bits(0,58), reg_cause(4,0)); }
|
||||
is (PCR_COREID) { rdata := Bits(COREID,64); }
|
||||
is (PCR_IMPL) { rdata := Bits(2) }
|
||||
is (PCR_FROMHOST) { rdata := reg_fromhost; }
|
||||
is (PCR_TOHOST) { rdata := reg_tohost; }
|
||||
is (PCR_K0) { rdata := reg_k0; }
|
||||
|
||||
@@ -32,7 +32,7 @@ class ioDTLB_CPU_resp extends Bundle
|
||||
class ioDTLB extends Bundle
|
||||
{
|
||||
// status bits (from PCR), to check current permission and whether VM is enabled
|
||||
val status = Bits(17,INPUT)
|
||||
val status = Bits(32, INPUT)
|
||||
// invalidate all TLB entries
|
||||
val invalidate = Bool(INPUT)
|
||||
val cpu_req = new ioDTLB_CPU_req().flip
|
||||
|
||||
@@ -177,7 +177,7 @@ class rocketHTIF(w: Int, ncores: Int) extends Component with FourStateCoherence
|
||||
|
||||
val my_reset = Reg(resetVal = Bool(true))
|
||||
when (io.cpu(i).pcr_wen && io.cpu(i).pcr_rdy) {
|
||||
when (io.cpu(i).pcr_addr === UFix(15)) { my_reset := io.cpu(i).pcr_wdata(0) }
|
||||
when (io.cpu(i).pcr_addr === PCR_RESET) { my_reset := io.cpu(i).pcr_wdata(0) }
|
||||
pcr_done := Bool(true)
|
||||
}
|
||||
io.cpu(i).reset := my_reset
|
||||
@@ -186,7 +186,7 @@ class rocketHTIF(w: Int, ncores: Int) extends Component with FourStateCoherence
|
||||
val rdata = Reg() { Bits() }
|
||||
when (io.cpu(i).pcr_ren && io.cpu(i).pcr_rdy) {
|
||||
rdata := io.cpu(i).pcr_rdata
|
||||
when (io.cpu(i).pcr_addr === UFix(15)) { rdata := my_reset }
|
||||
when (io.cpu(i).pcr_addr === PCR_RESET) { rdata := my_reset }
|
||||
pcr_done := Bool(true)
|
||||
}
|
||||
pcr_mux.io.sel(i) := Reg(me)
|
||||
|
||||
@@ -94,10 +94,10 @@ object Instructions
|
||||
val RDCYCLE = Bits("b?????_00000_00000_0000000100_1110111",32);
|
||||
val RDTIME = Bits("b?????_00000_00000_0000001100_1110111",32);
|
||||
val RDINSTRET = Bits("b?????_00000_00000_0000010100_1110111",32);
|
||||
val EI = Bits("b?????_00000_00000_0000000000_1111011",32);
|
||||
val DI = Bits("b?????_00000_00000_0000000001_1111011",32);
|
||||
val MFPCR = Bits("b?????_00000_?????_0000000010_1111011",32);
|
||||
val MTPCR = Bits("b00000_?????_?????_0000000011_1111011",32);
|
||||
val CLEARPCR = Bits("b?????_?????_????????????_000_1111011",32);
|
||||
val SETPCR = Bits("b?????_?????_????????????_001_1111011",32);
|
||||
val MFPCR = Bits("b?????_?????_00000_0000000010_1111011",32);
|
||||
val MTPCR = Bits("b?????_?????_?????_0000000011_1111011",32);
|
||||
val ERET = Bits("b00000_00000_00000_0000000100_1111011",32);
|
||||
val CFLUSH = Bits("b00000_00000_00000_0000000101_1111011",32);
|
||||
// floating point instructions
|
||||
@@ -247,13 +247,13 @@ object Instructions
|
||||
val VSETVL = Bits("b?????_?????_000000000000_101_1110011",32);
|
||||
val VF = Bits("b00000_?????_????????????_111_1110011",32);
|
||||
// vector supervisor instructions
|
||||
val VENQCMD = Bits("b00000_?????_?????_1100000011_1111011",32)
|
||||
val VENQIMM1 = Bits("b00000_?????_?????_1100000100_1111011",32)
|
||||
val VENQIMM2 = Bits("b00000_?????_?????_1100000101_1111011",32)
|
||||
val VENQCNT = Bits("b00000_?????_?????_1100000110_1111011",32)
|
||||
val VXCPTEVAC = Bits("b00000_?????_00000_1100000000_1111011",32)
|
||||
val VXCPTKILL = Bits("b00000_00000_00000_1000000010_1111011",32)
|
||||
val VXCPTHOLD = Bits("b00000_00000_00000_1100000010_1111011",32)
|
||||
val VENQCMD = Bits("b00000_?????_?????_0001010110_1111011",32)
|
||||
val VENQIMM1 = Bits("b00000_?????_?????_0001011110_1111011",32)
|
||||
val VENQIMM2 = Bits("b00000_?????_?????_0001100110_1111011",32)
|
||||
val VENQCNT = Bits("b00000_?????_?????_0001101110_1111011",32)
|
||||
val VXCPTKILL = Bits("b00000_00000_00000_0000010110_1111011",32)
|
||||
val VXCPTEVAC = Bits("b00000_?????_00000_0001000110_1111011",32)
|
||||
val VXCPTHOLD = Bits("b00000_00000_00000_0001001110_1111011",32)
|
||||
|
||||
val NOP = ADDI & Bits("b00000000000000000000001111111111", 32);
|
||||
}
|
||||
@@ -62,7 +62,7 @@ class ioTLB_PTW extends Bundle
|
||||
class ioITLB_CPU(view: List[String] = null) extends Bundle(view)
|
||||
{
|
||||
// status bits (from PCR), to check current permission and whether VM is enabled
|
||||
val status = Bits(17, INPUT);
|
||||
val status = Bits(32, INPUT);
|
||||
// invalidate all TLB entries
|
||||
val invalidate = Bool(INPUT);
|
||||
// lookup requests
|
||||
|
||||
Reference in new issue
Block a user