Andrew Waterman
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e12af07722
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update to newest rocket
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2012-11-25 04:40:46 -08:00 |
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Andrew Waterman
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de2f28193a
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get rid of more global constants
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2012-11-25 04:24:25 -08:00 |
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Andrew Waterman
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c036cdc1ea
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add option for 2-cycle load-use delay
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2012-11-24 22:01:08 -08:00 |
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Andrew Waterman
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b514c7b725
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clean up I$ parity code
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2012-11-24 22:00:43 -08:00 |
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Andrew Waterman
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55082e45c4
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add AVec, which automatically infers element type
should consider modifying Vec as such
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2012-11-24 18:19:28 -08:00 |
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Andrew Waterman
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9372912a9c
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update to newest rocket
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2012-11-20 05:42:44 -08:00 |
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Andrew Waterman
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6d47d18c2b
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catch sigterm to gracefully exit (fixes vcd)
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2012-11-20 05:40:44 -08:00 |
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Andrew Waterman
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7330deb13a
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print stack trace if elaboration fails
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2012-11-20 05:39:48 -08:00 |
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Andrew Waterman
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56f9b9721d
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treat prefetches as read requests
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2012-11-20 05:38:49 -08:00 |
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Andrew Waterman
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2b26082132
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use 1r1w ram for tags; merge tags & permissions
setting the dirty bit now allocates an MSHR (to reuse the existing datapath)
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2012-11-20 04:09:26 -08:00 |
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Andrew Waterman
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72f94d1141
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fix virtual address sign extension detection
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2012-11-20 04:06:57 -08:00 |
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Andrew Waterman
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30038bda8a
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bypass stores to subsequent loads
since we handle subword stores as RMW operations, this occurs frequently
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2012-11-20 01:33:32 -08:00 |
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Yunsup Lee
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4d73e6e38a
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revamp vector yet again with new D$
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2012-11-18 03:14:22 -08:00 |
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Yunsup Lee
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6bd4f93f8c
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pull out prefetch commands from isRead
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2012-11-18 03:13:17 -08:00 |
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Yunsup Lee
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395e4e3dd6
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andrew'x fix for D$ corner case in writeback->abort->probe
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2012-11-18 03:11:06 -08:00 |
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Yunsup Lee
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06eeb90e2a
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vector unit interfaces to the new D$
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2012-11-17 20:07:41 -08:00 |
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Yunsup Lee
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81d711e892
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fix D$ bug; now D$ doesn't respond to prefetches
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2012-11-17 20:06:13 -08:00 |
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Andrew Waterman
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7bcf59a18f
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support continous compilation via "make test"
for c++ emulator only, for now
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2012-11-17 19:58:18 -08:00 |
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Andrew Waterman
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b58214d7e3
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remove more global constants
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2012-11-17 17:25:43 -08:00 |
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Andrew Waterman
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29bc361d6c
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remove global constants; disentangle hwacha a bit
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2012-11-17 17:24:08 -08:00 |
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Andrew Waterman
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cf05b604b3
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upgrade to new rocket; improve vlsi makefiles
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2012-11-17 07:21:29 -08:00 |
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Andrew Waterman
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5a7777fe4d
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clock gate integer datapath more aggressively
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2012-11-17 06:48:44 -08:00 |
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Andrew Waterman
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cc067026a2
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pipeline D$ response -> FPU regfile
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2012-11-17 06:48:11 -08:00 |
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Andrew Waterman
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e68b039133
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fix misc. D$ control bugs
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2012-11-17 06:47:27 -08:00 |
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Andrew Waterman
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dad7b71062
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provide cmd/addr with cache response
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2012-11-16 21:26:12 -08:00 |
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Andrew Waterman
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cb8ac73045
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provide store data with cache response
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2012-11-16 21:15:13 -08:00 |
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Andrew Waterman
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9e010beffe
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fix D$ refill bug
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2012-11-16 21:05:29 -08:00 |
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Andrew Waterman
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672e904c86
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update to new rocket/uncore
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2012-11-16 02:41:50 -08:00 |
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Andrew Waterman
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8dce89703a
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new D$ with better QoR and AMO pipelining
Vector unit is disabled because nack handling needs to be fixed.
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2012-11-16 02:39:33 -08:00 |
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Andrew Waterman
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3e6dc35809
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issue self-probes for uncached read transactions
this facilitates I$ coherence. but it seems like a hack and perhaps
the mechanism should be rethought.
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2012-11-16 02:37:56 -08:00 |
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Andrew Waterman
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a90a1790a5
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improve tlb qor
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2012-11-16 01:59:38 -08:00 |
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Andrew Waterman
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ff8c736d94
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move icache invalidate out of request bundle
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2012-11-16 01:55:45 -08:00 |
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Andrew Waterman
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6d10115b19
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fix D$ tag width
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2012-11-15 16:46:39 -08:00 |
|
Yunsup Lee
|
1a91637673
|
refactored vector queue interface
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2012-11-07 01:16:02 -08:00 |
|
Yunsup Lee
|
be1980dd2d
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refactored vector queue interface
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2012-11-07 01:15:33 -08:00 |
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Yunsup Lee
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29d4c0b857
|
refactored tlb
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2012-11-06 23:54:14 -08:00 |
|
Yunsup Lee
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8764fe786a
|
refactored vector tlb
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2012-11-06 23:53:52 -08:00 |
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Yunsup Lee
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9a02298f6f
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andrew's fix for tlb lockup
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2012-11-06 23:52:58 -08:00 |
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Andrew Waterman
|
e2afae011a
|
factor out global constants
|
2012-11-06 08:18:40 -08:00 |
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Andrew Waterman
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4d1ca8ba3a
|
remove more global consts; refactor DTLBs
D$ now contains DTLB. provide full VAddr with initial request.
VU now has its own DTLBs.
|
2012-11-06 08:13:44 -08:00 |
|
Andrew Waterman
|
e76892f758
|
remove more global constants
|
2012-11-06 02:55:45 -08:00 |
|
Andrew Waterman
|
c5b93798fb
|
factor out more global constants
|
2012-11-05 23:52:32 -08:00 |
|
Yunsup Lee
|
1305372ce7
|
refactor flush logic
|
2012-11-05 23:01:08 -08:00 |
|
Yunsup Lee
|
9844ba1c1d
|
revamp the vector unit with the new frontend
HAVE_PVFB is still broken, we need to multi-thread the frontend
|
2012-11-05 01:44:02 -08:00 |
|
Yunsup Lee
|
ee081d1671
|
modify code to fix UFix := Bits error
|
2012-11-05 01:35:55 -08:00 |
|
Yunsup Lee
|
2a25307a8f
|
revamp the vector unit with the new frontend
|
2012-11-05 01:35:55 -08:00 |
|
Andrew Waterman
|
5b20ed71be
|
move rd=0 check into bypass logic
before, the check was in the write enable logic, but moving it obviated
an awkward corner case for mtpcr with rd=0.
|
2012-11-05 01:30:57 -08:00 |
|
Andrew Waterman
|
5e103054fd
|
fix bug in quine mccluskey
|
2012-11-05 00:28:25 -08:00 |
|
Yunsup Lee
|
dd6ee2571d
|
add vector vm tests
|
2012-11-04 19:29:56 -08:00 |
|
Andrew Waterman
|
0c372fc9ec
|
refactor I$ config into RocketConfiguration
|
2012-11-04 17:00:19 -08:00 |
|