riscv/rocket-chip
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281 Commits

Author SHA1 Message Date
Henry Cook
fc825c7103 MetaData & friends moved to uncore/ 2014-04-23 16:23:51 -07:00
Henry Cook
f4d326b8d7 Prep in HellaCache for extracting MetaData to uncore 2014-04-23 15:43:31 -07:00
Henry Cook
5c62cff2ce put replacement policy in uncore and minor nbdcache cleanups 2014-04-22 16:53:20 -07:00
Henry Cook
1fa505f9ff remove superfluous AVec object 2014-04-16 17:19:32 -07:00
Henry Cook
1da8ef2ddf Added serdes to decouple cache row size from tilelink data size 2014-04-10 12:34:12 -07:00
Henry Cook
910b3b203a removed AddressSpaceConstants, CacheConstants, and TileLinkSizeConstants 2014-04-10 12:32:44 -07:00
Henry Cook
ebdc0a2692 merge Aqcuire and AcquireData. cache line size coupled to tilelink data size 2014-04-10 12:09:52 -07:00
Henry Cook
2c2b3a7678 cleanups supporting uncore hierarchy 2014-01-31 12:07:26 -08:00
Andrew Waterman
57f4d89c90 Generate D$ replay_next signals correctly 2014-01-16 00:16:09 -08:00
Andrew Waterman
6ebdc4d94e Simplify store conditional failure code generation 2014-01-16 00:15:48 -08:00
Andrew Waterman
31060ea8ae Fix fubar long-latency writeback control logic 
Load miss writebacks happening at the same time as multiplication
wasn't working.  Hopefully this does it.
 2014-01-14 04:02:43 -08:00
Andrew Waterman
e8486817e6 Clean up formatting (i.e. remove tabs, semicolons) 2014-01-13 21:43:56 -08:00
Andrew Waterman
07a91bb99a Miscellaneous cleanup 2013-12-09 19:53:14 -08:00
Andrew Waterman
924261e2b2 Update to new privileged ISA... phew 2013-11-25 04:35:15 -08:00
Yunsup Lee
1583560757 fix replay bug, don't respond when cmd is a NOP 2013-10-28 22:35:18 -07:00
Andrew Waterman
f12bbc1e43 working RoCC AccumulatorExample 2013-09-14 22:34:53 -07:00
Andrew Waterman
18968dfbc7 Move store data generation into cache 2013-09-14 16:15:07 -07:00
Andrew Waterman
d053bdc89f Remove Hwacha from Rocket 
Soon it will use the coprocessor interface.
 2013-09-12 22:34:38 -07:00
Andrew Waterman
59f5358435 Implement AQ/RL; move fence logic out of cache 2013-09-12 16:07:30 -07:00
Henry Cook
f9b85d8158 NetworkIOs no longer use thunks 2013-09-10 16:15:19 -07:00
Henry Cook
d06e24ac24 new enum syntax 2013-09-10 10:51:35 -07:00
Henry Cook
3a266cbbfa final Reg changes 2013-08-15 15:28:15 -07:00
Henry Cook
b570435847 Reg standardization 2013-08-13 17:50:02 -07:00
Henry Cook
1a9e43aa11 initial attempt at upgrade 2013-08-12 10:39:11 -07:00
Henry Cook
4eaab214d2 Fold uncore constants into TileLinkConfiguration, update coherence API 2013-08-02 16:29:51 -07:00
Henry Cook
bef6c1db35 minor nbdcache cleanup 2013-08-02 16:29:37 -07:00
Henry Cook
9abdf4e154 Make compatible with scala 2.10. List.sort deprecated. Refactor constants into package object. 2013-07-23 20:27:58 -07:00
Henry Cook
569d8fd796 Merge branch 'tilelink-data' 2013-05-23 14:14:40 -07:00
Henry Cook
69b508ff39 ported caches and htif to use new tilelink 2013-05-21 17:21:04 -07:00
Andrew Waterman
1dab984231 use UFix instead of Bits for arithmetic 2013-05-18 00:45:29 -07:00
Andrew Waterman
474d321cc7 fix meta hazard counter to reset on new meta writes 2013-05-01 16:35:24 -07:00
Andrew Waterman
a6a88fce19 Revert "broaden scope of s1_nack to include new probes accepted by the probe unit on that cycle" 
This reverts commit b41e6bc50519631ba097ac1196737be7107295f9.
 2013-05-01 16:34:45 -07:00
Andrew Waterman
63a38e7982 Revert "temp" 
This reverts commit 73705e6ed8f98d08ce6b30fbe760de694c6563ae.
 2013-05-01 16:34:33 -07:00
Henry Cook
b6945408cb temp 2013-05-01 10:24:36 -07:00
Henry Cook
722bc917d3 broaden scope of s1_nack to include new probes accepted by the probe unit on that cycle 2013-05-01 10:05:54 -07:00
Andrew Waterman
1501e90c1f interlock probe unit on tag RAW hazards 2013-04-30 00:38:22 -07:00
Henry Cook
e8b20f3d38 clear meta state of silently-dropped, clean evictee, so as to prevent a write race on meta array between probes on evictee and refill grant 2013-04-25 17:41:04 -07:00
Andrew Waterman
ae7720e284 guarantee LR/SC forward progress 
the mechanism is to block new probes for several cycles after a successful LR.

this also cleans up the MSHR <-> ProbeUnit interface slightly.
 2013-04-07 19:27:21 -07:00
Andrew Waterman
e74e032c87 simplify MSHR memory response logic 2013-04-06 01:03:37 -07:00
Andrew Waterman
1abb9277db fix LR/SC atomicity violation 
note, it's still not starvation-free.
 2013-04-05 19:13:38 -07:00
Andrew Waterman
8cbdeb2abf add LR/SC support 2013-04-04 17:07:09 -07:00
Henry Cook
f8aebcbf8c fix for cache controller bug: failing to mux correct metadata into mshr.io.old_meta on tag match 2013-04-04 15:50:29 -07:00
Henry Cook
95f0a688e9 Merge branch 'release-xacts' 
Conflicts:
	src/htif.scala
	src/icache.scala
	src/nbdcache.scala
	src/tile.scala
 2013-03-20 17:37:50 -07:00
Henry Cook
273bd34091 Generalized mem arbiter, moved to uncore. Support for multiple banks when acking grants. 2013-03-20 15:53:36 -07:00
Andrew Waterman
ea9d0b771e remove aborts; simplify probes 2013-03-19 15:29:40 -07:00
Henry Cook
e0361840bd writebacks on release network pass asm tests and bmarks 2013-02-28 18:11:40 -08:00
Andrew Waterman
35349d227f update to new Mem style 2013-02-20 16:09:46 -08:00
Andrew Waterman
1fbc20450e don't allow simultaneous reads and writes to the tag ram 2013-01-24 17:55:00 -08:00
Andrew Waterman
37ee843b2c don't use reset combinationally 2013-01-24 17:55:00 -08:00
Andrew Waterman
bb6fbddf1f don't probe the mshr file to inquire about refills 2013-01-24 17:54:59 -08:00
Rimas Avizienis
63060bc0a8 minor tweaks for eos18 tapeout (SRAM r/w port ordering, etc) 2013-01-23 19:27:53 -08:00
Henry Cook
6b00e7ff74 New TileLink bundle names 2013-01-21 17:18:23 -08:00
Henry Cook
a2fa3fd04d Refactored packet headers/payloads 2013-01-15 15:50:37 -08:00
Henry Cook
e1225c5114 standardize IO naming convention 2013-01-07 13:41:36 -08:00
Henry Cook
261e14f831 Refactored uncore conf 2013-01-07 13:41:36 -08:00
Andrew Waterman
f5c53ce35d add ecc support to d$ data rams 
i haven't injected errors yet; it may well be incorrect.
 2012-12-11 15:58:53 -08:00
Andrew Waterman
3f59e439ef fix d$ tag raw hazard 2012-12-07 15:14:20 -08:00
Andrew Waterman
4dda38204f fix d$ reset bug 2012-12-06 03:13:22 -08:00
Andrew Waterman
290d3d226c fix AMO and store bypass bugs 
thanks, torture tester
 2012-12-06 02:07:52 -08:00
Andrew Waterman
4608660f6e torture revealed a couple bugs 
FP loads/stores with certain negative offsets could cause illegal rounding
mode traps, and x's were cropping up in situations that are benign in HW.
 2012-12-04 05:57:53 -08:00
Andrew Waterman
90cae54ac4 fix D$ read/write concurrency bug 2012-11-27 02:42:27 -08:00
Andrew Waterman
608f65e716 don't wastefully read 2x the bits from D$ RAMs 2012-11-26 20:34:30 -08:00
Andrew Waterman
8a6ff5f9aa fix D$ writeback bug 
I swear I did this last week... perhaps I am finally losing it!
 2012-11-25 19:46:48 -08:00
Andrew Waterman
de2f28193a get rid of more global constants 2012-11-25 04:24:25 -08:00
Andrew Waterman
c036cdc1ea add option for 2-cycle load-use delay 2012-11-24 22:01:08 -08:00
Andrew Waterman
2b26082132 use 1r1w ram for tags; merge tags & permissions 
setting the dirty bit now allocates an MSHR (to reuse the existing datapath)
 2012-11-20 04:09:26 -08:00
Andrew Waterman
30038bda8a bypass stores to subsequent loads 
since we handle subword stores as RMW operations, this occurs frequently
 2012-11-20 01:33:32 -08:00
Yunsup Lee
395e4e3dd6 andrew'x fix for D$ corner case in writeback->abort->probe 2012-11-18 03:11:06 -08:00
Yunsup Lee
81d711e892 fix D$ bug; now D$ doesn't respond to prefetches 2012-11-17 20:06:13 -08:00
Andrew Waterman
29bc361d6c remove global constants; disentangle hwacha a bit 2012-11-17 17:24:08 -08:00
Andrew Waterman
e68b039133 fix misc. D$ control bugs 2012-11-17 06:47:27 -08:00
Andrew Waterman
dad7b71062 provide cmd/addr with cache response 2012-11-16 21:26:12 -08:00
Andrew Waterman
cb8ac73045 provide store data with cache response 2012-11-16 21:15:13 -08:00
Andrew Waterman
9e010beffe fix D$ refill bug 2012-11-16 21:05:29 -08:00
Andrew Waterman
8dce89703a new D$ with better QoR and AMO pipelining 
Vector unit is disabled because nack handling needs to be fixed.
 2012-11-16 02:39:33 -08:00
Andrew Waterman
6d10115b19 fix D$ tag width 2012-11-15 16:46:39 -08:00
Yunsup Lee
9a02298f6f andrew's fix for tlb lockup 2012-11-06 23:52:58 -08:00
Andrew Waterman
4d1ca8ba3a remove more global consts; refactor DTLBs 
D$ now contains DTLB. provide full VAddr with initial request.
VU now has its own DTLBs.
 2012-11-06 08:13:44 -08:00
Andrew Waterman
c5b93798fb factor out more global constants 2012-11-05 23:52:32 -08:00
Henry Cook
88ac5af181 Merged consts-as-traits 2012-10-16 16:32:35 -07:00
Andrew Waterman
fc648d13a1 remove old Mux1H; add implicit conversions 2012-10-16 02:24:37 -07:00
Henry Cook
8970b635b2 improvements to implicit RocketConfiguration parameter 2012-10-15 16:29:49 -07:00
Henry Cook
9025d0610c first pass at configuration object passed as implicit parameter 2012-10-07 22:37:29 -07:00
Andrew Waterman
ed8cc4a1cf eliminate D$ probe->WB critical path 2012-10-04 09:05:14 -07:00
Huy Vo
e909093f37 factoring out uncore into separate uncore repo 2012-10-01 16:08:41 -07:00
Henry Cook
b9a9664de5 uncore and rocket changes for new xact types 2012-10-01 10:47:36 -07:00
Andrew Waterman
0f20771664 rename queue to Queue 
fixes build with case-insensitive file system
 2012-08-08 22:11:59 -07:00
Andrew Waterman
938effc053 don't dequeue probe queue during reset 2012-07-22 21:05:52 -07:00
Yunsup Lee
f633a55722 fix dcache tag array size 2012-07-16 22:19:03 -07:00
Huy Vo
fd95159837 INPUT/OUTPUT orderring swapped 2012-07-12 18:16:57 -07:00
Andrew Waterman
bac82762d3 use only one (wide) tag ram for set assoc. caches 2012-07-12 14:50:12 -07:00
Andrew Waterman
4e5f874266 update to new chisel/hwacha 2012-06-08 00:13:14 -07:00
Huy Vo
a99cebb483 ioDecoupled -> FIFOIO, ioPipe -> PipeIO 2012-06-06 18:22:56 -07:00
Huy Vo
04304fe788 moving util out into Chisel standard library 2012-06-06 12:51:26 -07:00
Andrew Waterman
7f6319047e update to new scala/chisel/Mem 2012-06-06 02:47:22 -07:00
Huy Vo
7408c9ab69 removing wires 2012-05-24 10:42:39 -07:00
Henry Cook
87cbae2c8a Removed defunct ioDmem 2012-05-07 17:31:39 -07:00
Henry Cook
622a801bb1 Refactored cpu/cache interface to use nested bundles 2012-05-02 11:54:28 -07:00
Andrew Waterman
c13d3e6f88 fix probe tag read-modify-write atomicity violation 2012-04-26 02:29:31 -07:00
Henry Cook
1ed89f1cab Fixed abort bug: removed uneeded state, added mshr guard on xact_abort.valid and xact_init.ready on same cycle 2012-04-24 17:17:42 -07:00
Henry Cook
a39080d0b1 Fixed abort bug: xact_abort.ready was not pinned high 2012-04-24 17:16:40 -07:00
Andrew Waterman
fb4408b150 fix AMO replay/coherence deadlock 2012-04-15 22:56:02 -07:00
Andrew Waterman
724735f13f fix writeback bug 2012-04-13 03:16:48 -07:00
Andrew Waterman
00d934cfac fix coherence bugs in cache 2012-04-12 21:57:37 -07:00
Andrew Waterman
c0ec3794bf coherence mostly works now 2012-04-10 02:22:45 -07:00
Henry Cook
3cdd166153 Refactored coherence as member rather than trait. MI and MEI protocols. 2012-04-10 00:09:58 -07:00
Henry Cook
0b4937f70f changed coherence message type names 2012-04-09 23:29:31 -07:00
Henry Cook
ed79ec98f7 Refactored coherence better from uncore hub, better coherence function names 2012-04-09 23:29:31 -07:00
Yunsup Lee
1cddd5de56 fix amo locking up problem 2012-03-20 02:16:28 -07:00
Yunsup Lee
264732556f fixes to match verilog X semantics 2012-03-19 03:10:00 -07:00
Andrew Waterman
cfca2d1411 clean up cache interfaces; avoid reserved keywords 2012-03-16 00:44:16 -07:00
Andrew Waterman
820884c7e6 fix probes for smaller cache sizes 
address bits (pgidx_bits-1,taglsb) were omitted from tag checks.
 2012-03-15 23:08:30 -07:00
Andrew Waterman
4684171ac6 fix fence.i for associative caches 2012-03-15 21:23:21 -07:00
Andrew Waterman
7dde7099d2 use broadcast hub and coherent HTIF 2012-03-14 16:44:35 -07:00
Andrew Waterman
1492457df5 add probe replies to HTIF 2012-03-13 16:56:47 -07:00
Andrew Waterman
b0f798962c add probe unit 2012-03-13 16:43:51 -07:00
Henry Cook
287bc1c262 Further refinement of tag_match/tag_hit signals 2012-03-13 11:48:12 -07:00
Andrew Waterman
d76b05bde1 fix way selection on D$ write upgrades 2012-03-13 02:21:02 -07:00
Henry Cook
6229a33dc4 fixed cache controller flush unit deadlock 2012-03-12 22:01:52 -07:00
Andrew Waterman
8ffdac9526 fix D$ store-upgrade bug 
loads to the same address as stores that cause an upgrade
could return the old value
 2012-03-10 15:50:10 -08:00
Andrew Waterman
e3a68848e0 fix D$ critical paths and fix verilog build 2012-03-09 20:02:51 -08:00
Henry Cook
e591d83e91 Fixed global_xact_id propagation bug 2012-03-09 11:05:44 -08:00
Andrew Waterman
766bac88f8 refactor D$ writebacks and flushes 
MSHRs now arbitrate for writebacks and handle flushes.
 2012-03-09 02:55:46 -08:00
Andrew Waterman
5a7c5772a8 clearly distinguish PPN and cache tag 2012-03-07 23:11:17 -08:00
Andrew Waterman
c09eeb7fd2 fix D$ next-state logic 
it was using the CPU command from the wrong pipeline stage,
which was a don't-care with ThreeStateIncoherence.
 2012-03-07 01:42:08 -08:00
Andrew Waterman
a0c9452b86 change D$ to use FourStateCoherence protocol 
instead of ThreeStateIncoherence.
 2012-03-07 01:26:35 -08:00
Andrew Waterman
6e16b04ada implement transaction finish messages 2012-03-06 15:48:08 -08:00
Andrew Waterman
5f33ab24b0 fix merge conflict 
oops :(
 2012-03-06 02:02:53 -08:00
Andrew Waterman
5f12990dfb support memory transaction aborts 2012-03-06 00:35:02 -08:00
Henry Cook
1b3307df32 Removed has_data fields from all coherence messages, increased message type names to compensate 2012-03-02 23:51:53 -08:00
Henry Cook
35f97bf858 Filled out 4 state coherence functions for cache 2012-03-02 21:58:50 -08:00
Yunsup Lee
8678b3d70c clean up ioDecoupled/ioPipe interface 2012-03-01 20:48:46 -08:00
Andrew Waterman
6d03d75835 improve D$ internal interfaces 2012-03-01 20:20:15 -08:00
Andrew Waterman
28cacd953f D$ cleanup - merge ReplayUnit and MSHRFile 2012-03-01 19:30:56 -08:00
Andrew Waterman
52101373e0 clean up D$ store data unit 2012-03-01 19:20:00 -08:00
Andrew Waterman
c38065d0e8 clean up priority encoders 2012-02-29 16:13:14 -08:00
Andrew Waterman
012da6002e replace tile memory interface with ioTileLink 
work in progress towards coherent HTIF. for now, requests
are incoherently passed through a null coherence hub.
 2012-02-29 03:10:47 -08:00
Andrew Waterman
c99f6bbeb7 separate memory request command and data 
also, merge some VLSI/C++ test harness functionality
 2012-02-28 19:06:23 -08:00
Andrew Waterman
2b1c07c723 replace ioDCache with ioMem 2012-02-27 18:36:09 -08:00
Yunsup Lee
bfd0ae125e upgrade to new rocket/vu memory interface, fix amo nack bug in hellacache 2012-02-26 23:46:51 -08:00
Andrew Waterman
6e706c7c74 fix yet another AMO-related replay bug 2012-02-26 20:20:45 -08:00
Huy Vo
5b0f7ccf68 updating rocket code to lastest version of chisel, passes assembly tests in C++ and Verilog as long as you dont use the vector unit 2012-02-26 17:24:08 -08:00
Yunsup Lee
94ba32bbd3 change package name and sbt project name to rocket 2012-02-25 17:09:26 -08:00
Andrew Waterman
7b3cce79e3 allocate a primary miss on a prefetch 2012-02-23 22:40:24 -08:00
Andrew Waterman
3eebf40310 nack CPU requests during any replay 2012-02-22 18:37:13 -08:00
Andrew Waterman
c8f768c8b3 fix AMO replay bug 
like the recent AMO bug fix, but affects stores too.  oops.
 2012-02-21 14:39:54 -08:00
Andrew Waterman
d5608b2728 fix AMO replay bug 
didn't check for structural hazard on AMO unit
if a replay was initiated one cycle before before
a hit-under-miss AMO was issued
 2012-02-21 01:02:16 -08:00
Henry Cook
d46e59a16d Abstract base nbcache class 2012-02-16 12:34:51 -08:00
Henry Cook
124efe5281 Replace nbcache manipulation of meta state bits with abstracted functions 2012-02-16 10:43:40 -08:00
Henry Cook
0671a99712 NBcache works with associativities other than powers of 2 2012-02-13 21:44:32 -08:00