riscv/rocket-chip
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558 Commits

Author SHA1 Message Date
Andrew Waterman
c13d3e6f88 fix probe tag read-modify-write atomicity violation 2012-04-26 02:29:31 -07:00
Andrew Waterman
66f86a2194 use pseudo-LRU replacement for TLBs 2012-04-26 02:29:30 -07:00
Andrew Waterman
a0378c5d2f remove faulting TLB entry after page fault 
this vastly reduces the frequency with which the TLB must be flushed
 2012-04-26 02:29:30 -07:00
Andrew Waterman
6d8fc74378 fix DTLB permissions bug 2012-04-26 02:29:30 -07:00
Henry Cook
1ed89f1cab Fixed abort bug: removed uneeded state, added mshr guard on xact_abort.valid and xact_init.ready on same cycle 2012-04-24 17:17:42 -07:00
Henry Cook
55e86b5cf4 Fixed coherence bug: probe counting for single tile 2012-04-24 17:17:13 -07:00
Henry Cook
a39080d0b1 Fixed abort bug: xact_abort.ready was not pinned high 2012-04-24 17:16:40 -07:00
Andrew Waterman
fb4408b150 fix AMO replay/coherence deadlock 2012-04-15 22:56:02 -07:00
Andrew Waterman
724735f13f fix writeback bug 2012-04-13 03:16:48 -07:00
Andrew Waterman
00d934cfac fix coherence bugs in cache 2012-04-12 21:57:37 -07:00
Henry Cook
fef58f1b3a Policy determined by constants. MSI policy added. 2012-04-11 17:56:59 -07:00
Andrew Waterman
c0ec3794bf coherence mostly works now 2012-04-10 02:22:45 -07:00
Henry Cook
3cdd166153 Refactored coherence as member rather than trait. MI and MEI protocols. 2012-04-10 00:09:58 -07:00
Henry Cook
9c8f849f50 defined abstract coherence traits in base trait, added Incoherent trait, cleaned up incoherent policy 2012-04-09 23:29:32 -07:00
Henry Cook
551e09c9d5 changed coherence type width names to represent max sizes for all protocols 2012-04-09 23:29:32 -07:00
Henry Cook
0b4937f70f changed coherence message type names 2012-04-09 23:29:31 -07:00
Henry Cook
ed79ec98f7 Refactored coherence better from uncore hub, better coherence function names 2012-04-09 23:29:31 -07:00
Andrew Waterman
aee9378712 fix coherence bug with multiple probe replies 2012-04-09 21:40:35 -07:00
Huy Vo
c9c3bd02bc kill mem stage if fpu nacks in mem stage 2012-04-01 17:02:32 -07:00
Andrew Waterman
7f254d9670 refine FP bugfixes 2012-04-01 14:52:33 -07:00
Huy Vo
c7c35322c2 two bug fixes to fpu 2012-03-31 22:23:51 -07:00
Andrew Waterman
a09e8d1c55 remove I$ prefetcher for now 
there's a bug in it, and I don't have time to fix it at the moment.
 2012-03-27 15:43:56 -07:00
Andrew Waterman
452876af37 fence on vvcfg; implement fence.v.g correctly 2012-03-27 14:49:00 -07:00
Yunsup Lee
bb704dc0c9 fix vector length calc bug, thanks chris and andrew 2012-03-27 12:04:07 -07:00
Andrew Waterman
6bda8674bd no dessert tonight :( 2012-03-26 23:50:09 -07:00
Yunsup Lee
a70f0414fa fix a workaroundable bug 2012-03-26 20:51:54 -07:00
Yunsup Lee
32d95e9594 fix -1:0 index problem for direct map case 2012-03-26 17:00:01 -07:00
Andrew Waterman
e2fe525fb6 remove bug from dessert 2012-03-26 14:18:57 -07:00
Yunsup Lee
e6b0e565de turn HAVE_VEC on 2012-03-26 01:21:39 -07:00
Andrew Waterman
5f53cd4ac1 reduce HTIF width 2012-03-25 23:49:59 -07:00
Andrew Waterman
ef505de017 reduce HTIF width 2012-03-25 23:49:45 -07:00
Andrew Waterman
31f0b600fd add dessert 2012-03-25 23:03:20 -07:00
Andrew Waterman
1666d3fbd7 loop host.in to host.out during reset 2012-03-25 21:45:10 -07:00
Andrew Waterman
f62a02ab54 remove dumb stuff in top.scala 2012-03-25 21:30:01 -07:00
Andrew Waterman
88bf8a4f23 add mem serdes unit 2012-03-25 17:03:58 -07:00
Andrew Waterman
7fa93da4f5 add backup memory port (disabled for now) 2012-03-25 15:49:32 -07:00
Yunsup Lee
1f33f6bb58 HAVE_VEC is on 2012-03-24 20:54:43 -07:00
Andrew Waterman
86d56ff67b refactor cpu/i$/d$ into Tile (rather than Top) 2012-03-24 16:57:28 -07:00
Andrew Waterman
3a487ac89b improve htif<->pcr interface 2012-03-24 16:57:28 -07:00
Andrew Waterman
54fa6f660d new supervisor mode 2012-03-24 13:03:31 -07:00
Yunsup Lee
65929a62e3 fix reset value for appvl 2012-03-22 15:32:04 -07:00
Yunsup Lee
aaed0241af get rid of vxcptwait 2012-03-21 15:09:04 -07:00
Yunsup Lee
023734175d now fence stalls in decode 2012-03-20 17:10:05 -07:00
Yunsup Lee
e450e3aa40 fix irt counter bug regarding vector stuff 2012-03-20 17:09:54 -07:00
Yunsup Lee
7d7d7f49f9 change the tlb arbiter to a round robing one 2012-03-20 15:21:36 -07:00
Yunsup Lee
1cddd5de56 fix amo locking up problem 2012-03-20 02:16:28 -07:00
Yunsup Lee
56cb9b7a63 fix bug in coherence hub, specifically in abort handling logic 2012-03-20 02:16:28 -07:00
Yunsup Lee
c036fff79c fix id interrupt signal 2012-03-19 15:13:57 -07:00
Yunsup Lee
0edea00166 now HAVE_VEC is true, since it passes the emulator 2012-03-19 03:10:00 -07:00
Yunsup Lee
264732556f fixes to match verilog X semantics 2012-03-19 03:10:00 -07:00
Andrew Waterman
bd27d0fab2 can now take interrupts on stalled instructions 2012-03-19 01:02:06 -07:00
Andrew Waterman
2ed0be65f9 fix RRArbiter 2012-03-19 00:19:33 -07:00
Yunsup Lee
ba06cd953e add chosen 2012-03-18 20:43:17 -07:00
Andrew Waterman
c4a91303fb update vector fence names and encoding 2012-03-18 20:42:38 -07:00
Yunsup Lee
2a01f558ba fix unmasked valid bug in ctrl_vec 2012-03-18 19:55:24 -07:00
Yunsup Lee
98e10ddc3c update vector exception instructions 2012-03-18 16:36:12 -07:00
Yunsup Lee
7493d55d3f add pf fault handling 2012-03-18 15:06:39 -07:00
Yunsup Lee
62ada5ea9e hookup vitlb ptw port 2012-03-17 23:01:06 -07:00
Yunsup Lee
b793d63182 no vector interrupt masking 2012-03-17 23:01:06 -07:00
Yunsup Lee
8a4f95e617 changes to xcpt handling 2012-03-17 17:50:37 -07:00
Yunsup Lee
8c50c81b81 drop vec_irq_aux pcr register, now everything goes through badvaddr 2012-03-17 14:03:57 -07:00
Yunsup Lee
3b4680a834 add vitlb exception port 2012-03-17 14:03:33 -07:00
Andrew Waterman
a47eeb9571 retime D$ bypass into beginning of EX stage 2012-03-16 18:35:54 -07:00
Andrew Waterman
6c26921766 reduce D$ critical path through page table walker 
costs an extra cycle per page table level to resolve a TLB miss. too bad.
 2012-03-16 18:35:54 -07:00
Yunsup Lee
d38603a4ee change number of tlb entries 2012-03-16 17:08:03 -07:00
Andrew Waterman
f0157b9e2a fix coherence bug 
popping wrong store dependence queue
 2012-03-16 01:24:07 -07:00
Andrew Waterman
cfca2d1411 clean up cache interfaces; avoid reserved keywords 2012-03-16 00:44:16 -07:00
Andrew Waterman
820884c7e6 fix probes for smaller cache sizes 
address bits (pgidx_bits-1,taglsb) were omitted from tag checks.
 2012-03-15 23:08:30 -07:00
Andrew Waterman
4684171ac6 fix fence.i for associative caches 2012-03-15 21:23:21 -07:00
Andrew Waterman
2b0bc8df2b use divided clk for htif. UDPATE YOUR FESVR 
by default, we now load programs via a backdoor, because otherwise
it takes too long to simulate.
 2012-03-15 18:36:51 -07:00
Yunsup Lee
ba566f246e change icache parameters 2012-03-15 15:35:12 -07:00
Yunsup Lee
72006160dc fix vxcptwait inst bug, it was incorrect when exception_valid was on before do_xcptwait 2012-03-15 02:10:21 -07:00
Yunsup Lee
f972977da1 refactored VMU, now uses one skid buffer 2012-03-15 01:10:17 -07:00
Henry Cook
b5fa86e844 4-way associative by default 2012-03-14 17:51:12 -07:00
Andrew Waterman
7dde7099d2 use broadcast hub and coherent HTIF 2012-03-14 16:44:35 -07:00
Yunsup Lee
b19d783fbd add vector irq handler 2012-03-14 14:15:28 -07:00
Yunsup Lee
040d62f372 refactored vector exception handling interface 2012-03-13 23:45:34 -07:00
Yunsup Lee
b100544b25 datapath to read out vector state 2012-03-13 23:45:34 -07:00
Yunsup Lee
5655dbd5da add vvcfg and vtcfg instructions 2012-03-13 23:45:34 -07:00
Andrew Waterman
ab6c9350db fix minor coherence bugs 2012-03-13 19:10:54 -07:00
Andrew Waterman
1788c34113 parameterize broadcast hub by # of tiles 2012-03-13 17:12:01 -07:00
Andrew Waterman
1492457df5 add probe replies to HTIF 2012-03-13 16:56:47 -07:00
Andrew Waterman
b0f798962c add probe unit 2012-03-13 16:43:51 -07:00
Huy Vo
fdffb124e3 Merge branch 'master' of github.com:ucb-bar/riscv-rocket 2012-03-13 12:34:39 -07:00
Huy Vo
6fd1527476 fix to rocket vec_dpath, updating makefiles to run xcpt test cases 2012-03-13 12:34:02 -07:00
Henry Cook
287bc1c262 Further refinement of tag_match/tag_hit signals 2012-03-13 11:48:12 -07:00
Andrew Waterman
d76b05bde1 fix way selection on D$ write upgrades 2012-03-13 02:21:02 -07:00
Andrew Waterman
fd29e00db0 support non-power-of-2 queue sizes 
need to manually wrap queue pointers.
 2012-03-13 01:58:28 -07:00
Henry Cook
cbf7b13341 fix hit logic for amos 2012-03-12 22:01:52 -07:00
Henry Cook
6229a33dc4 fixed cache controller flush unit deadlock 2012-03-12 22:01:52 -07:00
Henry Cook
ea0775643b fixed abort bug 2012-03-12 22:01:52 -07:00
Yunsup Lee
1ba5e7b865 changes to the vector exception interface 2012-03-11 21:38:47 -07:00
Yunsup Lee
113a94a21d add vector hold waits 2012-03-11 16:29:19 -07:00
Yunsup Lee
e42a4c767e don't stall on vector fences, keep replaying 2012-03-11 16:29:19 -07:00
Henry Cook
c5dd37ae80 bugfix in locking arbiter 2012-03-11 15:47:27 -07:00
Henry Cook
4ebf637642 More broadcast hub bugfixes 2012-03-11 14:17:27 -07:00
Henry Cook
a4d0025187 fix icache prefetch global_xact_id bug 2012-03-11 00:50:11 -08:00
Yunsup Lee
1aa4b0e93d going back to null coherence hub 2012-03-10 20:16:20 -08:00
Andrew Waterman
8ffdac9526 fix D$ store-upgrade bug 
loads to the same address as stores that cause an upgrade
could return the old value
 2012-03-10 15:50:10 -08:00
Andrew Waterman
4f4b990a4f fix null hub store ack bug 2012-03-10 15:19:12 -08:00
Yunsup Lee
44ff22a26f vector exception handler now handles prefetches correctly 2012-03-10 12:54:36 -08:00
Andrew Waterman
7eb73c325e fix signedness of zero fmul results 
We were using the FMA unit to compute rs1 * rs2 + 0.0 for fmul,
which incorrectly computes +0.0 when rs1 * rs2 == -0.0.  Now we
add -0.0 if rs1*rs2 is negative.
 2012-03-10 00:21:51 -08:00
Andrew Waterman
e3a68848e0 fix D$ critical paths and fix verilog build 2012-03-09 20:02:51 -08:00
Henry Cook
e591d83e91 Fixed global_xact_id propagation bug 2012-03-09 11:05:44 -08:00
Henry Cook
9319130483 Special cased NTILES == 1 due to log2up revision 2012-03-09 11:04:58 -08:00
Andrew Waterman
85504f0ddc fix bug in fence.i and improve test 2012-03-09 03:26:05 -08:00
Andrew Waterman
766bac88f8 refactor D$ writebacks and flushes 
MSHRs now arbitrate for writebacks and handle flushes.
 2012-03-09 02:55:46 -08:00
Andrew Waterman
ff2e47f380 Merge branch 'master' of github.com:ucb-bar/riscv-rocket 2012-03-09 02:08:55 -08:00
Yunsup Lee
a1b30282dd major refactoring on vector exception interface 2012-03-09 01:09:22 -08:00
Yunsup Lee
8acbe98f53 change how fence.*.cv works, now control processor stalls on the fence instruction 2012-03-08 23:32:31 -08:00
Henry Cook
22726ae646 icache and htif now obey require_ack field of TransactionReply. Avoids extraneous TransactionFinish on prefetcher-supplied icache data 2012-03-08 18:47:32 -08:00
Henry Cook
4d2e7172f6 Added require_ack field to TransactionReply bundle 2012-03-08 18:07:44 -08:00
Henry Cook
35c4bd4084 Hub addr comparison bug fix 2012-03-08 16:39:05 -08:00
Henry Cook
788ad327da Fixed dependency queue bug in Broadcast Hub 2012-03-08 11:36:10 -08:00
Henry Cook
7f43dee0c9 PriorityEncoder apply() no longer has recursive depth param 2012-03-08 01:04:26 -08:00
Andrew Waterman
5a7c5772a8 clearly distinguish PPN and cache tag 2012-03-07 23:11:17 -08:00
Andrew Waterman
941873bad1 coherence hub fixes 2012-03-07 21:03:44 -08:00
Henry Cook
7deff5fbe2 Broadcast hub bug fixes for load uncached mem req and store uncached xact rep 2012-03-07 11:40:49 -08:00
Andrew Waterman
c09eeb7fd2 fix D$ next-state logic 
it was using the CPU command from the wrong pipeline stage,
which was a don't-care with ThreeStateIncoherence.
 2012-03-07 01:42:08 -08:00
Andrew Waterman
a0c9452b86 change D$ to use FourStateCoherence protocol 
instead of ThreeStateIncoherence.
 2012-03-07 01:26:35 -08:00
Andrew Waterman
6e2610b0ad fix Mux1H for bundles 2012-03-06 23:38:36 -08:00
Yunsup Lee
81dcb194d3 new vector exception interface 2012-03-06 22:39:15 -08:00
Henry Cook
47a2097507 unified coherence trait functions 2012-03-06 17:33:11 -08:00
Henry Cook
3dd404dcf4 hub code cleanup 2012-03-06 17:01:47 -08:00
Henry Cook
c0ed010bc9 newTransactionOnMiss() 2012-03-06 15:54:41 -08:00
Henry Cook
962e5a54af Added store dependency queues to BroadcastHub. Minor improvements to utils. 2012-03-06 15:54:41 -08:00
Andrew Waterman
499c5b4a2e automatically infer MEM_TAG_BITS 2012-03-06 15:49:28 -08:00
Andrew Waterman
6e16b04ada implement transaction finish messages 2012-03-06 15:48:08 -08:00
Yunsup Lee
dba99e07a9 set MEM_TAG_BITS to 5 when HAVE_VEC is true, since NMSHR=4 2012-03-06 08:54:21 -08:00
Andrew Waterman
5f33ab24b0 fix merge conflict 
oops :(
 2012-03-06 02:02:53 -08:00
Andrew Waterman
5f12990dfb support memory transaction aborts 2012-03-06 00:35:02 -08:00
Henry Cook
950b5cd900 Added aborted data dequeueing state machine for BroadcastHub 2012-03-05 17:44:30 -08:00
Henry Cook
5c66a6699c Broadcast hub control logic bugfixes and code cleanup 2012-03-05 17:27:55 -08:00
Yunsup Lee
a950d526d2 add prefetch count queue 2012-03-05 12:09:41 -08:00
Yunsup Lee
d4ec7ff4d9 refined vector exception interface 2012-03-03 16:11:54 -08:00
Yunsup Lee
e28a551368 refactor code related to vector exceptions 
- revisied interfaces
- new instructions
 2012-03-03 15:15:00 -08:00
Yunsup Lee
f9fb3978ca fix store prefetch bug, it no longer occupies an entry in the sdq 2012-03-03 15:14:59 -08:00
Henry Cook
1b3307df32 Removed has_data fields from all coherence messages, increased message type names to compensate 2012-03-02 23:51:53 -08:00
Henry Cook
35f97bf858 Filled out 4 state coherence functions for cache 2012-03-02 21:58:50 -08:00
Henry Cook
00989c58bd Correction to probe reply w/ data handling 2012-03-02 17:20:22 -08:00
Andrew Waterman
1e1926ce63 flip direction of ioPipe to match ioDecoupled 2012-03-02 16:18:32 -08:00
Henry Cook
7406908d4a BroadcastHub can be elaborated by C and vlsi backends 2012-03-02 12:19:27 -08:00
Yunsup Lee
54baa0713c hack fence.g.cv to support waiting the control processor 2012-03-02 02:10:26 -08:00
Yunsup Lee
1054cec087 add vec countq interface 2012-03-02 00:43:32 -08:00
Yunsup Lee
8678b3d70c clean up ioDecoupled/ioPipe interface 2012-03-01 20:48:46 -08:00
Andrew Waterman
6d03d75835 improve D$ internal interfaces 2012-03-01 20:20:15 -08:00
Andrew Waterman
28cacd953f D$ cleanup - merge ReplayUnit and MSHRFile 2012-03-01 19:30:56 -08:00
Andrew Waterman
52101373e0 clean up D$ store data unit 2012-03-01 19:20:00 -08:00
Henry Cook
da39810bb2 Fixed elaboration errors in LockingArbiter and BoradcastHub. Fixed ioDecoupled direction error in XactTracker 2012-03-01 18:24:22 -08:00
Henry Cook
9d7707a0a2 Made xact_rep an ioValid, removed has_data member 2012-03-01 18:24:21 -08:00
Yunsup Lee
c7b01230f4 fix mul/div when waddr=0, can't believe torture didn't find this one 2012-03-01 10:15:27 -08:00
Henry Cook
c6162ac743 Unified hub ios. Fixed some hub elaboration errors. 2012-03-01 01:20:57 -08:00
Yunsup Lee
a8ef5e9e27 change NMSHR when HAVE_VEC is true 2012-03-01 01:07:47 -08:00
Yunsup Lee
6847160343 refactor arbiter priorities 2012-03-01 00:22:34 -08:00
Yunsup Lee
f641b44fb8 changes after the module uniquify bug fix 2012-02-29 22:00:59 -08:00
Henry Cook
813ffcbf3e Finished broadcast hub with split mem req types. Untested. 2012-02-29 17:58:15 -08:00
Yunsup Lee
4939b72ba5 Merge branch 'master' of github.com:ucb-bar/riscv-rocket 2012-02-29 17:12:02 -08:00
Yunsup Lee
20d0088f66 temporary fix to match bit widths for Mem 2012-02-29 17:09:31 -08:00
Henry Cook
008ad1f45b Added 'locking' arbiter that won't rearbitrate until the lock signal on the current winning input is low 2012-02-29 17:05:06 -08:00
Henry Cook
c723ef4c50 ioDecoupled now allows inner bundle to be used in covariant positions, i.e. it accepts subtypes 2012-02-29 16:46:16 -08:00
Andrew Waterman
c38065d0e8 clean up priority encoders 2012-02-29 16:13:14 -08:00
Andrew Waterman
b9ec69f8f5 add new Queue singleton 2012-02-29 14:21:42 -08:00
Andrew Waterman
012da6002e replace tile memory interface with ioTileLink 
work in progress towards coherent HTIF. for now, requests
are incoherently passed through a null coherence hub.
 2012-02-29 03:10:47 -08:00
Henry Cook
082b38d315 Broadcast hub nears completion. Still does not handle generation/arbitration for decoupled mem reqs. 2012-02-29 02:59:27 -08:00
Henry Cook
8ff6e21e3a Fixed race between read resps/reps and write req/reps in null hub 2012-02-29 00:44:03 -08:00
Andrew Waterman
c99f6bbeb7 separate memory request command and data 
also, merge some VLSI/C++ test harness functionality
 2012-02-28 19:06:23 -08:00
Henry Cook
040aa9fe02 Added temporary ioMemHub and made coherence hub implementations depend on it rather than ioMem 2012-02-28 17:33:32 -08:00
Daiwei Li
3f998b1353 send vcfg and setvl to vu prefetch queues 2012-02-28 14:54:48 -08:00
Henry Cook
5cc10337b4 Null coherence hub. Begin work on internal tracker logic 2012-02-27 19:10:15 -08:00
Andrew Waterman
2b1c07c723 replace ioDCache with ioMem 2012-02-27 18:36:09 -08:00
Andrew Waterman
1d41a41afa remove extraneous constants 2012-02-27 17:49:48 -08:00
Yunsup Lee
3d96a2d4f0 add fpu.dec.wen := false when HAVE_FPU is turned off 2012-02-27 14:00:58 -08:00
Henry Cook
f0588a0052 Added probe_req ready sigs, GenArray to Vec 2012-02-27 11:26:18 -08:00
Henry Cook
7a8f53a117 probe req transactors in coherence hub 2012-02-27 09:24:33 -08:00
Henry Cook
2275239f33 xact init transactors in coherence hub 2012-02-27 09:24:32 -08:00
Yunsup Lee
bfd0ae125e upgrade to new rocket/vu memory interface, fix amo nack bug in hellacache 2012-02-26 23:46:51 -08:00
Andrew Waterman
6e706c7c74 fix yet another AMO-related replay bug 2012-02-26 20:20:45 -08:00
Andrew Waterman
e12b9eae93 remove ext_mem interface 
hindsight is 20/20
 2012-02-26 18:53:39 -08:00
Andrew Waterman
2d04664a98 simplify cpu-cache interface 2012-02-26 18:26:29 -08:00
Andrew Waterman
ad713a5d83 fix icache ram depth; new chisel 2012-02-26 17:51:46 -08:00
Yunsup Lee
f3bb02b2ea refactored dmem arbiter 2012-02-26 17:38:08 -08:00
Huy Vo
93f41d3359 Merge branch 'master' of github.com:ucb-bar/riscv-rocket 2012-02-26 17:24:23 -08:00
Huy Vo
5b0f7ccf68 updating rocket code to lastest version of chisel, passes assembly tests in C++ and Verilog as long as you dont use the vector unit 2012-02-26 17:24:08 -08:00
Yunsup Lee
766a039ffe small changes to the dtlb arbiter 2012-02-26 16:19:50 -08:00
Daiwei Li
69260756bd change ppn and vpn in dtlb from ufix to bits 2012-02-26 02:54:31 -08:00
Yunsup Lee
49efe4b744 now vu steals cycles from the fpu's fma alu 2012-02-26 01:55:07 -08:00
Daiwei Li
47dbc2a417 head should be working again 2012-02-26 00:30:50 -08:00
Daiwei Li
569698b824 dtlb now arbitrates between cpu, vec, and vec pf 2012-02-25 22:05:30 -08:00
Yunsup Lee
94ba32bbd3 change package name and sbt project name to rocket 2012-02-25 17:09:26 -08:00
Yunsup Lee
946e0c6e4e add vector exception infrastructure 2012-02-25 16:37:56 -08:00
Yunsup Lee
3839e3a318 massive refactoring of vector constants 2012-02-25 15:55:36 -08:00
Henry Cook
3980120279 More stylish bundle param names, some hub progress 2012-02-25 15:27:53 -08:00
Henry Cook
db6d480778 Better foldR 2012-02-25 15:27:09 -08:00
Henry Cook
df97de0fd3 Better abstraction of data bundles 2012-02-25 12:57:01 -08:00
Henry Cook
4fa31b300b Added popcount util 2012-02-25 12:57:01 -08:00
Yunsup Lee
a1600d95db fix bug related to waddr and wdata in wb stage 
for the instructions which don't use waddr/wdata for writeback, the contents were getting overwritten by the ll ops
it manifested itself after cp imul were sharing the alu with the vu
 2012-02-25 12:21:10 -08:00
Yunsup Lee
137fd62007 refactor cpfences 2012-02-25 12:20:36 -08:00
Andrew Waterman
4121fb178c clean up mul/div interface; use VU mul if HAVE_VEC 2012-02-24 19:22:35 -08:00
Andrew Waterman
b3a3289d34 fix (?) external memory request nack interface 2012-02-24 01:42:33 -08:00
Daiwei Li
477f3cde02 added prefetch queues for vu 2012-02-24 00:44:13 -08:00