riscv/rocket-chip
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Author SHA1 Message Date
Stephen Twigg 3b3250339a Explicitely convert results of Bits Muxes to UInt 
Chisel updated to emit SInt result instead of UInt so this commit addresses this change.
 2015-02-03 18:15:01 -08:00
Henry Cook 57340be72b doc update 2015-02-02 01:11:13 -08:00
Henry Cook 6141b3efc5 uncached -> builtin_type 2015-02-02 01:02:06 -08:00
Henry Cook e6491d351f Offset AMOs within beat and return old value 2015-02-02 00:22:21 -08:00
Henry Cook 3aa030f960 Support for uncached sub-block reads and writes, major TileLink and CoherencePolicy refactor. 2015-02-01 20:37:16 -08:00
Henry Cook 7b4e9dd137 Block L2 transactions on the same set from proceeding in parallel 2015-02-01 20:29:23 -08:00
Henry Cook 973eb43128 state machine bug on uncached write hits 2015-02-01 20:29:23 -08:00
Henry Cook f58f8bf385 Make L2 data array use a single Mem 2015-01-25 15:37:04 -08:00
Henry Cook 9ef00d187f %s/master/manager/g + better comments 2014-12-29 22:55:58 -08:00
Henry Cook c76b4bc21d TileLink doc 2014-12-29 22:55:18 -08:00
Henry Cook e62c71203e disconnect unused outer network headers 2014-12-22 18:50:37 -08:00
Henry Cook 2ef4357ca8 acquire allocation bugfix 2014-12-19 17:39:23 -08:00
Henry Cook f234fe65ce Initial verison of L2WritebackUnit, passes MiT2 bmark tests 2014-12-19 03:03:53 -08:00
Henry Cook d121af7f94 Simplify release handling 2014-12-18 17:12:29 -08:00
Henry Cook bfcfc3fe18 refactor cache params 2014-12-17 14:28:14 -08:00
Henry Cook ab39cbb15d cleanup DirectoryRepresentation and coherence params 2014-12-15 19:24:42 -08:00
Andrew Waterman d04da83f96 Make data RAMs 1RW instead of 1R1W 2014-12-15 17:36:17 -08:00
Henry Cook 6a8b66231c Add uncached->cached tilelink converter 2014-12-12 17:06:03 -08:00
Henry Cook 424df2368f 1R/W L2 data array? 
Add TLDataBeats to new LLC; all bmarks pass
 2014-12-12 17:05:21 -08:00
Henry Cook 3026c46a9c Finish adding TLDataBeats to uncore & hub 2014-12-12 17:04:52 -08:00
Henry Cook 2f733a60db Begin adding TLDataBeats to uncore 2014-12-12 17:04:31 -08:00
Henry Cook 404773eb9f fix wb bug 2014-12-03 14:22:39 -08:00
Henry Cook 05b5188ad9 meta and data bundle refactor 2014-11-19 15:55:25 -08:00
Henry Cook a519a43f23 Merge branch 'master' into new-llc 
Conflicts:
	src/main/scala/coherence.scala
	src/main/scala/memserdes.scala
	src/main/scala/tilelink.scala
 2014-11-12 16:25:25 -08:00
Henry Cook cb7e712599 Added uncached write data queue to coherence hub 2014-11-12 12:55:07 -08:00
Henry Cook 82155f333e Major tilelink revision for uncached message types 2014-11-11 17:36:55 -08:00
Henry Cook 35553cc0b7 NullDirectory sharers.count fix 2014-11-11 16:05:25 -08:00
Henry Cook 10309849b7 Remove master_xact_id from Probe and Release 2014-11-06 12:07:33 -08:00
Henry Cook 27c72e5eed nearly all isa tests pass 2014-10-23 21:50:03 -07:00
Henry Cook a891ba1d46 more correct handling of internal state 2014-10-21 17:40:30 -07:00
Henry Cook 044b19dbc1 Compiles and elaborates, does not pass asm tests 2014-10-15 11:46:35 -07:00
Henry Cook 86bdbd6535 new tshrs, compiles but does not elaborate 2014-10-07 22:33:10 -07:00
Henry Cook 394eb38a96 temp; converted voluntary wb tracker 2014-10-03 01:06:49 -07:00
Henry Cook dc1a61264d initial version, acts like old hub 2014-10-03 01:06:49 -07:00
Henry Cook d735f64110 Parameter API update 2014-10-02 16:47:35 -07:00
Henry Cook 7571695320 Removed broken or unfinished modules, new MemPipeIO converter 2014-09-24 15:11:24 -07:00
Henry Cook 82fe22f958 support for multiple tilelink paramerterizations in same design 
Conflicts:

	src/main/scala/cache.scala
 2014-09-24 11:30:40 -07:00
Henry Cook 53b8d7b031 use new coherence methods in l2, ready to query dir logic 2014-09-20 18:01:14 -07:00
Henry Cook 149d51d644 more coherence API cleanup 2014-09-20 16:57:13 -07:00
Henry Cook faed47d131 use thunk for dir info 2014-09-20 16:54:28 -07:00
Henry Cook f7b1e23ead functional style on MuxBundle 2014-09-20 16:54:28 -07:00
Yunsup Lee f249da1803 update README 2014-09-17 11:25:14 -07:00
Yunsup Lee 49b027db2c forgot to add LICENSE file 2014-09-12 15:36:29 -07:00
Yunsup Lee 0b51d70bd2 add LICENSE 2014-09-12 15:31:38 -07:00
Yunsup Lee f8d450b4e2 mark DRAMSideLLC as HasKnownBug 2014-09-11 22:06:03 -07:00
Henry Cook 5e26b4ab66 Merge branch 'dse' 
Conflicts:
	src/main/scala/htif.scala
	src/main/scala/llc.scala
 2014-09-06 06:16:58 -07:00
Scott Beamer f8821b4cc9 better fix with explanation of sbt issue 2014-09-02 15:16:03 -07:00
Scott Beamer bfb662968d fixes sbt error during first run 2014-09-02 14:33:58 -07:00
Henry Cook 712f3a754d merge in master 2014-09-02 12:34:42 -07:00
Henry Cook 17b2359c9a htif parameters trait 2014-08-24 19:27:58 -07:00