riscv/rocket-chip
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Henry Cook 82fe22f958 support for multiple tilelink paramerterizations in same design 
Conflicts:

	src/main/scala/cache.scala
2014-09-24 11:30:40 -07:00
uncore
support for multiple tilelink paramerterizations in same design
2014-09-24 11:30:40 -07:00
Description
Rocket Chip Generator (https://github.com/freechipsproject/rocket-chip)
13 MiB
Languages
Scala 93.1%
C++ 2.1%
Python 2%
Makefile 1.2%
Verilog 0.8%
Other 0.7%