riscv/rocket-chip
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Author SHA1 Message Date
Wesley W. Terpstra 13ec3853ed junctions: get unit tests running again 2016-11-18 17:38:46 -08:00
Wesley W. Terpstra 10dd6070ad groundtest: gracefully handle zero uncached ports 2016-11-18 17:26:28 -08:00
Wesley W. Terpstra 03bca77b33 tilelink2 Metadata: cannot assert data good when !valid 2016-11-18 17:16:12 -08:00
Wesley W. Terpstra be8121eeaf coreplex: fix clock crossing 2016-11-18 17:15:57 -08:00
Wesley W. Terpstra 0082d713af coreplex: disable Stateless config until we implement adapter 2016-11-18 16:23:16 -08:00
Wesley W. Terpstra 8059d33217 groundtest: simplify FancyMemtestConfig for now 2016-11-18 16:18:33 -08:00
Wesley W. Terpstra 04b9a68ea6 MergedPutRegression: wait for all Puts if tlMaxClientXacts != 3 2016-11-18 16:18:33 -08:00
Wesley W. Terpstra cd19bf65b8 regression: fix bad regression that deadlocks SoC with illegal D stall 2016-11-18 16:18:33 -08:00
Wesley W. Terpstra 5f7fa3dae5 regression: remove illegal test which reuses the same ID 2016-11-18 16:18:33 -08:00
Wesley W. Terpstra a6188efc41 rocketchip: break infinite Config loops 2016-11-18 16:18:33 -08:00
Wesley W. Terpstra 37a3c22639 rocketchip: move from using cde to config 2016-11-18 16:18:33 -08:00
Wesley W. Terpstra 40daea2e15 util: Config scheme supporting up with ++ 2016-11-18 16:18:30 -08:00
Wesley W. Terpstra e5febcfa33 rocketchip: there are no more useful parameters to dump 2016-11-18 14:31:42 -08:00
Wesley W. Terpstra 30425d1665 rocketchip: eliminate all Knobs 2016-11-18 14:31:42 -08:00
Wesley W. Terpstra 119ccae9af rocketchip: don't use explicit cde namespace 2016-11-18 14:31:42 -08:00
Wesley W. Terpstra 179c93db42 tilelink2 broadcast: make it controlled via Config 2016-11-17 17:26:49 -08:00
Wesley W. Terpstra f4ca5ea1f3 rocketchip: match simulated memory width to ExtMem.beatBytes 2016-11-17 15:40:47 -08:00
Wesley W. Terpstra 12d0d8bea2 rocketchip: remove obsolete bus configuration 2016-11-17 14:30:15 -08:00
Wesley W. Terpstra c82b371354 rocketchip: remove obsolete TL1 config 2016-11-17 14:24:45 -08:00
Wesley W. Terpstra dfc3a0dafb tilelink2: do not depend on obsolete TL1 configuration 2016-11-17 14:07:53 -08:00
Wesley W. Terpstra 8a0ecdaaad groundtest: ComparatorConfig lives again 2016-11-17 11:07:49 -08:00
Wesley W. Terpstra 06a7b95d0d tilelink2 broadcast: support bufferless Config 2016-11-16 12:25:11 -08:00
Wesley W. Terpstra 3703ed39f7 groundtest: PTW needs atomics 2016-11-16 12:16:54 -08:00
Wesley W. Terpstra 5d2e637a4a tilelink2 Legacy: uncached TL never needs manager_xact_id 2016-11-16 12:16:25 -08:00
Wesley W. Terpstra 10e459fedb rocket: change connection between rocketchip and coreplex 
* rtc and dtm are now crossed half-and-half on the two sides
* groundtest no longer uses riscv platform traits
 2016-11-15 18:27:52 -08:00
Wesley W. Terpstra ab3dafb8bc Monitor: restore Probe&Acquire checks 2016-11-14 15:36:52 -08:00
Wesley W. Terpstra 385b5d5698 axi4: default should be GET_EFFECTS 2016-11-14 15:19:39 -08:00
Wesley W. Terpstra 32fd11935c rocketchip: use TL2 and AXI4 for memory subsytem 2016-11-04 13:36:47 -07:00
Wesley W. TerpstraandHenry Cook 9d77e34bee tilelink2 Filter: make transfer cap robust against large filters 2016-11-04 13:35:36 -07:00
Wesley W. TerpstraandHenry Cook 4a2cf6431b coreplex: make 'mem' port an Option until we can use a Seq 2016-11-04 13:35:36 -07:00
Wesley W. TerpstraandHenry Cook 8f757a9135 coreplex: rename BankedL2 trait to BankedL2CoherenceManagers 2016-11-04 13:35:36 -07:00
Wesley W. TerpstraandHenry Cook b8df59f43b tilelink2 Broadcast: support "bufferless" implementation 2016-11-04 13:35:36 -07:00
Wesley W. TerpstraandHenry Cook 14800f8fb4 tilelink2 Broadcast: only support caching readable devices 2016-11-04 13:35:36 -07:00
Wesley W. TerpstraandHenry Cook d03046d11c coreplex: fix BankedL2 line width 2016-11-04 13:35:36 -07:00
Wesley W. TerpstraandGitHub ea602790a8 Merge pull request #432 from ucb-bar/tl2-address-filtering 
Tl2 address filtering
 2016-11-04 00:12:43 -07:00
Wesley W. Terpstra da3cc3b299 coreplex: TileLink2 l1tol2 memory channels 2016-11-03 22:18:28 -07:00
Wesley W. Terpstra 0f3947bb86 tilelink2 Broadcast: add special case handling for 0 cached clients 2016-11-03 22:18:28 -07:00
Wesley W. Terpstra ba3c83287f tilelink2 Xbar: merge the AddressSets of fractured managers 2016-11-03 22:18:28 -07:00
Wesley W. Terpstra 55326c29bb tilelink2: Filter adapter removes some of the address space 2016-11-03 22:18:23 -07:00
Wesley W. TerpstraandGitHub 163b7577bd Merge pull request #431 from ucb-bar/tl2-broadcast 
Tl2 broadcast
 2016-11-03 15:39:43 -07:00
Wesley W. Terpstra 86ba94781b tilelink2: broadcast coherence manager 2016-11-03 14:37:19 -07:00
Wesley W. Terpstra d067e87a7d tilelink2 Parameters: sinkId is per port, not per manager 2016-11-03 14:37:17 -07:00
Wesley W. TerpstraandGitHub 1b016051e8 Merge pull request #424 from ucb-bar/coreplex-cake 
Coreplex cake
 2016-10-31 16:49:27 -07:00
Wesley W. Terpstra ed4224dde4 tilelink2 AtomicAutomata: fix AccessAck on same cycle as PutFull 
If we send out the PutFull portion of an AMO, the slave is allowed
to respond with AccessAck on the same cycle. In this case, we are
still in the AMO state, but must still match the D response.
 2016-10-31 15:17:10 -07:00
Wesley W. Terpstra f83d1d0aaf coreplex: rename trait CoreplexRISCVPlatform 
This makes it clear we are talking about the devices one expects in the
platform, not the ISA.
 2016-10-31 11:42:47 -07:00
Wesley W. Terpstra f943c5d6ef rocketchip: connect rtcTick to coreplex 2016-10-31 11:42:47 -07:00
Wesley W. Terpstra 4a0b29850c coreplex: reattach clint interrupt 2016-10-31 11:42:47 -07:00
Wesley W. Terpstra a12fea51e8 Plic: skip reserved interrupt in interrupt map printout 2016-10-31 11:42:47 -07:00
Wesley W. Terpstra aabd17d935 rocketchip: must create bundles within Module scope 
1. Bundles be created after base class Module constructor runs
2. Bundles must be created before Module(...) runs

Solution: pass a bundle constructor to the cake base class

Require the constructor to take a parameter so people don't use it by
accident; they should get a type error.

Consistently name all the cake arguments with an _io, _coreplex, _outer,
so that they don't shadow the base class variables you should be using.
 2016-10-31 11:42:47 -07:00
Wesley W. Terpstra d52615c39e coreplex: one IntNode per tile 2016-10-31 11:42:47 -07:00
Wesley W. Terpstra e97844f71e coreplex: make it possible to override the ConfigString 2016-10-31 11:42:47 -07:00
Wesley W. Terpstra 4de1822470 rocketchip: avoid using the nearly defunct GlobalAddrMap 2016-10-31 11:42:47 -07:00
Wesley W. Terpstra 688e1bffdf rocketchip: pull rtcTick out of the coreplex 2016-10-31 11:42:47 -07:00
Wesley W. Terpstra 5bca13ebdb rocketchip: use self-type constraints 2016-10-31 11:42:47 -07:00
Wesley W. Terpstra d51b0b5c02 rocketchip: use self-type 2016-10-31 11:42:47 -07:00
Wesley W. Terpstra 841a31479a coreplex: fix TinyConfig 2016-10-31 11:42:47 -07:00
Wesley W. Terpstra ba529c3716 rocketchip: use TileLink2 interrupts 2016-10-31 11:42:47 -07:00
Wesley W. Terpstra 6505431eac coreplex: use self-type constraints 2016-10-31 11:42:47 -07:00
Wesley W. Terpstra ac886026e6 rocketchip: reduce number of type parameters 2016-10-31 11:42:47 -07:00
Wesley W. Terpstra 043ed48c8c tilelink2 HintHandler: delay answers to help TL1 legacy clients 2016-10-31 11:42:47 -07:00
Wesley W. Terpstra 72a7948ad2 rocketchip Periphery: move atomics before WidthWidget => 64-bit AMOs 2016-10-31 11:42:47 -07:00
Wesley W. Terpstra 015c3b862a diplomacy: print out bus widths on edges in agent graph 2016-10-31 11:42:47 -07:00
Wesley W. Terpstra 92ee498521 rocket scratchpad: support atomics 2016-10-31 11:42:47 -07:00
Wesley W. Terpstra 0cc00e7616 regressions: test scratchpad 2016-10-31 11:42:47 -07:00
Wesley W. Terpstra d2e9fa8ec6 Plic: remove path from ready to bits 2016-10-31 11:42:47 -07:00
Wesley W. Terpstra 545154c1c3 groundtest: make it happy with TL2 addressing 2016-10-31 11:42:47 -07:00
Wesley W. Terpstra 9a26cb7ec7 Debug: mark the debug device executable 2016-10-31 11:42:47 -07:00
Wesley W. Terpstra e9725aea2f rocketchip: all of the address map now comes from TL2 2016-10-31 11:42:44 -07:00
Wesley W. Terpstra 401fd378b4 rocketchip: include devices from cbus in ConfigString 2016-10-31 11:42:13 -07:00
Wesley W. Terpstra b68bc449e7 rocket: put a Fragmenter infront of the scratchpad 2016-10-31 11:42:13 -07:00
Wesley W. Terpstra a73aa351ca rocketchip: fix all clock crossings 2016-10-31 11:42:13 -07:00
Wesley W. Terpstra 825c253a72 rocketchip: move TL2 and cake pattern into Coreplex 2016-10-31 11:42:13 -07:00
Wesley W. Terpstra 89139a9492 Plic: split constants from variables used in config string 2016-10-31 11:42:13 -07:00
Wesley W. Terpstra 11121b6f4c rocket: convert scratchpad to TL2 2016-10-31 11:42:13 -07:00
Wesley W. Terpstra dddb50a942 BuildTiles: convert to LazyTile 2016-10-31 11:42:13 -07:00
Wesley W. Terpstra f8a0829134 rocketchip: remove clint; it moves into coreplex 2016-10-31 11:42:13 -07:00
Wesley W. Terpstra b99662796d PLIC: converted to TL2 2016-10-31 11:42:13 -07:00
Wesley W. Terpstra bddfa4d69b Debug: make address configurable 2016-10-31 11:42:13 -07:00
Wesley W. Terpstra c3dacca39a rocketchip: remove pbus; TL2 has swallowed it completely 2016-10-31 11:42:08 -07:00
Wesley W. Terpstra 3df797fcab rocketchip: replace TL1 MMIO with an example of TL2 MMIO 2016-10-31 11:41:18 -07:00
Wesley W. Terpstra 650f6fb23f diplomacy: add BlindNodes for use as external ports 2016-10-31 11:41:18 -07:00
Wesley W. Terpstra 0edcd3304a diplomacy Nodes: leave flipping to the MixedNode implementation 2016-10-31 11:41:18 -07:00
Wesley W. Terpstra 082f338432 diplomacy Nodes: remove useless indirection 2016-10-31 11:41:18 -07:00
Wesley W. Terpstra ec2d23b8b7 rocketchip: Bundle-slices need access to the outer LazyModule 
We need this change in order for some ports to use parameters that result
from LazyModule diplomacy.

Now you can eat your cake too!
 2016-10-31 11:41:18 -07:00
Wesley W. Terpstra 0ae45d0f24 rocketchip: bundle (=> B) need not be delayed; Module is constructed later 2016-10-31 11:41:18 -07:00
Wesley W. Terpstra 0dbda2f07d rocketchip: remove obsolete pDevices used during TL1=>2 migration 2016-10-31 11:41:18 -07:00
Wesley W. Terpstraandmwachs5 a807c922d0 diplomacy: take names from the outermost common node 2016-10-25 15:58:09 -07:00
Wesley W. Terpstraandmwachs5 fee67c4abf diplomacy: add methods to find {out,in}ner-most common node 2016-10-25 15:58:09 -07:00
Wesley W. Terpstraandmwachs5 67ab27f5a5 diplomacy: guess the LazyModule name from the containing class 2016-10-25 15:58:09 -07:00
Wesley W. TerpstraandGitHub 4d50733548 tilelink2 ToAXI4: use helper method for a_last (#418) 2016-10-25 10:16:42 -07:00
Wesley W. TerpstraandGitHub 7dc97674d6 rocketchip: include an socBus between l1tol2 and periphery (#415) 
Sometimes we have high performance devices that go inbetween.
 2016-10-24 23:56:09 -07:00
Wesley W. TerpstraandGitHub a5ac106bb8 axi4 ToTL: fix decode error arbitration (#417) 
When selecting between error generation on R and real data on R,
correctly calculate the R backpressure.

This bug manifests when a valid request is immediately followed by
an invalid request, wedging the R channel.
 2016-10-24 22:15:19 -07:00
Wesley W. TerpstraandGitHub 4c815f7958 tilelink2 Parameters: fix {contains,supports}Safe (#416) 
When there is only one manager, you still want to know if the address
was wrong on the link to that manager!
 2016-10-24 20:37:04 -07:00
Wesley W. TerpstraandGitHub 8bfd6bcd4d axi4: ensure we accept AR before reporting R (#411) 2016-10-21 21:02:05 -07:00
Wesley W. TerpstraandGitHub c8fc05d154 Merge pull request #402 from ucb-bar/axi4-slave 
AXI4=>TL2 converter
 2016-10-17 10:34:29 -07:00
Wesley W. Terpstra 7c334e3c34 axi4 ToTL: shorter critical path on Q.bits if errors go first 2016-10-17 01:00:49 -07:00
Wesley W. Terpstra 73010c79a3 axi4 ToTL: handle bad AXI addresses 2016-10-17 00:12:26 -07:00
Wesley W. Terpstra 501d6d689f axi4: Test ToTL 2016-10-16 22:04:06 -07:00
Wesley W. Terpstra 5a1da63b5a axi4: prototype ToTL adapter 2016-10-16 22:04:01 -07:00
Wesley W. Terpstra 72e5a97d40 tilelink2: factor out the OH1ToOH function 2016-10-16 22:04:01 -07:00