riscv/rocket-chip
1
0
Fork 0
Code Releases Activity

tilelink2 Filter: make transfer cap robust against large filters

Browse Source
This commit is contained in:
Wesley W. Terpstra 2016-11-04 12:08:56 -07:00 committed by Henry Cook
parent 4a2cf6431b
commit 9d77e34bee
1 changed files with 4 additions and 1 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

5
src/main/scala/uncore/tilelink2/Filter.scala
View File

@ -14,7 +14,10 @@ class TLFilter(select: AddressSet) extends LazyModule
managerFn = { case Seq(mp) =>
mp.copy(managers = mp.managers.map { m =>
val filtered = m.address.map(_.intersect(select)).flatten
val cap = TransferSizes(1, select.alignment.toInt)
val alignment = select.alignment /* alignment 0 means 'select' selected everything */
val maxTransfer = 1 << 30
val capTransfer = if (alignment == 0 || alignment > maxTransfer) maxTransfer else alignment.toInt
val cap = TransferSizes(1, capTransfer)
if (filtered.isEmpty) { None } else {
Some(m.copy(
address = filtered,