riscv/rocket-chip
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rocketchip: match simulated memory width to ExtMem.beatBytes

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This commit is contained in:
Wesley W. Terpstra 2016-11-17 15:38:11 -08:00
parent 12d0d8bea2
commit f4ca5ea1f3
8 changed files with 41 additions and 124 deletions
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4
src/main/scala/groundtest/BusMasterTest.scala
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@ -21,7 +21,7 @@ class ExampleBusMaster(implicit val p: Parameters) extends Module
with HasTileLinkParameters {
val mmioParams = p.alterPartial({ case TLId => p(InnerTLId) })
val memParams = p.alterPartial({ case TLId => p(OuterTLId) })
val memStart = p(ExtMemBase)
val memStart = p(ExtMem).base
val memStartBlock = memStart >> p(CacheBlockOffsetBits)
val io = new Bundle {
@ -70,7 +70,7 @@ class BusMasterTest(implicit p: Parameters) extends GroundTest()(p)
s_req_check :: s_resp_check :: s_done :: Nil) = Enum(Bits(), 8)
val state = Reg(init = s_idle)
val busMasterBlock = p(ExtBusBase) >> p(CacheBlockOffsetBits)
val busMasterBlock = p(ExtBus).base >> p(CacheBlockOffsetBits)
val start_acq = Put(
client_xact_id = UInt(0),
addr_block = UInt(busMasterBlock),

4
src/main/scala/groundtest/Configs.scala
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@ -106,7 +106,7 @@ class WithComparator extends Config(
case BuildGroundTest =>
(p: Parameters) => Module(new ComparatorCore()(p))
case ComparatorKey => ComparatorParameters(
targets = Seq(site(ExtMemBase), testRamAddr),
targets = Seq(site(ExtMem).base, testRamAddr),
width = 8,
operations = 1000,
atomics = site(UseAtomics),
@ -136,7 +136,7 @@ class WithMemtest extends Config(
}
case GeneratorKey => TrafficGeneratorParameters(
maxRequests = 128,
startAddress = BigInt(site(ExtMemBase)))
startAddress = BigInt(site(ExtMem).base))
case BuildGroundTest =>
(p: Parameters) => Module(new GeneratorTest()(p))
case _ => throw new CDEMatchError

2
src/main/scala/groundtest/Regression.scala
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@ -20,7 +20,7 @@ class RegressionIO(implicit val p: Parameters) extends ParameterizedBundle()(p)
abstract class Regression(implicit val p: Parameters)
extends Module with HasTileLinkParameters with HasAddrMapParameters {
val memStart = p(ExtMemBase)
val memStart = p(ExtMem).base
val memStartBlock = memStart >> p(CacheBlockOffsetBits)
val io = new RegressionIO

11
src/main/scala/groundtest/TestHarness.scala
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@ -16,15 +16,10 @@ class TestHarness(q: Parameters) extends Module {
io.success := dut.io.success
if (dut.io.mem_axi4.nonEmpty) {
val memSize = p(ExtMemSize)
val memSize = p(ExtMem).size
require(memSize % dut.io.mem_axi4.size == 0)
for (axi <- dut.io.mem_axi4.map(_(0))) {
val mem = Module(new SimAXIMem(memSize / dut.io.mem_axi4.size))
mem.io.axi.ar <> axi.ar
mem.io.axi.aw <> axi.aw
mem.io.axi.w <> axi.w
axi.r <> LatencyPipe(mem.io.axi.r, p(SimMemLatency))
axi.b <> LatencyPipe(mem.io.axi.b, p(SimMemLatency))
for (axi <- dut.io.mem_axi4) {
Module(LazyModule(new SimAXIMem(memSize / dut.io.mem_axi4.size)).module).io.axi <> axi
}
}
}

4
src/main/scala/groundtest/Tile.scala
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@ -5,7 +5,7 @@ import rocket._
import uncore.tilelink._
import uncore.agents.CacheName
import uncore.tilelink2._
import rocketchip.ExtMemBase
import rocketchip.ExtMem
import diplomacy._
import scala.util.Random
import scala.collection.mutable.ListBuffer
@ -30,7 +30,7 @@ trait HasGroundTestParameters {
val nUncached = tileSettings.uncached
val nCached = tileSettings.cached
val nPTW = tileSettings.ptw
val memStart = p(ExtMemBase)
val memStart = p(ExtMem).base
val memStartBlock = memStart >> p(CacheBlockOffsetBits)
}

29
src/main/scala/rocketchip/Configs.scala
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@ -23,16 +23,8 @@ class BasePlatformConfig extends Config(
(pname,site,here) => {
type PF = PartialFunction[Any,Any]
def findBy(sname:Any):Any = here[PF](site[Any](sname))(pname)
lazy val edgeDataBits = site(EdgeDataBits)
lazy val edgeDataBeats = (8 * site(CacheBlockBytes)) / edgeDataBits
pname match {
//Memory Parameters
case EdgeDataBits => 64
case EdgeIDBits => 5
case NastiKey => NastiParameters(
dataBits = edgeDataBits,
addrBits = site(PAddrBits),
idBits = site(EdgeIDBits))
case TLEmitMonitors => true
case NExtTopInterrupts => 2
case SOCBusConfig => site(L1toL2Config)
@ -40,23 +32,10 @@ class BasePlatformConfig extends Config(
case PeripheryBusArithmetic => true
// Note that PLIC asserts that this is > 0.
case IncludeJtagDTM => false
case NExtBusAXIChannels => 0
case HastiId => "Ext"
case HastiKey("TL") =>
HastiParameters(
addrBits = site(PAddrBits),
dataBits = site(TLKey(site(TLId))).dataBits / site(TLKey(site(TLId))).dataBeats)
case HastiKey("Ext") =>
HastiParameters(
addrBits = site(PAddrBits),
dataBits = edgeDataBits)
case NMemoryChannels => Dump("N_MEM_CHANNELS", 1)
case ExtMemBase => Dump("MEM_BASE", 0x80000000L)
case ExtMemSize => Dump("MEM_SIZE", 0x10000000L)
case ExtBusBase => 0x60000000L
case ExtBusSize => 0x20000000L
case ExtMem => AXIMasterConfig(0x80000000L, 0x10000000L, 8, 4)
case ExtBus => AXIMasterConfig(0x60000000L, 0x20000000L, 8, 4)
case RTCPeriod => 100 // gives 10 MHz RTC assuming 1 GHz uncore clock
case SimMemLatency => 0
case _ => throw new CDEMatchError
}
}
@ -91,7 +70,7 @@ class WithNMemoryChannels(n: Int) extends Config(
class WithExtMemSize(n: Long) extends Config(
(pname,site,here) => pname match {
case ExtMemSize => Dump("MEM_SIZE", n)
case ExtMem => site(ExtMem).copy(size = n)
case _ => throw new CDEMatchError
}
)
@ -122,7 +101,7 @@ class RoccExampleConfig extends Config(new WithRoccExample ++ new BaseConfig)
class WithEdgeDataBits(dataBits: Int) extends Config(
(pname, site, here) => pname match {
case EdgeDataBits => dataBits
case ExtMem => site(ExtMem).copy(beatBytes = dataBits/8)
case _ => throw new CDEMatchError
})

33
src/main/scala/rocketchip/Periphery.scala
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@ -19,13 +19,10 @@ import rocket.XLen
import scala.math.max
import coreplex._
/** External Bus controls */
case object NExtBusAXIChannels extends Field[Int]
/** Specifies the size of external memory */
case object ExtMemSize extends Field[Long]
case object ExtMemBase extends Field[Long]
case object ExtBusSize extends Field[Long]
case object ExtBusBase extends Field[Long]
case class AXIMasterConfig(base: Long, size: Long, beatBytes: Int, idBits: Int)
case object ExtMem extends Field[AXIMasterConfig]
case object ExtBus extends Field[AXIMasterConfig]
/** Specifies the number of external interrupts */
case object NExtTopInterrupts extends Field[Int]
/** Source of RTC. First bundle is TopIO.extra, Second bundle is periphery.io.extra **/
@ -36,10 +33,6 @@ case object PeripheryBusArithmetic extends Field[Boolean]
/* Specifies the SOC-bus configuration */
case object SOCBusConfig extends Field[TLBusConfig]
/* Specifies the data and id width at the chip boundary */
case object EdgeDataBits extends Field[Int]
case object EdgeIDBits extends Field[Int]
/** Utility trait for quick access to some relevant parameters */
trait HasPeripheryParameters {
implicit val p: Parameters
@ -81,13 +74,12 @@ trait PeripheryExtInterruptsModule {
trait PeripheryMasterAXI4Mem {
this: BaseTop[BaseCoreplex] with TopNetwork =>
val base = p(ExtMemBase)
val size = p(ExtMemSize)
val channels = coreplexMem.size
private val config = p(ExtMem)
private val channels = coreplexMem.size
val mem_axi4 = coreplexMem.zipWithIndex.map { case (node, i) =>
val c_size = size/channels
val c_base = base + c_size*i
val c_size = config.size/channels
val c_base = config.base + c_size*i
val axi4 = AXI4BlindOutputNode(AXI4SlavePortParameters(
slaves = Seq(AXI4SlaveParameters(
@ -97,11 +89,11 @@ trait PeripheryMasterAXI4Mem {
supportsWrite = TransferSizes(1, 256), // The slave supports 1-256 byte transfers
supportsRead = TransferSizes(1, 256),
interleavedId = Some(0))), // slave does not interleave read responses
beatBytes = 8)) // 64-bit AXI interface
beatBytes = config.beatBytes))
axi4 :=
// AXI4Fragmenter(lite=false, maxInFlight = 20)( // beef device up to support awlen = 0xff
TLToAXI4(idBits = 4)( // use idBits = 0 for AXI4-Lite
TLToAXI4(idBits = config.idBits)( // use idBits = 0 for AXI4-Lite
TLWidthWidget(coreplex.l1tol2_beatBytes)( // convert width before attaching to the l1tol2
node))
@ -129,18 +121,19 @@ trait PeripheryMasterAXI4MemModule {
trait PeripheryMasterAXI4MMIO {
this: TopNetwork =>
private val config = p(ExtBus)
val mmio_axi4 = AXI4BlindOutputNode(AXI4SlavePortParameters(
slaves = Seq(AXI4SlaveParameters(
address = List(AddressSet(BigInt(p(ExtBusBase)), p(ExtBusSize)-1)),
address = List(AddressSet(BigInt(config.base), config.size-1)),
executable = true, // Can we run programs on this memory?
supportsWrite = TransferSizes(1, 256), // The slave supports 1-256 byte transfers
supportsRead = TransferSizes(1, 256),
interleavedId = Some(0))), // slave does not interleave read responses
beatBytes = 8)) // 64-bit AXI interface
beatBytes = config.beatBytes))
mmio_axi4 :=
// AXI4Fragmenter(lite=false, maxInFlight = 20)( // beef device up to support awlen = 0xff
TLToAXI4(idBits = 4)( // use idBits = 0 for AXI4-Lite
TLToAXI4(idBits = config.idBits)( // use idBits = 0 for AXI4-Lite
TLWidthWidget(socBusConfig.beatBytes)( // convert width before attaching to socBus
socBus.node))
}

78
src/main/scala/rocketchip/TestHarness.scala
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@ -7,11 +7,9 @@ import cde.{Parameters, Field}
import junctions._
import diplomacy._
import coreplex._
import junctions.NastiConstants._
import util.LatencyPipe
import uncore.axi4._
case object BuildExampleTop extends Field[Parameters => ExampleTop[coreplex.BaseCoreplex]]
case object SimMemLatency extends Field[Int]
class TestHarness(q: Parameters) extends Module {
val io = new Bundle {
@ -24,79 +22,31 @@ class TestHarness(q: Parameters) extends Module {
int := Bool(false)
if (dut.io.mem_axi4.nonEmpty) {
val memSize = p(ExtMemSize)
val memSize = p(ExtMem).size
require(memSize % dut.io.mem_axi4.size == 0)
for (axi <- dut.io.mem_axi4.map(_(0))) {
val mem = Module(new SimAXIMem(memSize / dut.io.mem_axi4.size))
mem.io.axi.ar <> axi.ar
mem.io.axi.aw <> axi.aw
mem.io.axi.w <> axi.w
axi.r <> LatencyPipe(mem.io.axi.r, p(SimMemLatency))
axi.b <> LatencyPipe(mem.io.axi.b, p(SimMemLatency))
for (axi <- dut.io.mem_axi4) {
Module(LazyModule(new SimAXIMem(memSize / dut.io.mem_axi4.size)).module).io.axi <> axi
}
}
val dtm = Module(new SimDTM).connect(clock, reset, dut.io.debug, io.success)
for (mmio_axi <- dut.io.mmio_axi) {
val slave = Module(new NastiErrorSlave)
slave.io <> mmio_axi
}
val mmio_sim = Module(LazyModule(new SimAXIMem(4096)).module)
mmio_sim.io.axi <> dut.io.mmio_axi
}
class SimAXIMem(size: BigInt)(implicit p: Parameters) extends NastiModule()(p) {
val io = new Bundle {
val axi = new NastiIO().flip
}
class SimAXIMem(size: BigInt)(implicit p: Parameters) extends LazyModule {
val config = p(ExtMem)
val rValid = Reg(init = Bool(false))
val ar = RegEnable(io.axi.ar.bits, io.axi.ar.fire())
io.axi.ar.ready := !rValid
when (io.axi.ar.fire()) { rValid := Bool(true) }
when (io.axi.r.fire()) {
assert(ar.burst === NastiConstants.BURST_INCR)
ar.addr := ar.addr + (UInt(1) << ar.size)
ar.len := ar.len - UInt(1)
when (ar.len === UInt(0)) { rValid := Bool(false) }
}
val node = AXI4BlindInputNode(AXI4MasterPortParameters(Seq(AXI4MasterParameters(IdRange(0, 1 << config.idBits)))))
val sram = LazyModule(new AXI4RAM(AddressSet(0, size-1), beatBytes = config.beatBytes))
sram.node := AXI4Buffer()(AXI4Fragmenter(maxInFlight = 4)(node))
val w = io.axi.w.bits
require((size * 8) % nastiXDataBits == 0)
val depth = (size * 8) / nastiXDataBits
val mem = Mem(depth.toInt, w.data)
val wValid = Reg(init = Bool(false))
val bValid = Reg(init = Bool(false))
val aw = RegEnable(io.axi.aw.bits, io.axi.aw.fire())
io.axi.aw.ready := !wValid && !bValid
io.axi.w.ready := wValid
when (io.axi.b.fire()) { bValid := Bool(false) }
when (io.axi.aw.fire()) { wValid := Bool(true) }
when (io.axi.w.fire()) {
assert(aw.burst === NastiConstants.BURST_INCR)
aw.addr := aw.addr + (UInt(1) << aw.size)
aw.len := aw.len - UInt(1)
when (aw.len === UInt(0)) {
wValid := Bool(false)
bValid := Bool(true)
lazy val module = new LazyModuleImp(this) {
val io = new Bundle {
val axi = node.bundleIn
}
def row = mem((aw.addr >> log2Ceil(nastiXDataBits/8))(log2Ceil(depth)-1, 0))
val mask = FillInterleaved(8, w.strb)
val newData = mask & w.data | ~mask & row
row := newData
}
io.axi.b.valid := bValid
io.axi.b.bits.id := aw.id
io.axi.b.bits.resp := RESP_OKAY
io.axi.r.valid := rValid
io.axi.r.bits.id := ar.id
io.axi.r.bits.data := mem((ar.addr >> log2Ceil(nastiXDataBits/8))(log2Ceil(depth)-1, 0))
io.axi.r.bits.resp := RESP_OKAY
io.axi.r.bits.last := ar.len === UInt(0)
}
class SimDTM(implicit p: Parameters) extends BlackBox {