riscv/rocket-chip
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Author SHA1 Message Date
Yunsup Lee
02c08a156f generate consts.vh from chisel source 2014-09-10 17:14:55 -07:00
Yunsup Lee
cfecd8832d tease out reference-chip specific stuff 2014-09-09 20:49:28 -07:00
Yunsup Lee
6b6bdd2b83 decommission Slave top-level module for fpga build 2014-09-08 00:23:15 -07:00
Yunsup Lee
ddfd3ce968 further generalize fpga/vlsi builds 2014-09-08 00:21:57 -07:00
Yunsup Lee
3175a40509 add berkeley-hardfloat as submodule 2014-09-08 00:18:49 -07:00
Yunsup Lee
1e5b2f658f remove existing hardfloat repository 2014-09-07 23:45:47 -07:00
Henry Cook
ae05125f29 Adjustements to top-level parameters and knobs for hwacha 2014-09-07 17:57:33 -07:00
Henry Cook
4126678c9d Merge branch 'dse' 
Conflicts:
	rocket
	uncore
 2014-09-06 06:59:14 -07:00
Yunsup Lee
1cb2d1d7b7 initialize all SRAMs to avoid X propagation problem 2014-09-04 11:06:01 -07:00
Yunsup Lee
763c57931b fix problem introduced with verilog generation in vsim/fsim 2014-09-04 09:49:57 -07:00
Scott Beamer
6c6f5a3843 add verilog target to build without simulator 2014-09-03 17:28:45 -07:00
Scott Beamer
13b6ec4712 including better sbt fixes 2014-09-02 15:16:31 -07:00
Scott Beamer
26649b30ed fixes sbt error during first run 2014-09-02 14:34:55 -07:00
Henry Cook
82467313dd merge in rocketchip changes from master 2014-09-02 13:51:57 -07:00
Henry Cook
3250db0dd5 bump uncore 2014-09-02 12:37:44 -07:00
Henry Cook
8622eb0f5b bump rocket 2014-09-01 13:34:15 -07:00
Yunsup Lee
7734285507 forgot to comment out hwacha 2014-09-01 09:01:36 -07:00
Yunsup Lee
0d18e491c7 update gitignore 2014-09-01 08:59:59 -07:00
Yunsup Lee
882fecf43a update README 2014-08-31 20:57:16 -07:00
Yunsup Lee
c03c09ec31 update for rocket-chip release 2014-08-31 20:26:55 -07:00
Henry Cook
78ab83d224 refactor fpga top/config 2014-08-28 13:07:54 -07:00
Scott Beamer
83380053de use fpga backend for fpga 2014-08-26 15:56:27 -07:00
Henry Cook
bf356b9cb4 Refactor to combine fpga and vlsi tops, part 1 2014-08-24 19:30:53 -07:00
Henry Cook
a41d55b643 Final parameter refactor. 2014-08-23 01:26:03 -07:00
Scott Beamer
63b62394d9 added l2 to fpga 
with new chisel & uncore, it goes into brams
 2014-08-20 15:41:07 -07:00
Henry Cook
9b36162b67 Point rocket/ to rocket-staging repo 2014-08-19 14:20:15 -07:00
Henry Cook
2741bbf2b9 Point rocket/ to rocket-staging repo 2014-08-19 13:53:24 -07:00
Scott Beamer
e1a4d12c65 fix small typos in README 2014-08-14 17:59:24 -07:00
Henry Cook
1563c1bb36 Fixed cache params. Asm and bmark tests pass. 2014-08-12 15:00:54 -07:00
Henry Cook
910c886837 bump chisel 2014-08-12 14:53:19 -07:00
Henry Cook
74796868e7 chisel bump 2014-08-12 10:58:09 -07:00
Henry Cook
0ca24a5d91 fix debug flags 2014-08-12 10:35:39 -07:00
Henry Cook
7f07771600 Cache utility traits. Completely compiles, asm tests hang. 2014-08-11 18:37:10 -07:00
Henry Cook
1983260e6f a few more fixes. some param lookups fail (here() in Alter blocks) 2014-08-10 23:08:21 -07:00
Henry Cook
63bd0b9d2a Partial conversion to params. Compiles but does not elaborate. Rocket and uncore conversion complete. FPGA and VLSI config are identical. HwachaConfig and MemoryControllerConfig not yet removed. 2014-08-08 12:27:47 -07:00
Scott Beamer
d3a8a224fe README updated for new fpga flow 2014-08-07 14:52:56 -07:00
Scott Beamer
e390eba8ce convert README to markdown 2014-08-07 14:50:31 -07:00
Scott Beamer
4109d7cc87 newest version of chisel needed for brams 2014-08-07 13:49:31 -07:00
Palmer Dabbelt
0fc3acb978 Update the directions on how to update Chisel 
It seems that the update process in the README is really out of date
(it refers to scala-2.8 and chisel-1.1).  I've updated it to what I
believe to be correct, which now just consists of pulling the Chisel
submodule.

Note that I tried this myself, but when I did it I also ran an "sbt
package" in the Chisel submodule top-level directory (there's no "sbt"
directory in there any more).  I believe it's not necessary to run
"sbt package", but I really know nothing about SBT...
 2014-08-05 11:56:03 -07:00
Palmer Dabbelt
693489da87 Add a note to the README about "make emulator-debug" 
I made a clean checkout of reference-chip yesterday and wasn't able to
build the debug emulator without first having built the non-debug
emulator.  I just added a note to the README to say this.
 2014-08-05 11:53:55 -07:00
Adam Izraelevitz
08d81d0892 First cut at using new chisel parameters for toplevel parameters and fpu 2014-08-01 18:09:37 -07:00
Adam Izraelevitz
fcd68364ff Merge branch 'master' of github.com:ucb-bar/reference-chip into dse 
Conflicts:
	src/main/scala/ReferenceChip.scala
 2014-08-01 18:07:22 -07:00
Henry Cook
434da22283 Refactored Metadata, expanded coherence API (bump rocket, uncore, chisel) 2014-05-28 17:16:49 -07:00
Henry Cook
b0ccb88982 make outer cache type choice a top-level const 2014-05-28 14:46:07 -07:00
Stephen Twigg
d2a3b1dc20 Merge branch 'shapeanalysis' 2014-05-06 16:49:54 -07:00
Henry Cook
f8b3117ac0 bump rocket, uncore 2014-05-06 13:10:12 -07:00
Henry Cook
445d4f2eee bump rocket, uncore 2014-05-01 01:46:55 -07:00
Henry Cook
ce056b4b89 client/master -> inner/outer 2014-04-29 16:50:30 -07:00
Henry Cook
224e286dd3 New uncore config objects. Backends get their own file. Simplify fpga uncore. 2014-04-26 19:46:11 -07:00
Henry Cook
3d4273954a TileLinkIO.GrantAck -> TileLinkIO.Finish 2014-04-26 15:19:25 -07:00