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rocket-chip
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5632 Commits

Author SHA1 Message Date
Henry Cook 940027a888 Finished broadcast hub with split mem req types. Untested. 2012-02-29 17:58:15 -08:00
Henry Cook 813ffcbf3e Finished broadcast hub with split mem req types. Untested. 2012-02-29 17:58:15 -08:00
Yunsup Lee 4f00bcc760 Merge branch 'master' of github.com:ucb-bar/riscv-rocket 2012-02-29 17:12:02 -08:00
Yunsup Lee 7e6d990bad Merge branch 'master' of github.com:ucb-bar/riscv-rocket 2012-02-29 17:12:02 -08:00
Yunsup Lee 4939b72ba5 Merge branch 'master' of github.com:ucb-bar/riscv-rocket 2012-02-29 17:12:02 -08:00
Yunsup Lee 20d0088f66 temporary fix to match bit widths for Mem 2012-02-29 17:09:31 -08:00
Henry Cook 008ad1f45b Added 'locking' arbiter that won't rearbitrate until the lock signal on the current winning input is low 2012-02-29 17:05:06 -08:00
Henry Cook c723ef4c50 ioDecoupled now allows inner bundle to be used in covariant positions, i.e. it accepts subtypes 2012-02-29 16:46:16 -08:00
Andrew Waterman c38065d0e8 clean up priority encoders 2012-02-29 16:13:14 -08:00
Andrew Waterman b9ec69f8f5 add new Queue singleton 2012-02-29 14:21:42 -08:00
Andrew Waterman 8b519e7ea8 replace tile memory interface with ioTileLink 
work in progress towards coherent HTIF. for now, requests
are incoherently passed through a null coherence hub.
 2012-02-29 03:10:47 -08:00
Andrew Waterman 012da6002e replace tile memory interface with ioTileLink 
work in progress towards coherent HTIF. for now, requests
are incoherently passed through a null coherence hub.
 2012-02-29 03:10:47 -08:00
Henry Cook ef94f13087 Broadcast hub nears completion. Still does not handle generation/arbitration for decoupled mem reqs. 2012-02-29 02:59:27 -08:00
Henry Cook 082b38d315 Broadcast hub nears completion. Still does not handle generation/arbitration for decoupled mem reqs. 2012-02-29 02:59:27 -08:00
Henry Cook 6304aa992f Fixed race between read resps/reps and write req/reps in null hub 2012-02-29 00:44:03 -08:00
Henry Cook 8ff6e21e3a Fixed race between read resps/reps and write req/reps in null hub 2012-02-29 00:44:03 -08:00
Andrew Waterman eec369a1c7 separate memory request command and data 
also, merge some VLSI/C++ test harness functionality
 2012-02-28 19:06:23 -08:00
Andrew Waterman c99f6bbeb7 separate memory request command and data 
also, merge some VLSI/C++ test harness functionality
 2012-02-28 19:06:23 -08:00
Henry Cook e15284d22c Added temporary ioMemHub and made coherence hub implementations depend on it rather than ioMem 2012-02-28 17:33:32 -08:00
Henry Cook 040aa9fe02 Added temporary ioMemHub and made coherence hub implementations depend on it rather than ioMem 2012-02-28 17:33:32 -08:00
Daiwei Li 3f998b1353 send vcfg and setvl to vu prefetch queues 2012-02-28 14:54:48 -08:00
Henry Cook ffc7652e01 Null coherence hub. Begin work on internal tracker logic 2012-02-27 19:10:15 -08:00
Henry Cook 5cc10337b4 Null coherence hub. Begin work on internal tracker logic 2012-02-27 19:10:15 -08:00
Andrew Waterman 7d331858e2 replace ioDCache with ioMem 2012-02-27 18:36:09 -08:00
Andrew Waterman 2b1c07c723 replace ioDCache with ioMem 2012-02-27 18:36:09 -08:00
Andrew Waterman 1d41a41afa remove extraneous constants 2012-02-27 17:49:48 -08:00
Yunsup Lee 3d96a2d4f0 add fpu.dec.wen := false when HAVE_FPU is turned off 2012-02-27 14:00:58 -08:00
Henry Cook 3393dc2d31 Added probe_req ready sigs, GenArray to Vec 2012-02-27 11:26:18 -08:00
Henry Cook f0588a0052 Added probe_req ready sigs, GenArray to Vec 2012-02-27 11:26:18 -08:00
Henry Cook 70cdf869ac probe req transactors in coherence hub 2012-02-27 09:24:33 -08:00
Henry Cook 7a8f53a117 probe req transactors in coherence hub 2012-02-27 09:24:33 -08:00
Henry Cook b6e6d603cc xact init transactors in coherence hub 2012-02-27 09:24:32 -08:00
Henry Cook 2275239f33 xact init transactors in coherence hub 2012-02-27 09:24:32 -08:00
Yunsup Lee bfd0ae125e upgrade to new rocket/vu memory interface, fix amo nack bug in hellacache 2012-02-26 23:46:51 -08:00
Andrew Waterman 6e706c7c74 fix yet another AMO-related replay bug 2012-02-26 20:20:45 -08:00
Andrew Waterman e12b9eae93 remove ext_mem interface 
hindsight is 20/20
 2012-02-26 18:53:39 -08:00
Andrew Waterman 2d04664a98 simplify cpu-cache interface 2012-02-26 18:26:29 -08:00
Andrew Waterman ad713a5d83 fix icache ram depth; new chisel 2012-02-26 17:51:46 -08:00
Yunsup Lee f3bb02b2ea refactored dmem arbiter 2012-02-26 17:38:08 -08:00
Huy Vo 0fd777f480 Merge branch 'master' of github.com:ucb-bar/riscv-rocket 2012-02-26 17:24:23 -08:00
Huy Vo aa099a53fa Merge branch 'master' of github.com:ucb-bar/riscv-rocket 2012-02-26 17:24:23 -08:00
Huy Vo 93f41d3359 Merge branch 'master' of github.com:ucb-bar/riscv-rocket 2012-02-26 17:24:23 -08:00
Huy Vo e22106af3f updating rocket code to lastest version of chisel, passes assembly tests in C++ and Verilog as long as you dont use the vector unit 2012-02-26 17:24:08 -08:00
Huy Vo 5b0f7ccf68 updating rocket code to lastest version of chisel, passes assembly tests in C++ and Verilog as long as you dont use the vector unit 2012-02-26 17:24:08 -08:00
Yunsup Lee 766a039ffe small changes to the dtlb arbiter 2012-02-26 16:19:50 -08:00
Daiwei Li 69260756bd change ppn and vpn in dtlb from ufix to bits 2012-02-26 02:54:31 -08:00
Yunsup Lee 49efe4b744 now vu steals cycles from the fpu's fma alu 2012-02-26 01:55:07 -08:00
Daiwei Li 47dbc2a417 head should be working again 2012-02-26 00:30:50 -08:00
Daiwei Li 569698b824 dtlb now arbitrates between cpu, vec, and vec pf 2012-02-25 22:05:30 -08:00
Yunsup Lee ca2e70454e change package name and sbt project name to rocket 2012-02-25 17:09:26 -08:00