Finished broadcast hub with split mem req types. Untested.
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7e6d990bad
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940027a888
@ -28,8 +28,7 @@ class ioMem() extends Bundle
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}
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class HubMemReq extends Bundle {
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val req_cmd = (new ioDecoupled) { new MemReqCmd() }
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val req_data = (new ioDecoupled) { new MemData() }
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val lock = Bool()
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}
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class TrackerProbeData extends Bundle {
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@ -187,7 +186,9 @@ class XactTracker(id: Int) extends Component with CoherencePolicy {
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val p_rep_data = (new ioDecoupled) { new ProbeReplyData() }
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val x_init_data = (new ioDecoupled) { new TransactionInitData() }
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val mem_req = (new ioDecoupled) { new HubMemReq() }.flip
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val mem_req_cmd = (new ioDecoupled) { new MemReqCmd() }
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val mem_req_data = (new ioDecoupled) { new MemData() }
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val mem_req_lock = Bool(OUTPUT)
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val probe_req = (new ioDecoupled) { new ProbeRequest() }.flip
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val busy = Bool(OUTPUT)
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val addr = Bits(PADDR_BITS, OUTPUT)
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@ -225,14 +226,40 @@ class XactTracker(id: Int) extends Component with CoherencePolicy {
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val t_type_ = Reg{ Bits() }
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val init_tile_id_ = Reg{ Bits() }
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val tile_xact_id_ = Reg{ Bits() }
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val probe_done = Reg{ Bits() }
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val mem_count = Reg(resetVal = UFix(0, width = log2up(REFILL_CYCLES)))
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val p_rep_count = Reg(resetVal = UFix(0, width = log2up(NTILES)))
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val p_req_flags = Reg(resetVal = UFix(0, width = NTILES))
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val p_rep_tile_id_ = Reg{ Bits() }
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val x_needs_read = Reg{ Bool() }
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val x_init_data_needs_write = Reg{ Bool() }
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val p_rep_data_needs_write = Reg{ Bool() }
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val x_needs_read = Reg(resetVal = Bool(false))
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val x_init_data_needs_write = Reg(resetVal = Bool(false))
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val p_rep_data_needs_write = Reg(resetVal = Bool(false))
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val mem_cmd_sent = Reg(resetVal = Bool(false))
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val mem_cnt = Reg(resetVal = UFix(0, width = log2up(REFILL_CYCLES)))
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val mem_cnt_next = mem_cnt + UFix(1)
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def doMemReqWrite(req_cmd: ioDecoupled[MemReqCmd], req_data: ioDecoupled[MemData], lock: Bool, data: ioDecoupled[MemData], trigger: Bool, pop: Bool) {
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req_cmd.valid := mem_cmd_sent
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req_cmd.bits.rw := Bool(true)
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req_data <> data
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lock := Bool(true)
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when(req_cmd.ready && req_cmd.valid) {
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mem_cmd_sent := Bool(false)
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}
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when(req_data.ready && req_data.valid) {
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pop := Bool(true)
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mem_cnt := mem_cnt_next
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}
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when(mem_cnt === ~UFix(0)) {
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trigger := Bool(false)
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}
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}
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def doMemReqRead(req_cmd: ioDecoupled[MemReqCmd], trigger: Bool) {
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req_cmd.valid := Bool(true)
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req_cmd.bits.rw := Bool(false)
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when(req_cmd.ready ) {
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trigger := Bool(false)
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}
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}
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io.busy := state != s_idle
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io.addr := addr_
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@ -241,14 +268,13 @@ class XactTracker(id: Int) extends Component with CoherencePolicy {
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io.sharer_count := UFix(NTILES) // TODO: Broadcast only
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io.t_type := t_type_
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io.mem_req.valid := Bool(false)
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io.mem_req.bits.req_cmd.valid := Bool(false)
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io.mem_req.bits.req_cmd.bits.rw := Bool(false)
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io.mem_req.bits.req_cmd.bits.addr := addr_
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io.mem_req.bits.req_cmd.bits.tag := UFix(id)
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io.mem_req.bits.req_data.valid := Bool(false)
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io.mem_req.bits.req_data.bits.data := UFix(0)
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// := io.mem.ready //sent mem req
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io.mem_req_cmd.valid := Bool(false)
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io.mem_req_cmd.bits.rw := Bool(false)
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io.mem_req_cmd.bits.addr := addr_
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io.mem_req_cmd.bits.tag := UFix(id)
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io.mem_req_data.valid := Bool(false)
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io.mem_req_data.bits.data := UFix(0)
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io.mem_req_lock := Bool(false)
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io.probe_req.valid := Bool(false)
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io.probe_req.bits.p_type := sendProbeReqType(t_type_, UFix(0))
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io.probe_req.bits.global_xact_id := UFix(id)
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@ -269,9 +295,11 @@ class XactTracker(id: Int) extends Component with CoherencePolicy {
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tile_xact_id_ := io.alloc_req.bits.xact_init.tile_xact_id
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x_init_data_needs_write := io.alloc_req.bits.xact_init.has_data
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x_needs_read := needsMemRead(io.alloc_req.bits.xact_init.t_type, UFix(0))
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p_rep_count := UFix(NTILES)
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p_req_flags := ~Bits(0, width = NTILES)
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state := s_probe
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p_rep_count := UFix(NTILES-1)
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p_req_flags := ~( UFix(1) << io.alloc_req.bits.init_tile_id )
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state := Mux(p_req_flags.orR, s_probe, s_mem)
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mem_cnt := UFix(0)
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mem_cmd_sent := Bool(false)
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io.pop_x_init := Bool(true)
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}
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}
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@ -285,8 +313,11 @@ class XactTracker(id: Int) extends Component with CoherencePolicy {
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}
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when(io.p_rep_cnt_dec.orR) {
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val p_rep_count_next = p_rep_count - PopCount(io.p_rep_cnt_dec)
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io.pop_p_rep := io.p_rep_cnt_dec
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p_rep_count := p_rep_count_next
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when(p_rep_count_next === UFix(0)) {
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mem_cnt := UFix(0)
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mem_cmd_sent := Bool(false)
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state := s_mem
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}
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}
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@ -296,36 +327,12 @@ class XactTracker(id: Int) extends Component with CoherencePolicy {
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}
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}
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is(s_mem) {
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when(x_init_data_needs_write) {
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//io.mem_req.valid := //?TODO ??? || io.x_init_data.valid
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//io.mem_req.bits.req_cmd.valid := // TODO ???
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io.mem_req.bits.req_cmd.bits.rw := Bool(true)
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io.mem_req.bits.req_data <> io.x_init_data
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when(io.mem_req.ready && io.mem_req.bits.req_cmd.ready) {
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//TODO
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}
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when(io.mem_req.ready && io.mem_req.bits.req_data.ready) {
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io.pop_x_init_data := Bool(true)
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//TODO: count with mem_count somehow
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}
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} . elsewhen (p_rep_data_needs_write) {
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//io.mem_req.valid := //TODO ??? || io.p_rep_data.valid
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//io.mem_req.bits.req_cmd.valid := //TODO ???
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io.mem_req.bits.req_cmd.bits.rw := Bool(true)
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io.mem_req.bits.req_data <> io.p_rep_data
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when(io.mem_req.ready && io.mem_req.bits.req_cmd.ready) {
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//TODO
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}
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when(io.mem_req.ready && io.mem_req.bits.req_data.ready) {
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io.pop_p_rep_data := Bool(true)
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//TODO: count with mem_count somehow
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}
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when (p_rep_data_needs_write) {
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doMemReqWrite(io.mem_req_cmd, io.mem_req_data, io.mem_req_lock, io.p_rep_data, p_rep_data_needs_write, io.pop_p_rep_data)
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} . elsewhen(x_init_data_needs_write) {
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doMemReqWrite(io.mem_req_cmd, io.mem_req_data, io.mem_req_lock, io.x_init_data, x_init_data_needs_write, io.pop_x_init_data)
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} . elsewhen (x_needs_read) {
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io.mem_req.valid := Bool(true)
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io.mem_req.bits.req_cmd.valid := Bool(true)
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when(io.mem_req.ready && io.mem_req.bits.req_cmd.ready) {
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x_needs_read := Bool(false)
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}
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doMemReqRead(io.mem_req_cmd, x_needs_read)
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} . otherwise {
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io.send_x_rep_ack := needsAckRep(t_type_, UFix(0))
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state := s_busy
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@ -369,7 +376,7 @@ class CoherenceHubNull extends Component {
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}
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class CoherenceHubNoDir extends CoherenceHub {
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class CoherenceHubBroadcast extends CoherenceHub {
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def coherenceConflict(addr1: Bits, addr2: Bits): Bool = {
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addr1(PADDR_BITS-1, OFFSET_BITS) === addr2(PADDR_BITS-1, OFFSET_BITS)
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@ -440,14 +447,16 @@ class CoherenceHubNoDir extends CoherenceHub {
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// Create an arbiter for the one memory port
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// We have to arbitrate between the different trackers' memory requests
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// and once we have picked a request, get the right write data
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val mem_req_arb = (new Arbiter(NGLOBAL_XACTS)) { new HubMemReq() }
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val mem_req_cmd_arb = (new LockingArbiter(NGLOBAL_XACTS)) { new MemReqCmd() }
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val mem_req_data_arb = (new LockingArbiter(NGLOBAL_XACTS)) { new MemData() }
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for( i <- 0 until NGLOBAL_XACTS ) {
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mem_req_arb.io.in(i) <> trackerList(i).io.mem_req
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mem_req_cmd_arb.io.in(i) <> trackerList(i).io.mem_req_cmd
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mem_req_cmd_arb.io.lock(i) <> trackerList(i).io.mem_req_lock
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mem_req_data_arb.io.in(i) <> trackerList(i).io.mem_req_data
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mem_req_data_arb.io.lock(i) <> trackerList(i).io.mem_req_lock
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}
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//mem_req_arb.io.out.ready := io.mem.req_cmd.ready || io.mem.req_data.ready
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io.mem.req_cmd <> mem_req_arb.io.out.bits.req_cmd
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io.mem.req_data <> mem_req_arb.io.out.bits.req_data
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io.mem.req_cmd <> mem_req_cmd_arb.io.out
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io.mem.req_data <> mem_req_data_arb.io.out
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// Handle probe replies, which may or may not have data
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for( j <- 0 until NTILES ) {
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