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100 Commits

Author SHA1 Message Date
Yunsup Lee d6df479870 move 'include /Makefrag' out of top-level Makefrag 2015-07-14 16:13:32 -07:00
Henry Cook 407d8e473e first cut at parameter-based testing 2015-07-13 14:54:26 -07:00
Yunsup Lee 09e29e8fe0 add zscale 
only supports generating Verilog, which plugs into the fpga-spartan6 repository, for now
 2015-07-07 20:38:47 -07:00
Yunsup Lee e6a13cdeba New machine-mode timer facility 
Mirroring Andrew's commit to reference-chip
 2015-07-07 17:26:07 -07:00
Henry Cook 854fd64fba Added optional Makefile includes for private chip repos 2015-07-06 17:15:27 -07:00
Henry Cook d3ccec1044 Massive update containing several months of changes from the now-defunct private chip repo. 
* Adds support for a L2 cache with directory bits for tracking L1 coherence (DefaultL2Config), and new metadata-based coherence API.
* Additional tests.
* New virtual memory implementation, priviliged architecture (1.7), custom CSRs, FDivSqrt unit
* Updated TileLink protocol, NASTI protocol SHIMs.
* Lays groundwork for multiple top-level memory channels, superscalar fetch.
* Bump all submodules.
 2015-07-02 14:43:30 -07:00
Yunsup Lee 7a28d2b47c forgot to move more hwacha stuff out in rocket-chip 2014-09-25 15:34:18 -07:00
Yunsup Lee 275b72368b add CONFIG to the name of simulator executable 2014-09-11 22:11:58 -07:00
Yunsup Lee 086bb02c24 check RISCV envirnoment variable 2014-09-11 02:38:21 -07:00
Yunsup Lee 02c08a156f generate consts.vh from chisel source 2014-09-10 17:14:55 -07:00
Yunsup Lee cfecd8832d tease out reference-chip specific stuff 2014-09-09 20:49:28 -07:00
Yunsup Lee ddfd3ce968 further generalize fpga/vlsi builds 2014-09-08 00:21:57 -07:00
Henry Cook 82467313dd merge in rocketchip changes from master 2014-09-02 13:51:57 -07:00
Yunsup Lee c03c09ec31 update for rocket-chip release 2014-08-31 20:26:55 -07:00
Adam Izraelevitz fcd68364ff Merge branch 'master' of github.com:ucb-bar/reference-chip into dse 
Conflicts:
	src/main/scala/ReferenceChip.scala
 2014-08-01 18:07:22 -07:00
Henry Cook 1bf5439f0b include new mm test in benchmarks 2014-04-18 18:05:30 -07:00
Andrew Waterman f04bde75fb New FP encoding 2014-03-11 19:12:20 -07:00
Yunsup Lee 23045ec379 add hwacha vfmsv instructions, keepcfg bug fix, turn off secondary fconv 2014-03-02 03:38:06 -08:00
Yunsup Lee bcfcdefe88 update hwacha 2014-02-27 04:39:12 -08:00
Yunsup Lee 46714c0c60 more improvements to hwacha 2014-02-26 21:20:53 -08:00
Yunsup Lee a5625de3d5 support vector irq tests 2014-02-25 21:18:03 -08:00
Yunsup Lee e5c2bd5e7b add extensions option to riscv-dis for better disassembly 2014-02-25 03:50:32 -08:00
Adam Izraelevitz 58d2e62e3f Merge branch 'master' of github.com:ucb-bar/reference-chip into dse 
Conflicts:
	chisel
	src/main/scala/ReferenceChip.scala
 2014-02-19 14:24:36 -08:00
Stephen Twigg 6808245bb5 Timeout cycles now defined in toplevel Makefrag in order to allow for easier alteration when debugging. 2014-02-12 16:50:13 -08:00
Adam Izraelevitz 548cf16061 Added jack Makefile and hammer.scala, as well as changed reference chip to have multiple datacache sizes. Requires chisel branch dse 2014-02-11 14:36:47 -08:00
Yunsup Lee dbeadba2dc add vfmvv 2014-02-05 03:28:33 -08:00
Stephen Twigg 8c96e27ca6 Merge branch 'master' into hwacha-port 
Mostly Stable version that is passing tests
 2014-02-04 17:20:28 -08:00
Andrew Waterman e9d3a650a4 Speed up C++ compilation 2014-01-31 12:25:19 -08:00
Andrew Waterman b6c6bddb62 Add full CSRRx support and an asm test 2014-01-21 16:20:24 -08:00
Yunsup Lee 5642194834 push hwacha to consistent state 2013-11-20 16:44:33 -08:00
Stephen Twigg a870f51300 Add some vector tests 2013-11-14 15:56:25 -08:00
Andrew Waterman 628745226c Use spike disassembler riscv-dis if it exists 2013-09-15 04:25:53 -07:00
Andrew Waterman fbdbb01232 update to new isa; disable vector tests 2013-09-12 17:04:03 -07:00
Henry Cook b06d33da2f Canonicalized sbt, updated makefiles, cleaned up submodules, minor bugfixes 2013-08-19 19:54:41 -07:00
Henry Cook 896179cbb6 removed bad mt test 2013-06-14 00:14:18 -07:00
Henry Cook 85fbb650c9 makefile support for new multithreading tests 2013-06-13 15:34:54 -07:00
Yunsup Lee a86ad08c1e commit awesome vlsi/energy scripts 2013-05-01 02:59:11 -07:00
Yunsup Lee a2f584e928 add riscv-tests, get rid of riscv-asmtests-bmarks 2013-04-29 19:29:51 -07:00
Yunsup Lee 9114012def assmebly tests are now built from riscv-tests 2013-04-24 01:59:14 -07:00
Andrew Waterman 7f5282d355 replace RDNPC with AUIPC 2013-04-22 04:21:46 -07:00
Andrew Waterman 7ea782fd22 add LR/SC 2013-04-07 19:36:15 -07:00
Andrew Waterman ef4927c9ad use a named pipe for VCD -> VPD conversion 2013-03-25 16:19:19 -07:00
Yunsup Lee bc140ce9bc add vec_{vvadd,cmplxmult,matmul} bmarks 2013-03-19 00:43:51 -07:00
Andrew Waterman d911e635d6 simplify c++ memory models; support +dramsim flag 
works for both vlsi and emulator
 2012-12-04 07:04:26 -08:00
Andrew Waterman 7330deb13a print stack trace if elaboration fails 2012-11-20 05:39:48 -08:00
Andrew Waterman 4ed2d614a2 update to new rocket; retime fpu in dc-syn 2012-11-04 16:43:02 -08:00
Andrew Waterman 367b5489d1 first crack at continuous compilation/testing flow 
try it out: cd emulator; make test
 2012-10-19 04:09:07 -07:00
Andrew Waterman edf0eeed01 integrate updated rocket/uncore 2012-10-18 17:51:41 -07:00
Yunsup Lee 34da073077 fix tab 2012-10-11 12:09:49 -07:00
Huy Vo 93a0182b96 everything to get emulator working 2012-10-01 19:30:11 -07:00