2014-09-13 00:31:38 +02:00
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// See LICENSE for license details.
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2012-09-27 21:59:45 +02:00
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package uncore
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2012-04-03 21:03:05 +02:00
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import Chisel._
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2014-08-08 21:21:57 +02:00
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case object NReleaseTransactors extends Field[Int]
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2014-12-16 04:23:13 +01:00
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case object NProbeTransactors extends Field[Int]
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2014-08-08 21:21:57 +02:00
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case object NAcquireTransactors extends Field[Int]
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2014-04-27 04:11:36 +02:00
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2015-03-01 02:02:13 +01:00
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trait CoherenceAgentParameters extends UsesParameters {
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2014-11-12 21:55:07 +01:00
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val nReleaseTransactors = 1
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2014-08-12 03:35:49 +02:00
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val nAcquireTransactors = params(NAcquireTransactors)
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val nTransactors = nReleaseTransactors + nAcquireTransactors
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2015-03-01 02:02:13 +01:00
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def outerTLParams = params.alterPartial({ case TLId => params(OuterTLId)})
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val outerDataBeats = outerTLParams(TLDataBeats)
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val outerDataBits = outerTLParams(TLDataBits)
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2015-03-11 23:43:41 +01:00
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val outerBeatAddrBits = log2Up(outerDataBeats)
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val outerByteAddrBits = log2Up(outerDataBits/8)
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2015-03-01 02:02:13 +01:00
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def innerTLParams = params.alterPartial({case TLId => params(InnerTLId)})
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val innerDataBeats = innerTLParams(TLDataBeats)
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val innerDataBits = innerTLParams(TLDataBits)
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val innerBeatAddrBits = log2Up(innerDataBeats)
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val innerByteAddrBits = log2Up(innerDataBits/8)
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require(outerDataBeats == innerDataBeats) //TODO: must fix all xact_data Vecs to remove this requirement
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2014-08-12 03:35:49 +02:00
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}
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2015-04-20 07:06:44 +02:00
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2015-03-01 02:02:13 +01:00
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abstract class CoherenceAgentBundle extends Bundle with CoherenceAgentParameters
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abstract class CoherenceAgentModule extends Module with CoherenceAgentParameters
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trait HasCoherenceAgentWiringHelpers {
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2015-04-18 01:55:20 +02:00
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def doOutputArbitration[T <: TileLinkChannel](
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out: DecoupledIO[T],
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ins: Seq[DecoupledIO[T]]) {
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def lock(o: T) = o.hasMultibeatData()
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val arb = Module(new LockingRRArbiter(out.bits.clone, ins.size, out.bits.tlDataBeats, lock _))
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2015-03-01 02:02:13 +01:00
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out <> arb.io.out
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2015-04-18 01:55:20 +02:00
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arb.io.in <> ins
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2014-12-12 10:11:08 +01:00
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}
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2013-01-17 08:57:35 +01:00
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2015-03-01 02:02:13 +01:00
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def doInputRouting[T <: HasManagerTransactionId](
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2015-04-18 01:55:20 +02:00
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in: DecoupledIO[T],
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outs: Seq[DecoupledIO[T]]) {
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val idx = in.bits.manager_xact_id
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2015-03-01 02:02:13 +01:00
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outs.map(_.bits := in.bits)
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outs.zipWithIndex.map { case (o,i) => o.valid := in.valid && idx === UInt(i) }
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in.ready := Vec(outs.map(_.ready)).read(idx)
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2014-11-12 21:55:07 +01:00
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}
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2013-01-17 08:57:35 +01:00
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}
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2015-03-01 02:02:13 +01:00
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trait HasInnerTLIO extends CoherenceAgentBundle {
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2015-04-18 01:55:20 +02:00
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val inner = Bundle(new ManagerTileLinkIO)(innerTLParams)
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2015-04-20 07:06:44 +02:00
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val incoherent = Vec.fill(inner.tlNCachingClients){Bool()}.asInput
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2015-04-18 01:55:20 +02:00
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def iacq(dummy: Int = 0) = inner.acquire.bits
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def iprb(dummy: Int = 0) = inner.probe.bits
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def irel(dummy: Int = 0) = inner.release.bits
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def ignt(dummy: Int = 0) = inner.grant.bits
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def ifin(dummy: Int = 0) = inner.finish.bits
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2013-01-29 01:39:45 +01:00
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}
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2015-03-01 02:02:13 +01:00
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trait HasUncachedOuterTLIO extends CoherenceAgentBundle {
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2015-04-18 01:55:20 +02:00
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val outer = Bundle(new ClientUncachedTileLinkIO)(outerTLParams)
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2015-03-24 10:06:53 +01:00
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def oacq(dummy: Int = 0) = outer.acquire.bits
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def ognt(dummy: Int = 0) = outer.grant.bits
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2013-01-29 01:39:45 +01:00
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}
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2013-01-17 08:57:35 +01:00
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2015-03-01 02:02:13 +01:00
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trait HasCachedOuterTLIO extends CoherenceAgentBundle {
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2015-04-18 01:55:20 +02:00
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val outer = Bundle(new ClientTileLinkIO)(outerTLParams)
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2015-03-24 10:06:53 +01:00
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def oacq(dummy: Int = 0) = outer.acquire.bits
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def oprb(dummy: Int = 0) = outer.probe.bits
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def orel(dummy: Int = 0) = outer.release.bits
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def ognt(dummy: Int = 0) = outer.grant.bits
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2015-03-01 02:02:13 +01:00
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}
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2014-03-29 18:53:49 +01:00
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2015-03-01 02:02:13 +01:00
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class ManagerTLIO extends HasInnerTLIO with HasUncachedOuterTLIO
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2013-01-17 08:57:35 +01:00
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2015-03-01 02:02:13 +01:00
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abstract class CoherenceAgent extends CoherenceAgentModule {
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2015-04-18 01:55:20 +02:00
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def innerTL: ManagerTileLinkIO
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def outerTL: ClientTileLinkIO
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2015-03-01 02:02:13 +01:00
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def incoherent: Vec[Bool]
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}
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2014-12-12 10:11:08 +01:00
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2015-03-01 02:02:13 +01:00
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abstract class ManagerCoherenceAgent extends CoherenceAgent
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with HasCoherenceAgentWiringHelpers {
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val io = new ManagerTLIO
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def innerTL = io.inner
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def outerTL = TileLinkIOWrapper(io.outer, outerTLParams)
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def incoherent = io.incoherent
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}
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2014-03-29 18:53:49 +01:00
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2015-03-01 02:02:13 +01:00
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class HierarchicalTLIO extends HasInnerTLIO with HasCachedOuterTLIO
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2014-03-29 18:53:49 +01:00
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2015-03-01 02:02:13 +01:00
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abstract class HierarchicalCoherenceAgent extends CoherenceAgent {
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val io = new HierarchicalTLIO
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def innerTL = io.inner
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def outerTL = io.outer
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def incoherent = io.incoherent
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}
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2014-03-29 18:53:49 +01:00
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2015-03-01 02:02:13 +01:00
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trait HasTrackerConflictIO extends Bundle {
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val has_acquire_conflict = Bool(OUTPUT)
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val has_acquire_match = Bool(OUTPUT)
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val has_release_match = Bool(OUTPUT)
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}
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2014-03-29 18:53:49 +01:00
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2015-03-01 02:02:13 +01:00
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class ManagerXactTrackerIO extends ManagerTLIO with HasTrackerConflictIO
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class HierarchicalXactTrackerIO extends HierarchicalTLIO with HasTrackerConflictIO
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2013-01-17 08:57:35 +01:00
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2015-04-18 01:55:20 +02:00
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abstract class XactTracker extends CoherenceAgentModule with HasDataBeatCounters {
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2015-04-04 02:24:44 +02:00
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def addPendingBitWhenBeat[T <: HasBeat](inc: Bool, in: T): UInt =
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Fill(in.tlDataBeats, inc) & UIntToOH(in.addr_beat)
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def dropPendingBitWhenBeat[T <: HasBeat](dec: Bool, in: T): UInt =
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~Fill(in.tlDataBeats, dec) | ~UIntToOH(in.addr_beat)
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2015-03-24 10:06:53 +01:00
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2015-04-18 01:55:20 +02:00
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def addPendingBitWhenBeatHasData[T <: HasBeat](in: DecoupledIO[T]): UInt =
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addPendingBitWhenBeat(in.fire() && in.bits.hasData(), in.bits)
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2015-03-18 01:51:00 +01:00
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2015-05-13 02:14:06 +02:00
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def addPendingBitWhenBeatHasDataAndAllocs(in: DecoupledIO[AcquireFromSrc]): UInt =
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addPendingBitWhenBeat(in.fire() && in.bits.hasData() && in.bits.allocate(), in.bits)
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2015-04-18 01:55:20 +02:00
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def addPendingBitWhenBeatIsGetOrAtomic(in: DecoupledIO[AcquireFromSrc]): UInt = {
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val a = in.bits
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2015-03-24 10:06:53 +01:00
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val isGetOrAtomic = a.isBuiltInType() &&
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2015-04-18 01:55:20 +02:00
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(Vec(Acquire.getType, Acquire.getBlockType, Acquire.putAtomicType).contains(a.a_type))
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addPendingBitWhenBeat(in.fire() && isGetOrAtomic, a)
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2015-03-18 01:51:00 +01:00
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}
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2015-03-18 04:28:06 +01:00
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2015-04-18 01:55:20 +02:00
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def dropPendingBitWhenBeatHasData[T <: HasBeat](in: DecoupledIO[T]): UInt =
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dropPendingBitWhenBeat(in.fire() && in.bits.hasData(), in.bits)
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2015-03-19 01:55:05 +01:00
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2015-04-18 01:55:20 +02:00
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def dropPendingBitAtDest(in: DecoupledIO[ProbeToDst]): UInt =
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2015-04-20 07:06:44 +02:00
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~Fill(in.bits.tlNCachingClients, in.fire()) | ~UIntToOH(in.bits.client_id)
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2013-01-17 08:57:35 +01:00
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}
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