2014-09-13 00:31:38 +02:00
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// See LICENSE for license details.
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2012-09-27 21:59:45 +02:00
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package uncore
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2012-04-03 21:03:05 +02:00
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import Chisel._
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2014-08-08 21:21:57 +02:00
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case object NReleaseTransactors extends Field[Int]
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2014-12-16 04:23:13 +01:00
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case object NProbeTransactors extends Field[Int]
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2014-08-08 21:21:57 +02:00
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case object NAcquireTransactors extends Field[Int]
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2014-12-16 04:23:13 +01:00
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case object NIncoherentClients extends Field[Int]
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case object NCoherentClients extends Field[Int]
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2014-11-12 21:55:07 +01:00
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case object L2StoreDataQueueDepth extends Field[Int]
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2014-12-16 04:23:13 +01:00
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case object L2CoherencePolicy extends Field[DirectoryRepresentation => CoherencePolicy]
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case object L2DirectoryRepresentation extends Field[DirectoryRepresentation]
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2014-04-27 04:11:36 +02:00
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2014-12-07 12:02:20 +01:00
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abstract trait CoherenceAgentParameters extends UsesParameters
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with TileLinkParameters {
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2014-11-12 21:55:07 +01:00
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val nReleaseTransactors = 1
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2014-08-12 03:35:49 +02:00
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val nAcquireTransactors = params(NAcquireTransactors)
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val nTransactors = nReleaseTransactors + nAcquireTransactors
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2014-12-16 04:23:13 +01:00
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val nCoherentClients = params(NCoherentClients)
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val nIncoherentClients = params(NIncoherentClients)
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val nClients = nCoherentClients + nIncoherentClients
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2014-12-07 12:02:20 +01:00
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val sdqDepth = params(L2StoreDataQueueDepth)*tlDataBeats
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2014-12-12 10:11:08 +01:00
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val dqIdxBits = math.max(log2Up(nReleaseTransactors) + 1, log2Up(sdqDepth))
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2014-12-07 12:02:20 +01:00
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val nDataQueueLocations = 3 //Stores, VoluntaryWBs, Releases
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2014-08-12 03:35:49 +02:00
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}
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2014-12-07 12:02:20 +01:00
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class DataQueueLocation extends Bundle with CoherenceAgentParameters {
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val idx = UInt(width = dqIdxBits)
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val loc = UInt(width = log2Ceil(nDataQueueLocations))
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}
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object DataQueueLocation {
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def apply(idx: UInt, loc: UInt) = {
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val d = new DataQueueLocation
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d.idx := idx
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d.loc := loc
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d
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}
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}
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2014-12-12 10:11:08 +01:00
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abstract class CoherenceAgent(innerId: String, outerId: String) extends Module
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with CoherenceAgentParameters {
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val io = new Bundle {
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val inner = Bundle(new TileLinkIO, {case TLId => innerId}).flip
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val outer = Bundle(new UncachedTileLinkIO, {case TLId => outerId})
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val incoherent = Vec.fill(nClients){Bool()}.asInput
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}
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}
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2014-12-16 04:23:13 +01:00
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class L2BroadcastHub(bankId: Int, innerId: String, outerId: String) extends
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2014-09-24 20:14:36 +02:00
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CoherenceAgent(innerId, outerId) {
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2013-08-02 23:55:06 +02:00
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2014-12-07 12:02:20 +01:00
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val internalDataBits = new DataQueueLocation().getWidth
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val inStoreQueue :: inVolWBQueue :: inClientReleaseQueue :: Nil = Enum(UInt(), nDataQueueLocations)
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2014-11-12 21:55:07 +01:00
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2013-08-02 23:55:06 +02:00
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// Create SHRs for outstanding transactions
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2014-08-12 03:35:49 +02:00
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val trackerList = (0 until nReleaseTransactors).map(id =>
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2014-12-07 12:02:20 +01:00
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Module(new VoluntaryReleaseTracker(id, bankId, innerId, outerId), {case TLDataBits => internalDataBits})) ++
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2014-08-12 03:35:49 +02:00
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(nReleaseTransactors until nTransactors).map(id =>
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2014-12-07 12:02:20 +01:00
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Module(new AcquireTracker(id, bankId, innerId, outerId), {case TLDataBits => internalDataBits}))
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2013-01-17 08:57:35 +01:00
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2013-08-02 23:55:06 +02:00
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// Propagate incoherence flags
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2013-03-20 22:10:16 +01:00
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trackerList.map(_.io.tile_incoherent := io.incoherent.toBits)
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2013-01-17 08:57:35 +01:00
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2014-12-07 12:02:20 +01:00
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// Queue to store impending UncachedWrite data
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2014-04-30 01:49:18 +02:00
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val acquire = io.inner.acquire
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2014-12-07 12:02:20 +01:00
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val sdq_val = Reg(init=Bits(0, sdqDepth))
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val sdq_alloc_id = PriorityEncoder(~sdq_val)
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val sdq_rdy = !sdq_val.andR
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2015-02-02 04:57:53 +01:00
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val sdq_enq = acquire.fire() && acquire.bits.payload.hasData()
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2014-12-07 12:02:20 +01:00
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val sdq = Vec.fill(sdqDepth){ Reg(io.inner.acquire.bits.payload.data) }
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when (sdq_enq) { sdq(sdq_alloc_id) := acquire.bits.payload.data }
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// Handle acquire transaction initiation
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2013-01-29 01:39:45 +01:00
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val any_acquire_conflict = trackerList.map(_.io.has_acquire_conflict).reduce(_||_)
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2013-04-10 22:46:31 +02:00
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val block_acquires = any_acquire_conflict
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2013-08-12 19:36:44 +02:00
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val alloc_arb = Module(new Arbiter(Bool(), trackerList.size))
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2013-03-20 22:10:16 +01:00
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for( i <- 0 until trackerList.size ) {
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2014-04-30 01:49:18 +02:00
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val t = trackerList(i).io.inner
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2014-03-29 18:53:49 +01:00
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alloc_arb.io.in(i).valid := t.acquire.ready
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t.acquire.bits := acquire.bits
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2014-12-07 12:02:20 +01:00
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t.acquire.bits.payload.data := DataQueueLocation(sdq_alloc_id, inStoreQueue).toBits
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2014-03-29 18:53:49 +01:00
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t.acquire.valid := alloc_arb.io.in(i).ready
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2013-01-17 08:57:35 +01:00
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}
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2014-11-12 21:55:07 +01:00
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acquire.ready := trackerList.map(_.io.inner.acquire.ready).reduce(_||_) && sdq_rdy && !block_acquires
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alloc_arb.io.out.ready := acquire.valid && sdq_rdy && !block_acquires
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2013-01-17 08:57:35 +01:00
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2014-12-07 12:02:20 +01:00
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// Queue to store impending Voluntary Release data
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2014-04-30 01:49:18 +02:00
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val release = io.inner.release
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2015-02-02 04:57:53 +01:00
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val voluntary = release.bits.payload.isVoluntary()
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val vwbdq_enq = release.fire() && voluntary && release.bits.payload.hasData()
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2014-12-07 12:02:20 +01:00
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val (rel_data_cnt, rel_data_done) = Counter(vwbdq_enq, tlDataBeats) //TODO Zero width
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val vwbdq = Vec.fill(tlDataBeats){ Reg(release.bits.payload.data) } //TODO Assumes nReleaseTransactors == 1
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when(vwbdq_enq) { vwbdq(rel_data_cnt) := release.bits.payload.data }
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// Handle releases, which might be voluntary and might have data
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2014-12-19 02:12:29 +01:00
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val release_idx = Vec(trackerList.map(_.io.has_release_match)).indexWhere{b: Bool => b}
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2013-03-20 22:10:16 +01:00
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for( i <- 0 until trackerList.size ) {
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2014-04-30 01:49:18 +02:00
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val t = trackerList(i).io.inner
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2014-03-29 18:53:49 +01:00
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t.release.bits := release.bits
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2014-12-07 12:02:20 +01:00
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t.release.bits.payload.data := (if (i < nReleaseTransactors)
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DataQueueLocation(rel_data_cnt, inVolWBQueue)
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else DataQueueLocation(UInt(0), inClientReleaseQueue)).toBits
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2014-12-19 02:12:29 +01:00
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t.release.valid := release.valid && (release_idx === UInt(i))
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2013-01-17 08:57:35 +01:00
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}
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2014-12-19 02:12:29 +01:00
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release.ready := Vec(trackerList.map(_.io.inner.release.ready)).read(release_idx)
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2013-01-17 08:57:35 +01:00
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2014-12-12 10:11:08 +01:00
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// Wire finished transaction acks
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val ack = io.inner.finish
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trackerList.map(_.io.inner.finish.valid := ack.valid)
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trackerList.map(_.io.inner.finish.bits := ack.bits)
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ack.ready := Bool(true)
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2014-12-07 12:02:20 +01:00
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// Wire probe requests to clients
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val probe_arb = Module(new Arbiter(new LogicalNetworkIO(new Probe), trackerList.size))
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io.inner.probe <> probe_arb.io.out
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probe_arb.io.in zip trackerList map { case (arb, t) => arb <> t.io.inner.probe }
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2014-11-12 21:55:07 +01:00
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2014-12-07 12:02:20 +01:00
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// Wire grant reply to initiating client
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2015-02-02 04:57:53 +01:00
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def hasData(m: LogicalNetworkIO[Grant]) = m.payload.hasMultibeatData()
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2014-12-07 12:02:20 +01:00
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val grant_arb = Module(new LockingArbiter(new LogicalNetworkIO(new Grant), trackerList.size, tlDataBeats, Some(hasData _)))
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2014-11-12 21:55:07 +01:00
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io.inner.grant.bits.payload.data := io.outer.grant.bits.payload.data
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2015-02-02 04:57:53 +01:00
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io.inner.grant.bits.payload.addr_beat := io.outer.grant.bits.payload.addr_beat
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2014-04-30 01:49:18 +02:00
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io.inner.grant <> grant_arb.io.out
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grant_arb.io.in zip trackerList map { case (arb, t) => arb <> t.io.inner.grant }
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2013-01-17 08:57:35 +01:00
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// Create an arbiter for the one memory port
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2014-09-24 20:14:36 +02:00
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val outer_arb = Module(new UncachedTileLinkIOArbiterThatPassesId(trackerList.size),
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2014-12-07 12:02:20 +01:00
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{ case TLId => outerId; case TLDataBits => internalDataBits })
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2014-04-30 01:49:18 +02:00
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outer_arb.io.in zip trackerList map { case(arb, t) => arb <> t.io.outer }
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2014-12-07 12:02:20 +01:00
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val outer_data_ptr = new DataQueueLocation().fromBits(outer_arb.io.out.acquire.bits.payload.data)
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val is_in_sdq = outer_data_ptr.loc === inStoreQueue
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val free_sdq = io.outer.acquire.fire() &&
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2015-02-02 04:57:53 +01:00
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io.outer.acquire.bits.payload.hasData() &&
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2014-12-07 12:02:20 +01:00
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outer_data_ptr.loc === inStoreQueue
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io.outer.acquire.bits.payload.data := MuxLookup(outer_data_ptr.loc, release.bits.payload.data, Array(
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inStoreQueue -> sdq(outer_data_ptr.idx),
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inVolWBQueue -> vwbdq(outer_data_ptr.idx)))
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2014-04-30 01:49:18 +02:00
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io.outer <> outer_arb.io.out
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2014-11-12 21:55:07 +01:00
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// Update SDQ valid bits
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when (io.outer.acquire.valid || sdq_enq) {
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2014-12-07 12:02:20 +01:00
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sdq_val := sdq_val & ~(UIntToOH(outer_data_ptr.idx) & Fill(sdqDepth, free_sdq)) |
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2014-11-12 21:55:07 +01:00
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PriorityEncoderOH(~sdq_val(sdqDepth-1,0)) & Fill(sdqDepth, sdq_enq)
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}
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2013-01-17 08:57:35 +01:00
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}
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2013-01-29 01:39:45 +01:00
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2014-09-24 20:14:36 +02:00
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abstract class XactTracker(innerId: String, outerId: String) extends Module {
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2014-12-16 04:23:13 +01:00
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val (co, tlDataBeats) = (params(TLCoherence), params(TLDataBeats))
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val nClients = params(NCoherentClients) + params(NIncoherentClients)
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2013-01-17 08:57:35 +01:00
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val io = new Bundle {
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2014-09-24 20:14:36 +02:00
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val inner = Bundle(new TileLinkIO, {case TLId => innerId}).flip
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val outer = Bundle(new UncachedTileLinkIO, {case TLId => outerId})
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2014-12-16 04:23:13 +01:00
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val tile_incoherent = Bits(INPUT, nClients)
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2013-03-20 22:10:16 +01:00
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val has_acquire_conflict = Bool(OUTPUT)
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2014-12-19 02:12:29 +01:00
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val has_release_match = Bool(OUTPUT)
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2013-01-29 01:39:45 +01:00
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}
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2014-03-29 18:53:49 +01:00
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2015-02-02 04:57:53 +01:00
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val cacq = io.inner.acquire.bits
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val crel = io.inner.release.bits
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val cgnt = io.inner.grant.bits
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val cfin = io.inner.finish.bits
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val macq = io.outer.acquire.bits
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val mgnt = io.outer.grant.bits
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2014-12-07 12:02:20 +01:00
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2013-01-29 01:39:45 +01:00
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}
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2014-09-24 20:14:36 +02:00
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class VoluntaryReleaseTracker(trackerId: Int, bankId: Int, innerId: String, outerId: String) extends XactTracker(innerId, outerId) {
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2015-02-02 04:57:53 +01:00
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val s_idle :: s_outer :: s_grant :: s_ack :: Nil = Enum(UInt(), 4)
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2013-08-16 00:27:38 +02:00
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val state = Reg(init=s_idle)
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2014-12-12 10:11:08 +01:00
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val xact_src = Reg(io.inner.release.bits.header.src.clone)
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val xact_r_type = Reg(io.inner.release.bits.payload.r_type)
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2015-02-02 04:57:53 +01:00
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val xact_addr_block = Reg(io.inner.release.bits.payload.addr_block.clone)
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2014-12-12 10:11:08 +01:00
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val xact_client_xact_id = Reg(io.inner.release.bits.payload.client_xact_id.clone)
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val xact_data = Vec.fill(tlDataBeats){ Reg(io.inner.release.bits.payload.data.clone) }
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2015-02-02 04:57:53 +01:00
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val xact = Release(
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voluntary = Bool(true),
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r_type = xact_r_type,
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client_xact_id = xact_client_xact_id,
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addr_block = xact_addr_block)
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2014-12-12 10:11:08 +01:00
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2014-12-07 12:02:20 +01:00
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val collect_inner_data = Reg(init=Bool(false))
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2015-02-02 04:57:53 +01:00
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// TODO: assert that all releases have full blocks of data
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2014-12-07 12:02:20 +01:00
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val (inner_data_cnt, inner_data_done) =
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2015-02-02 04:57:53 +01:00
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Counter(io.inner.release.fire() && io.inner.release.bits.payload.hasMultibeatData(), tlDataBeats)
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2014-12-07 12:02:20 +01:00
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val (outer_data_cnt, outer_data_done) =
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2015-02-02 04:57:53 +01:00
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Counter(io.outer.acquire.fire() && io.outer.acquire.bits.payload.hasMultibeatData(), tlDataBeats)
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2013-01-29 01:39:45 +01:00
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io.has_acquire_conflict := Bool(false)
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2015-02-02 04:57:53 +01:00
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io.has_release_match := crel.payload.isVoluntary()
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2013-03-20 22:10:16 +01:00
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2014-04-30 01:49:18 +02:00
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io.outer.grant.ready := Bool(false)
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io.outer.acquire.valid := Bool(false)
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io.inner.acquire.ready := Bool(false)
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io.inner.probe.valid := Bool(false)
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io.inner.release.ready := Bool(false)
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io.inner.grant.valid := Bool(false)
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2014-12-12 10:11:08 +01:00
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io.inner.finish.ready := Bool(false)
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2014-04-30 01:49:18 +02:00
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io.inner.grant.bits.header.src := UInt(bankId)
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2014-12-12 10:11:08 +01:00
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io.inner.grant.bits.header.dst := xact_src
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2015-02-02 04:57:53 +01:00
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io.inner.grant.bits.payload := xact.makeGrant(UInt(trackerId))
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io.outer.acquire.bits.payload := Bundle(UncachedWriteBlock(
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client_xact_id = UInt(trackerId),
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addr_block = xact_addr_block,
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addr_beat = outer_data_cnt,
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data = xact_data(outer_data_cnt)),
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2014-12-12 10:11:08 +01:00
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{ case TLId => outerId })
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2014-12-07 12:02:20 +01:00
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when(collect_inner_data) {
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io.inner.release.ready := Bool(true)
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when(io.inner.release.valid) {
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2015-02-02 04:57:53 +01:00
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xact_data(inner_data_cnt) := crel.payload.data
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2014-12-07 12:02:20 +01:00
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}
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when(inner_data_done) { collect_inner_data := Bool(false) }
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}
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2013-01-29 01:39:45 +01:00
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switch (state) {
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is(s_idle) {
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2014-12-07 12:02:20 +01:00
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io.inner.release.ready := Bool(true)
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2014-04-30 01:49:18 +02:00
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when( io.inner.release.valid ) {
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2015-02-02 04:57:53 +01:00
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xact_src := crel.header.src
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xact_r_type := crel.payload.r_type
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xact_addr_block := crel.payload.addr_block
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xact_client_xact_id := crel.payload.client_xact_id
|
|
|
|
xact_data(UInt(0)) := crel.payload.data
|
|
|
|
collect_inner_data := crel.payload.hasMultibeatData()
|
|
|
|
state := Mux(crel.payload.hasData(), s_outer,
|
|
|
|
Mux(crel.payload.requiresAck(), s_ack, s_idle))
|
2013-01-29 01:39:45 +01:00
|
|
|
}
|
|
|
|
}
|
2014-12-07 12:02:20 +01:00
|
|
|
is(s_outer) {
|
2014-12-12 10:11:08 +01:00
|
|
|
io.outer.acquire.valid := (if(tlDataBeats == 1) Bool(true)
|
|
|
|
else !collect_inner_data || (outer_data_cnt < inner_data_cnt))
|
2015-02-02 04:57:53 +01:00
|
|
|
when(outer_data_done) {
|
|
|
|
state := Mux(xact.requiresAck(), s_grant, s_idle)
|
|
|
|
}
|
2013-01-29 01:39:45 +01:00
|
|
|
}
|
2015-02-02 04:57:53 +01:00
|
|
|
is(s_grant) {
|
2014-04-30 01:49:18 +02:00
|
|
|
io.inner.grant.valid := Bool(true)
|
2015-02-02 04:57:53 +01:00
|
|
|
when(io.inner.grant.ready) {
|
|
|
|
state := Mux(cgnt.payload.requiresAck(), s_ack, s_idle)
|
|
|
|
}
|
|
|
|
}
|
|
|
|
is(s_ack) {
|
|
|
|
// TODO: This state is unnecessary if no client will ever issue the
|
|
|
|
// pending Acquire that caused this writeback until it receives the
|
|
|
|
// Grant.voluntaryAck for this writeback
|
|
|
|
io.inner.finish.ready := Bool(true)
|
|
|
|
when(io.inner.finish.valid) { state := s_idle }
|
2013-01-29 01:39:45 +01:00
|
|
|
}
|
2013-01-17 08:57:35 +01:00
|
|
|
}
|
2013-01-29 01:39:45 +01:00
|
|
|
}
|
2013-01-17 08:57:35 +01:00
|
|
|
|
2014-09-24 20:14:36 +02:00
|
|
|
class AcquireTracker(trackerId: Int, bankId: Int, innerId: String, outerId: String) extends XactTracker(innerId, outerId) {
|
2015-02-02 04:57:53 +01:00
|
|
|
val s_idle :: s_probe :: s_mem_read :: s_mem_write :: s_make_grant :: s_mem_resp :: s_ack :: Nil = Enum(UInt(), 7)
|
2013-08-16 00:27:38 +02:00
|
|
|
val state = Reg(init=s_idle)
|
2014-12-12 10:11:08 +01:00
|
|
|
|
|
|
|
val xact_src = Reg(io.inner.acquire.bits.header.src.clone)
|
2015-02-02 10:02:06 +01:00
|
|
|
val xact_builtin_type = Reg(io.inner.acquire.bits.payload.builtin_type.clone)
|
2014-12-12 10:11:08 +01:00
|
|
|
val xact_a_type = Reg(io.inner.acquire.bits.payload.a_type.clone)
|
|
|
|
val xact_client_xact_id = Reg(io.inner.acquire.bits.payload.client_xact_id.clone)
|
2015-02-02 04:57:53 +01:00
|
|
|
val xact_addr_block = Reg(io.inner.acquire.bits.payload.addr_block.clone)
|
|
|
|
val xact_addr_beat = Reg(io.inner.acquire.bits.payload.addr_beat.clone)
|
2014-12-12 10:11:08 +01:00
|
|
|
val xact_subblock = Reg(io.inner.acquire.bits.payload.subblock.clone)
|
|
|
|
val xact_data = Vec.fill(tlDataBeats){ Reg(io.inner.acquire.bits.payload.data.clone) }
|
2015-02-02 04:57:53 +01:00
|
|
|
val xact = Acquire(
|
2015-02-02 10:02:06 +01:00
|
|
|
builtin_type = xact_builtin_type,
|
2015-02-02 04:57:53 +01:00
|
|
|
a_type = xact_a_type,
|
|
|
|
client_xact_id = xact_client_xact_id,
|
|
|
|
addr_block = xact_addr_block,
|
|
|
|
addr_beat = xact_addr_beat,
|
|
|
|
data = UInt(0),
|
|
|
|
subblock = xact_subblock)
|
2014-12-12 10:11:08 +01:00
|
|
|
|
2014-12-07 12:02:20 +01:00
|
|
|
val collect_inner_data = Reg(init=Bool(false))
|
2015-02-02 04:57:53 +01:00
|
|
|
//TODO: Assert that if xact.uncached, xact_a_type is ReadBlock or WriteBlock
|
2014-12-07 12:02:20 +01:00
|
|
|
val (inner_data_cnt, inner_data_done) =
|
2015-02-02 04:57:53 +01:00
|
|
|
Counter(io.inner.acquire.fire() && cacq.payload.hasMultibeatData(), tlDataBeats)
|
2014-12-07 12:02:20 +01:00
|
|
|
val (outer_data_cnt, outer_data_done) =
|
2015-02-02 04:57:53 +01:00
|
|
|
Counter(io.outer.acquire.fire() && macq.payload.hasMultibeatData(), tlDataBeats)
|
|
|
|
val (cgnt_data_cnt, cgnt_data_done) =
|
|
|
|
Counter(io.inner.grant.fire() && cgnt.payload.hasMultibeatData(), tlDataBeats)
|
|
|
|
|
2014-03-29 18:53:49 +01:00
|
|
|
|
2014-12-12 10:11:08 +01:00
|
|
|
val release_count = Reg(init=UInt(0, width = log2Up(nClients)))
|
2014-08-08 21:21:57 +02:00
|
|
|
val probe_flags = Reg(init=Bits(0, width = nClients))
|
2013-03-26 00:20:12 +01:00
|
|
|
val curr_p_id = PriorityEncoder(probe_flags)
|
2014-03-29 18:53:49 +01:00
|
|
|
|
2015-02-02 04:57:53 +01:00
|
|
|
val pending_outer_write = xact.hasData()
|
2014-12-30 07:55:58 +01:00
|
|
|
val pending_outer_read = co.requiresOuterRead(xact, co.managerMetadataOnFlush)
|
2014-03-29 18:53:49 +01:00
|
|
|
|
2014-08-08 21:21:57 +02:00
|
|
|
val probe_initial_flags = Bits(width = nClients)
|
2013-01-23 05:09:21 +01:00
|
|
|
probe_initial_flags := Bits(0)
|
2014-12-07 12:02:20 +01:00
|
|
|
// issue self-probes for uncached read xacts to facilitate I$ coherence
|
2015-02-02 04:57:53 +01:00
|
|
|
val probe_self = io.inner.acquire.bits.payload.requiresSelfProbe()
|
|
|
|
val myflag = Mux(probe_self, Bits(0), UIntToOH(cacq.header.src(log2Up(nClients)-1,0)))
|
2014-12-07 12:02:20 +01:00
|
|
|
probe_initial_flags := ~(io.tile_incoherent | myflag)
|
2013-01-17 08:57:35 +01:00
|
|
|
|
2015-02-06 22:20:44 +01:00
|
|
|
io.has_acquire_conflict := xact.conflicts(cacq.payload) &&
|
|
|
|
!collect_inner_data &&
|
|
|
|
(state != s_idle)
|
|
|
|
io.has_release_match := xact.conflicts(crel.payload) &&
|
2015-02-02 04:57:53 +01:00
|
|
|
!crel.payload.isVoluntary() &&
|
2014-12-12 10:11:08 +01:00
|
|
|
(state != s_idle)
|
|
|
|
|
2015-02-02 04:57:53 +01:00
|
|
|
val outer_write_acq = Bundle(UncachedWriteBlock(
|
|
|
|
client_xact_id = UInt(trackerId),
|
|
|
|
addr_block = xact_addr_block,
|
|
|
|
addr_beat = outer_data_cnt,
|
|
|
|
data = xact_data(outer_data_cnt)),
|
|
|
|
{ case TLId => outerId })
|
|
|
|
val outer_write_rel = Bundle(UncachedWriteBlock(
|
|
|
|
client_xact_id = UInt(trackerId),
|
|
|
|
addr_block = xact_addr_block,
|
|
|
|
addr_beat = crel.payload.addr_beat,
|
|
|
|
data = crel.payload.data),
|
2014-12-12 10:11:08 +01:00
|
|
|
{ case TLId => outerId })
|
2015-02-02 04:57:53 +01:00
|
|
|
val outer_read = Bundle(UncachedReadBlock(
|
|
|
|
client_xact_id = UInt(trackerId),
|
|
|
|
addr_block = xact_addr_block),
|
2014-12-12 10:11:08 +01:00
|
|
|
{ case TLId => outerId })
|
2014-03-29 18:53:49 +01:00
|
|
|
|
2014-04-30 01:49:18 +02:00
|
|
|
io.outer.acquire.valid := Bool(false)
|
2014-12-12 10:11:08 +01:00
|
|
|
io.outer.acquire.bits.payload := outer_read //default
|
2014-04-30 01:49:18 +02:00
|
|
|
io.outer.grant.ready := io.inner.grant.ready
|
2014-03-29 18:53:49 +01:00
|
|
|
|
2014-04-30 01:49:18 +02:00
|
|
|
io.inner.probe.valid := Bool(false)
|
|
|
|
io.inner.probe.bits.header.src := UInt(bankId)
|
|
|
|
io.inner.probe.bits.header.dst := curr_p_id
|
2015-02-02 04:57:53 +01:00
|
|
|
io.inner.probe.bits.payload := xact.makeProbe()
|
2014-03-29 18:53:49 +01:00
|
|
|
|
2014-04-30 01:49:18 +02:00
|
|
|
io.inner.grant.valid := Bool(false)
|
|
|
|
io.inner.grant.bits.header.src := UInt(bankId)
|
2014-12-12 10:11:08 +01:00
|
|
|
io.inner.grant.bits.header.dst := xact_src
|
2015-02-02 04:57:53 +01:00
|
|
|
io.inner.grant.bits.payload := xact.makeGrant(UInt(trackerId)) // Data bypassed in parent
|
2014-03-29 18:53:49 +01:00
|
|
|
|
2014-04-30 01:49:18 +02:00
|
|
|
io.inner.acquire.ready := Bool(false)
|
|
|
|
io.inner.release.ready := Bool(false)
|
2013-01-17 08:57:35 +01:00
|
|
|
|
2014-12-07 12:02:20 +01:00
|
|
|
when(collect_inner_data) {
|
|
|
|
io.inner.acquire.ready := Bool(true)
|
|
|
|
when(io.inner.acquire.valid) {
|
2015-02-02 04:57:53 +01:00
|
|
|
xact_data(inner_data_cnt) := cacq.payload.data
|
2014-12-07 12:02:20 +01:00
|
|
|
}
|
|
|
|
when(inner_data_done) { collect_inner_data := Bool(false) }
|
|
|
|
}
|
|
|
|
|
2013-01-17 08:57:35 +01:00
|
|
|
switch (state) {
|
|
|
|
is(s_idle) {
|
2014-04-30 01:49:18 +02:00
|
|
|
io.inner.acquire.ready := Bool(true)
|
2015-02-02 04:57:53 +01:00
|
|
|
val needs_outer_write = cacq.payload.hasData()
|
|
|
|
val needs_outer_read = co.requiresOuterRead(cacq.payload, co.managerMetadataOnFlush)
|
|
|
|
when(io.inner.acquire.valid) {
|
2015-02-02 10:02:06 +01:00
|
|
|
xact_builtin_type := cacq.payload.builtin_type
|
2015-02-02 04:57:53 +01:00
|
|
|
xact_a_type := cacq.payload.a_type
|
|
|
|
xact_addr_block := cacq.payload.addr_block
|
|
|
|
xact_addr_beat := cacq.payload.addr_beat
|
|
|
|
xact_client_xact_id := cacq.payload.client_xact_id
|
|
|
|
xact_data(UInt(0)) := cacq.payload.data
|
|
|
|
xact_subblock := cacq.payload.subblock
|
|
|
|
xact_src := cacq.header.src
|
|
|
|
collect_inner_data := cacq.payload.hasMultibeatData()
|
2013-01-23 05:09:21 +01:00
|
|
|
probe_flags := probe_initial_flags
|
2014-12-07 12:02:20 +01:00
|
|
|
release_count := PopCount(probe_initial_flags)
|
|
|
|
state := Mux(probe_initial_flags.orR, s_probe,
|
|
|
|
Mux(needs_outer_write, s_mem_write,
|
|
|
|
Mux(needs_outer_read, s_mem_read, s_make_grant)))
|
2013-01-17 08:57:35 +01:00
|
|
|
}
|
|
|
|
}
|
|
|
|
is(s_probe) {
|
2014-03-29 18:53:49 +01:00
|
|
|
// Generate probes
|
2014-04-30 01:49:18 +02:00
|
|
|
io.inner.probe.valid := probe_flags.orR
|
|
|
|
when(io.inner.probe.ready) {
|
2013-08-12 19:36:44 +02:00
|
|
|
probe_flags := probe_flags & ~(UIntToOH(curr_p_id))
|
2013-01-17 08:57:35 +01:00
|
|
|
}
|
2014-03-29 18:53:49 +01:00
|
|
|
|
|
|
|
// Handle releases, which may have data to be written back
|
2015-02-02 04:57:53 +01:00
|
|
|
io.inner.release.ready := !crel.payload.hasData() || io.outer.acquire.ready
|
2014-04-30 01:49:18 +02:00
|
|
|
when(io.inner.release.valid) {
|
2015-02-02 04:57:53 +01:00
|
|
|
when(crel.payload.hasData()) {
|
2014-04-30 01:49:18 +02:00
|
|
|
io.outer.acquire.valid := Bool(true)
|
|
|
|
io.outer.acquire.bits.payload := outer_write_rel
|
|
|
|
when(io.outer.acquire.ready) {
|
2014-12-07 12:02:20 +01:00
|
|
|
when(outer_data_done) {
|
|
|
|
release_count := release_count - UInt(1)
|
|
|
|
when(release_count === UInt(1)) {
|
|
|
|
state := Mux(pending_outer_write, s_mem_write,
|
|
|
|
Mux(pending_outer_read, s_mem_read, s_make_grant))
|
|
|
|
}
|
2014-03-29 18:53:49 +01:00
|
|
|
}
|
|
|
|
}
|
|
|
|
} .otherwise {
|
2014-12-07 12:02:20 +01:00
|
|
|
release_count := release_count - UInt(1)
|
2014-03-29 18:53:49 +01:00
|
|
|
when(release_count === UInt(1)) {
|
|
|
|
state := Mux(pending_outer_write, s_mem_write,
|
|
|
|
Mux(pending_outer_read, s_mem_read, s_make_grant))
|
|
|
|
}
|
2013-04-10 22:46:31 +02:00
|
|
|
}
|
2013-01-17 08:57:35 +01:00
|
|
|
}
|
2014-03-29 18:53:49 +01:00
|
|
|
}
|
2015-02-02 04:57:53 +01:00
|
|
|
is(s_mem_read) { // Read data from outer memory (possibly what was just written)
|
2014-04-30 01:49:18 +02:00
|
|
|
io.outer.acquire.valid := Bool(true)
|
|
|
|
io.outer.acquire.bits.payload := outer_read
|
2015-02-02 04:57:53 +01:00
|
|
|
when(io.outer.acquire.ready) { state := s_mem_resp }
|
2013-01-17 08:57:35 +01:00
|
|
|
}
|
2015-02-02 04:57:53 +01:00
|
|
|
is(s_mem_write) { // Write data to outer memory
|
2014-12-12 10:11:08 +01:00
|
|
|
io.outer.acquire.valid := (if(tlDataBeats == 1) Bool(true)
|
|
|
|
else !collect_inner_data || (outer_data_cnt < inner_data_cnt))
|
2014-04-30 01:49:18 +02:00
|
|
|
io.outer.acquire.bits.payload := outer_write_acq
|
2014-12-07 12:02:20 +01:00
|
|
|
when(outer_data_done) {
|
2014-03-29 18:53:49 +01:00
|
|
|
state := Mux(pending_outer_read, s_mem_read, s_make_grant)
|
2013-01-17 08:57:35 +01:00
|
|
|
}
|
|
|
|
}
|
2015-02-02 04:57:53 +01:00
|
|
|
is(s_make_grant) { // Manufactor a local grant (some kind of permission upgrade)
|
2014-04-30 01:49:18 +02:00
|
|
|
io.inner.grant.valid := Bool(true)
|
|
|
|
when(io.inner.grant.ready) {
|
2015-02-02 04:57:53 +01:00
|
|
|
state := Mux(cgnt.payload.requiresAck(), s_ack, s_idle)
|
2014-03-29 18:53:49 +01:00
|
|
|
}
|
2013-01-17 08:57:35 +01:00
|
|
|
}
|
2015-02-02 04:57:53 +01:00
|
|
|
is(s_mem_resp) { // Wait to forward grants from outer memory
|
|
|
|
when(io.outer.grant.valid && mgnt.payload.client_xact_id === UInt(trackerId)) {
|
2014-04-30 01:49:18 +02:00
|
|
|
io.inner.grant.valid := Bool(true)
|
2013-01-17 08:57:35 +01:00
|
|
|
}
|
2015-02-02 04:57:53 +01:00
|
|
|
when(cgnt_data_done) {
|
|
|
|
state := Mux(cgnt.payload.requiresAck(), s_ack, s_idle)
|
|
|
|
}
|
|
|
|
}
|
|
|
|
is(s_ack) { // Wait for transaction to complete
|
|
|
|
when(io.inner.finish.valid && cfin.payload.manager_xact_id === UInt(trackerId)) {
|
2014-03-29 18:53:49 +01:00
|
|
|
state := s_idle
|
2013-01-17 08:57:35 +01:00
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|