2012-09-27 21:59:45 +02:00
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package uncore
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2012-04-03 21:03:05 +02:00
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import Chisel._
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import Constants._
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2012-12-13 20:39:14 +01:00
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class TrackerProbeData(implicit conf: CoherenceHubConfiguration) extends Bundle {
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2013-01-16 00:52:47 +01:00
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val client_id = Bits(width = conf.ln.idBits)
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2012-04-03 21:03:05 +02:00
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}
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2012-12-13 20:39:14 +01:00
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class TrackerAllocReq(implicit conf: CoherenceHubConfiguration) extends Bundle {
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2013-01-22 02:17:26 +01:00
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val acquire = new Acquire()
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2013-01-16 00:52:47 +01:00
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val client_id = Bits(width = conf.ln.idBits)
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2012-10-16 22:58:18 +02:00
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override def clone = { new TrackerAllocReq().asInstanceOf[this.type] }
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2012-04-03 21:03:05 +02:00
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}
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class TrackerDependency extends Bundle {
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2013-01-22 02:17:26 +01:00
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val master_xact_id = Bits(width = MASTER_XACT_ID_BITS)
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2012-04-03 21:03:05 +02:00
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}
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2013-01-16 00:52:47 +01:00
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class XactTrackerBroadcast(id: Int)(implicit conf: CoherenceHubConfiguration) extends Component {
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2012-10-19 01:57:28 +02:00
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val co = conf.co
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2012-04-03 21:03:05 +02:00
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val io = new Bundle {
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2012-06-07 03:22:56 +02:00
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val alloc_req = (new FIFOIO) { new TrackerAllocReq }.flip
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val p_data = (new PipeIO) { new TrackerProbeData }.flip
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2012-04-03 21:03:05 +02:00
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val can_alloc = Bool(INPUT)
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2013-01-22 02:17:26 +01:00
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val grant_ack = Bool(INPUT)
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2013-01-23 05:09:21 +01:00
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val release_cnt_dec = Bits(INPUT, conf.ln.nTiles)
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val probe_cnt_inc = Bits(INPUT, conf.ln.nTiles)
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2012-12-13 20:39:14 +01:00
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val tile_incoherent = Bits(INPUT, conf.ln.nTiles)
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2013-01-23 05:09:21 +01:00
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val release_data = (new PipeIO) { new ReleaseData }.flip
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val acquire_data = (new PipeIO) { new AcquireData }.flip
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2013-01-22 02:17:26 +01:00
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val sent_grant_ack = Bool(INPUT)
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2013-01-23 05:09:21 +01:00
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val release_data_dep = (new PipeIO) { new TrackerDependency }.flip
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val acquire_data_dep = (new PipeIO) { new TrackerDependency }.flip
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2012-04-03 21:03:05 +02:00
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2012-06-07 03:22:56 +02:00
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val mem_req_cmd = (new FIFOIO) { new MemReqCmd }
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val mem_req_data = (new FIFOIO) { new MemData }
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2012-04-03 21:03:05 +02:00
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val mem_req_lock = Bool(OUTPUT)
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2013-01-22 02:17:26 +01:00
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val probe = (new FIFOIO) { new Probe }
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2012-04-03 21:03:05 +02:00
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val busy = Bool(OUTPUT)
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2012-07-13 03:12:49 +02:00
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val addr = Bits(OUTPUT, PADDR_BITS - OFFSET_BITS)
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2013-01-16 00:52:47 +01:00
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val init_client_id = Bits(OUTPUT, conf.ln.idBits)
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2013-01-23 05:09:21 +01:00
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val release_client_id = Bits(OUTPUT, conf.ln.idBits)
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2013-01-22 02:17:26 +01:00
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val client_xact_id = Bits(OUTPUT, CLIENT_XACT_ID_BITS)
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2012-12-13 20:39:14 +01:00
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val sharer_count = Bits(OUTPUT, conf.ln.idBits+1)
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2013-01-22 02:17:26 +01:00
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val a_type = Bits(OUTPUT, ACQUIRE_TYPE_MAX_BITS)
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2013-01-23 05:09:21 +01:00
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val push_probe = Bits(OUTPUT, conf.ln.nTiles)
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val pop_release = Bits(OUTPUT, conf.ln.nTiles)
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val pop_release_data = Bits(OUTPUT, conf.ln.nTiles)
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val pop_release_dep = Bits(OUTPUT, conf.ln.nTiles)
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val pop_acquire = Bits(OUTPUT, conf.ln.nTiles)
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val pop_acquire_data = Bits(OUTPUT, conf.ln.nTiles)
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val pop_acquire_dep = Bits(OUTPUT, conf.ln.nTiles)
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2013-01-22 02:17:26 +01:00
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val send_grant_ack = Bool(OUTPUT)
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2012-04-03 21:03:05 +02:00
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}
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2013-01-16 00:52:47 +01:00
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def doMemReqWrite(req_cmd: FIFOIO[MemReqCmd], req_data: FIFOIO[MemData], lock: Bool, data: PipeIO[MemData], trigger: Bool, cmd_sent: Bool, pop_data: Bits, pop_dep: Bits, at_front_of_dep_queue: Bool, client_id: UFix) {
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2012-04-03 21:03:05 +02:00
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req_cmd.bits.rw := Bool(true)
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req_data.bits := data.bits
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when(req_cmd.ready && req_cmd.valid) {
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cmd_sent := Bool(true)
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}
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2012-07-26 09:03:55 +02:00
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when (at_front_of_dep_queue) {
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2012-08-04 04:00:03 +02:00
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req_cmd.valid := !cmd_sent && req_data.ready && data.valid
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lock := data.valid || cmd_sent
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2012-07-26 09:03:55 +02:00
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when (req_cmd.ready || cmd_sent) {
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req_data.valid := data.valid
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when(req_data.ready) {
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2013-01-16 00:52:47 +01:00
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pop_data := UFix(1) << client_id
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2012-07-26 09:03:55 +02:00
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when (data.valid) {
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mem_cnt := mem_cnt_next
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when(mem_cnt === UFix(REFILL_CYCLES-1)) {
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2013-01-16 00:52:47 +01:00
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pop_dep := UFix(1) << client_id
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2012-07-26 09:03:55 +02:00
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trigger := Bool(false)
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}
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}
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2012-04-03 21:03:05 +02:00
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}
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}
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}
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}
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2012-06-07 03:22:56 +02:00
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def doMemReqRead(req_cmd: FIFOIO[MemReqCmd], trigger: Bool) {
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2012-04-03 21:03:05 +02:00
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req_cmd.valid := Bool(true)
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req_cmd.bits.rw := Bool(false)
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when(req_cmd.ready) {
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trigger := Bool(false)
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}
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}
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val s_idle :: s_ack :: s_mem :: s_probe :: s_busy :: Nil = Enum(5){ UFix() }
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val state = Reg(resetVal = s_idle)
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2013-01-22 02:17:26 +01:00
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val xact = Reg{ new Acquire }
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2013-01-16 00:52:47 +01:00
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val init_client_id_ = Reg{ Bits() }
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2013-01-23 05:09:21 +01:00
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val release_count = if (conf.ln.nTiles == 1) UFix(0) else Reg(resetVal = UFix(0, width = log2Up(conf.ln.nTiles)))
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val probe_flags = Reg(resetVal = Bits(0, width = conf.ln.nTiles))
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val release_client_id_ = Reg{ Bits() }
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2012-04-03 21:03:05 +02:00
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val x_needs_read = Reg(resetVal = Bool(false))
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2013-01-23 05:09:21 +01:00
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val acquire_data_needs_write = Reg(resetVal = Bool(false))
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val release_data_needs_write = Reg(resetVal = Bool(false))
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2012-04-03 21:03:05 +02:00
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val x_w_mem_cmd_sent = Reg(resetVal = Bool(false))
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val p_w_mem_cmd_sent = Reg(resetVal = Bool(false))
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2012-06-06 21:47:17 +02:00
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val mem_cnt = Reg(resetVal = UFix(0, width = log2Up(REFILL_CYCLES)))
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2012-04-03 21:03:05 +02:00
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val mem_cnt_next = mem_cnt + UFix(1)
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2012-06-06 21:47:17 +02:00
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val mem_cnt_max = ~UFix(0, width = log2Up(REFILL_CYCLES))
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2013-01-23 05:09:21 +01:00
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val probe_initial_flags = Bits(width = conf.ln.nTiles)
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probe_initial_flags := Bits(0)
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2012-12-13 20:39:14 +01:00
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if (conf.ln.nTiles > 1) {
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2012-11-16 11:37:56 +01:00
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// issue self-probes for uncached read xacts to facilitate I$ coherence
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// TODO: this is hackish; figure out how to do it more systematically
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val probe_self = co match {
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2013-01-22 02:17:26 +01:00
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case u: CoherencePolicyWithUncached => u.isUncachedReadTransaction(io.alloc_req.bits.acquire)
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2012-11-16 11:37:56 +01:00
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case _ => Bool(false)
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}
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2013-01-16 00:52:47 +01:00
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val myflag = Mux(probe_self, Bits(0), UFixToOH(io.alloc_req.bits.client_id(log2Up(conf.ln.nTiles)-1,0)))
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2013-01-23 05:09:21 +01:00
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probe_initial_flags := ~(io.tile_incoherent | myflag)
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2012-11-16 11:37:56 +01:00
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}
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2012-04-03 21:03:05 +02:00
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io.busy := state != s_idle
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2012-11-16 11:37:56 +01:00
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io.addr := xact.addr
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2013-01-16 00:52:47 +01:00
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io.init_client_id := init_client_id_
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2013-01-23 05:09:21 +01:00
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io.release_client_id := release_client_id_
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2013-01-22 02:17:26 +01:00
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io.client_xact_id := xact.client_xact_id
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2012-12-13 20:39:14 +01:00
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io.sharer_count := UFix(conf.ln.nTiles) // TODO: Broadcast only
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2013-01-22 02:17:26 +01:00
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io.a_type := xact.a_type
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2012-04-03 21:03:05 +02:00
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2012-04-10 09:09:58 +02:00
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io.mem_req_cmd.valid := Bool(false)
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2012-04-03 21:03:05 +02:00
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io.mem_req_cmd.bits.rw := Bool(false)
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2012-11-16 11:37:56 +01:00
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io.mem_req_cmd.bits.addr := xact.addr
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2012-04-03 21:03:05 +02:00
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io.mem_req_cmd.bits.tag := UFix(id)
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io.mem_req_data.valid := Bool(false)
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io.mem_req_data.bits.data := UFix(0)
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io.mem_req_lock := Bool(false)
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2013-01-22 02:17:26 +01:00
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io.probe.valid := Bool(false)
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io.probe.bits.p_type := co.getProbeType(xact.a_type, UFix(0))
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io.probe.bits.master_xact_id := UFix(id)
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io.probe.bits.addr := xact.addr
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2013-01-23 05:09:21 +01:00
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io.push_probe := Bits(0, width = conf.ln.nTiles)
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io.pop_release := Bits(0, width = conf.ln.nTiles)
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io.pop_release_data := Bits(0, width = conf.ln.nTiles)
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io.pop_release_dep := Bits(0, width = conf.ln.nTiles)
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io.pop_acquire := Bits(0, width = conf.ln.nTiles)
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io.pop_acquire_data := Bits(0, width = conf.ln.nTiles)
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io.pop_acquire_dep := Bits(0, width = conf.ln.nTiles)
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2013-01-22 02:17:26 +01:00
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io.send_grant_ack := Bool(false)
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2012-04-03 21:03:05 +02:00
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switch (state) {
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is(s_idle) {
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when( io.alloc_req.valid && io.can_alloc ) {
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2013-01-22 02:17:26 +01:00
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xact := io.alloc_req.bits.acquire
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2013-01-16 00:52:47 +01:00
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init_client_id_ := io.alloc_req.bits.client_id
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2013-01-23 05:09:21 +01:00
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acquire_data_needs_write := co.messageHasData(io.alloc_req.bits.acquire)
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2013-01-22 02:17:26 +01:00
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x_needs_read := co.needsMemRead(io.alloc_req.bits.acquire.a_type, UFix(0))
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2013-01-23 05:09:21 +01:00
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probe_flags := probe_initial_flags
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2012-04-03 21:03:05 +02:00
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mem_cnt := UFix(0)
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p_w_mem_cmd_sent := Bool(false)
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x_w_mem_cmd_sent := Bool(false)
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2013-01-23 05:09:21 +01:00
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io.pop_acquire := UFix(1) << io.alloc_req.bits.client_id
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2012-12-13 20:39:14 +01:00
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if(conf.ln.nTiles > 1) {
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2013-01-23 05:09:21 +01:00
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release_count := PopCount(probe_initial_flags)
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state := Mux(probe_initial_flags.orR, s_probe, s_mem)
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2012-04-19 01:31:14 +02:00
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} else state := s_mem
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2012-04-03 21:03:05 +02:00
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}
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}
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is(s_probe) {
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2013-01-23 05:09:21 +01:00
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when(probe_flags.orR) {
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io.push_probe := probe_flags
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2013-01-22 02:17:26 +01:00
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io.probe.valid := Bool(true)
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2012-04-03 21:03:05 +02:00
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}
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2013-01-23 05:09:21 +01:00
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when(io.probe_cnt_inc.orR) {
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probe_flags := probe_flags & ~io.probe_cnt_inc // unflag sent reqs
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2012-04-03 21:03:05 +02:00
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}
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2013-01-23 05:09:21 +01:00
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when(io.release_cnt_dec.orR) {
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val dec = PopCount(io.release_cnt_dec)
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io.pop_release := io.release_cnt_dec
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if(conf.ln.nTiles > 1) release_count := release_count - dec
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when(release_count === dec) {
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2012-04-03 21:03:05 +02:00
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state := s_mem
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}
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}
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when(io.p_data.valid) {
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2013-01-23 05:09:21 +01:00
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release_data_needs_write := Bool(true)
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release_client_id_ := io.p_data.bits.client_id
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2012-04-03 21:03:05 +02:00
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}
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}
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is(s_mem) {
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2013-01-23 05:09:21 +01:00
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when (release_data_needs_write) {
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2012-04-03 21:03:05 +02:00
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doMemReqWrite(io.mem_req_cmd,
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io.mem_req_data,
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io.mem_req_lock,
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2013-01-23 05:09:21 +01:00
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io.release_data,
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release_data_needs_write,
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2012-04-03 21:03:05 +02:00
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p_w_mem_cmd_sent,
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2013-01-23 05:09:21 +01:00
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io.pop_release_data,
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io.pop_release_dep,
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io.release_data_dep.valid && (io.release_data_dep.bits.master_xact_id === UFix(id)),
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release_client_id_)
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} . elsewhen(acquire_data_needs_write) {
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2012-04-03 21:03:05 +02:00
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doMemReqWrite(io.mem_req_cmd,
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io.mem_req_data,
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io.mem_req_lock,
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2013-01-23 05:09:21 +01:00
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io.acquire_data,
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acquire_data_needs_write,
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2012-04-03 21:03:05 +02:00
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x_w_mem_cmd_sent,
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2013-01-23 05:09:21 +01:00
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io.pop_acquire_data,
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io.pop_acquire_dep,
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io.acquire_data_dep.valid && (io.acquire_data_dep.bits.master_xact_id === UFix(id)),
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2013-01-16 00:52:47 +01:00
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init_client_id_)
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2012-04-03 21:03:05 +02:00
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} . elsewhen (x_needs_read) {
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doMemReqRead(io.mem_req_cmd, x_needs_read)
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} . otherwise {
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2013-01-22 02:17:26 +01:00
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state := Mux(co.needsAckReply(xact.a_type, UFix(0)), s_ack, s_busy)
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2012-04-03 21:03:05 +02:00
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}
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}
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is(s_ack) {
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2013-01-22 02:17:26 +01:00
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io.send_grant_ack := Bool(true)
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when(io.sent_grant_ack) { state := s_busy }
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2012-04-03 21:03:05 +02:00
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}
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is(s_busy) { // Nothing left to do but wait for transaction to complete
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2013-01-22 02:17:26 +01:00
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when (io.grant_ack) {
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2012-04-03 21:03:05 +02:00
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state := s_idle
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}
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}
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}
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}
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2012-12-13 20:39:14 +01:00
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case class CoherenceHubConfiguration(co: CoherencePolicy, ln: LogicalNetworkConfiguration)
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2012-10-16 22:58:18 +02:00
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2013-01-07 22:57:48 +01:00
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class CoherenceHubAdapter(implicit conf: LogicalNetworkConfiguration) extends Component with MasterCoherenceAgent {
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val io = new Bundle {
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val net = (new TileLinkIO).flip
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val hub = Vec(conf.nTiles) { new TileLinkIO }
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}
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2013-01-16 00:52:47 +01:00
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val netClientProducedSubBundles = io.net.getClass.getMethods.filter( x =>
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classOf[ClientSourcedIO[Data]].isAssignableFrom(x.getReturnType)).map{ m =>
|
|
|
|
m.invoke(io.net).asInstanceOf[ClientSourcedIO[LogicalNetworkIO[Data]]] }
|
|
|
|
val netMasterProducedSubBundles = io.net.getClass.getMethods.filter( x =>
|
|
|
|
classOf[MasterSourcedIO[Data]].isAssignableFrom(x.getReturnType)).map{ m =>
|
|
|
|
m.invoke(io.net).asInstanceOf[MasterSourcedIO[LogicalNetworkIO[Data]]] }
|
2013-01-07 22:57:48 +01:00
|
|
|
|
2013-01-16 00:52:47 +01:00
|
|
|
val hubClientProducedSubBundles = io.hub.map{ io => {
|
2013-01-07 22:57:48 +01:00
|
|
|
io.getClass.getMethods.filter( x =>
|
2013-01-16 00:52:47 +01:00
|
|
|
classOf[ClientSourcedIO[Data]].isAssignableFrom(x.getReturnType)).map{ m =>
|
|
|
|
m.invoke(io).asInstanceOf[ClientSourcedIO[LogicalNetworkIO[Data]]] }}}.transpose
|
|
|
|
val hubMasterProducedSubBundles = io.hub.map{ io => {
|
2013-01-07 22:57:48 +01:00
|
|
|
io.getClass.getMethods.filter( x =>
|
2013-01-16 00:52:47 +01:00
|
|
|
classOf[MasterSourcedIO[Data]].isAssignableFrom(x.getReturnType)).map{ m =>
|
|
|
|
m.invoke(io).asInstanceOf[MasterSourcedIO[LogicalNetworkIO[Data]]] }}}.transpose
|
2013-01-07 22:57:48 +01:00
|
|
|
|
2013-01-16 00:52:47 +01:00
|
|
|
hubMasterProducedSubBundles.zip(netMasterProducedSubBundles).foreach{ case(hub, net) => {
|
|
|
|
net.bits.header.src := UFix(0)
|
|
|
|
net.bits.header.dst := Vec(hub.map(_.valid)){Bool()}.indexWhere{s: Bool => s}
|
|
|
|
net.bits.payload := hub(0).bits.payload
|
2013-01-07 22:57:48 +01:00
|
|
|
net.valid := hub.map(_.valid).fold(Bool(false))(_||_)
|
|
|
|
hub.foreach( _.ready := net.ready)
|
|
|
|
}}
|
2013-01-16 00:52:47 +01:00
|
|
|
hubClientProducedSubBundles.zip(netClientProducedSubBundles).foreach{ case(hub, net) => {
|
|
|
|
hub.foreach(_.bits.header := net.bits.header)
|
|
|
|
hub.zipWithIndex.foreach{ case(h,i) => h.valid := (net.bits.header.src === UFix(i)) && net.valid }
|
|
|
|
hub.foreach(_.bits.payload := net.bits.payload)
|
2013-01-07 22:57:48 +01:00
|
|
|
net.ready := hub.map(_.ready).fold(Bool(false))(_||_)
|
|
|
|
}}
|
|
|
|
}
|
|
|
|
|
2012-12-13 20:39:14 +01:00
|
|
|
abstract class CoherenceHub(implicit conf: LogicalNetworkConfiguration) extends Component with MasterCoherenceAgent {
|
2012-04-03 21:03:05 +02:00
|
|
|
val io = new Bundle {
|
2013-01-07 22:57:48 +01:00
|
|
|
val tiles = Vec(conf.nTiles) { new TileLinkIO }.flip
|
|
|
|
val incoherent = Vec(conf.nTiles) { Bool() }.asInput
|
2012-04-03 21:03:05 +02:00
|
|
|
val mem = new ioMem
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2012-12-13 20:39:14 +01:00
|
|
|
class CoherenceHubNull(implicit conf: CoherenceHubConfiguration) extends CoherenceHub()(conf.ln)
|
2012-04-03 21:03:05 +02:00
|
|
|
{
|
2012-10-19 01:57:28 +02:00
|
|
|
val co = conf.co.asInstanceOf[ThreeStateIncoherence]
|
|
|
|
|
2013-01-23 05:09:21 +01:00
|
|
|
val acquire = io.tiles(0).acquire
|
|
|
|
val is_write = acquire.bits.payload.a_type === co.acquireWriteback
|
|
|
|
acquire.ready := io.mem.req_cmd.ready && !(is_write && io.mem.resp.valid) //stall write req/resp to handle previous read resp
|
|
|
|
io.mem.req_cmd.valid := acquire.valid && !(is_write && io.mem.resp.valid)
|
2012-04-03 21:03:05 +02:00
|
|
|
io.mem.req_cmd.bits.rw := is_write
|
2013-01-23 05:09:21 +01:00
|
|
|
io.mem.req_cmd.bits.tag := acquire.bits.payload.client_xact_id
|
|
|
|
io.mem.req_cmd.bits.addr := acquire.bits.payload.addr
|
2013-01-22 02:17:26 +01:00
|
|
|
io.mem.req_data <> io.tiles(0).acquire_data
|
|
|
|
|
|
|
|
val grant = io.tiles(0).grant
|
|
|
|
grant.bits.payload.g_type := Mux(io.mem.resp.valid, co.grantData, co.grantAck)
|
2013-01-23 05:09:21 +01:00
|
|
|
grant.bits.payload.client_xact_id := Mux(io.mem.resp.valid, io.mem.resp.bits.tag, acquire.bits.payload.client_xact_id)
|
2013-01-22 02:17:26 +01:00
|
|
|
grant.bits.payload.master_xact_id := UFix(0) // don't care
|
|
|
|
grant.bits.payload.data := io.mem.resp.bits.data
|
|
|
|
grant.bits.payload.require_ack := Bool(true)
|
2013-01-23 05:09:21 +01:00
|
|
|
grant.valid := io.mem.resp.valid || acquire.valid && is_write && io.mem.req_cmd.ready
|
2013-01-22 02:17:26 +01:00
|
|
|
|
|
|
|
io.tiles(0).abort.valid := Bool(false)
|
|
|
|
io.tiles(0).grant_ack.ready := Bool(true)
|
|
|
|
io.tiles(0).probe.valid := Bool(false)
|
|
|
|
io.tiles(0).release.ready := Bool(true)
|
|
|
|
io.tiles(0).release_data.ready := Bool(true)
|
2012-04-03 21:03:05 +02:00
|
|
|
}
|
|
|
|
|
|
|
|
|
2012-12-13 20:39:14 +01:00
|
|
|
class CoherenceHubBroadcast(implicit conf: CoherenceHubConfiguration) extends CoherenceHub()(conf.ln)
|
2012-04-03 21:03:05 +02:00
|
|
|
{
|
2013-01-16 00:52:47 +01:00
|
|
|
implicit val lnConf = conf.ln
|
2012-10-19 01:57:28 +02:00
|
|
|
val co = conf.co
|
2013-01-16 00:52:47 +01:00
|
|
|
val trackerList = (0 until NGLOBAL_XACTS).map(new XactTrackerBroadcast(_))
|
2012-04-03 21:03:05 +02:00
|
|
|
|
2012-05-24 19:33:15 +02:00
|
|
|
val busy_arr = Vec(NGLOBAL_XACTS){ Bool() }
|
|
|
|
val addr_arr = Vec(NGLOBAL_XACTS){ Bits(width=PADDR_BITS-OFFSET_BITS) }
|
2013-01-16 00:52:47 +01:00
|
|
|
val init_client_id_arr = Vec(NGLOBAL_XACTS){ Bits(width=conf.ln.idBits) }
|
2013-01-22 02:17:26 +01:00
|
|
|
val client_xact_id_arr = Vec(NGLOBAL_XACTS){ Bits(width=CLIENT_XACT_ID_BITS) }
|
|
|
|
val a_type_arr = Vec(NGLOBAL_XACTS){ Bits(width=ACQUIRE_TYPE_MAX_BITS) }
|
2012-12-13 20:39:14 +01:00
|
|
|
val sh_count_arr = Vec(NGLOBAL_XACTS){ Bits(width=conf.ln.idBits) }
|
2013-01-22 02:17:26 +01:00
|
|
|
val send_grant_ack_arr = Vec(NGLOBAL_XACTS){ Bool() }
|
2012-05-24 19:33:15 +02:00
|
|
|
|
|
|
|
val do_free_arr = Vec(NGLOBAL_XACTS){ Bool() }
|
2013-01-23 05:09:21 +01:00
|
|
|
val release_cnt_dec_arr = VecBuf(NGLOBAL_XACTS){ Vec(conf.ln.nTiles){ Bool()} }
|
|
|
|
val probe_cnt_inc_arr = VecBuf(NGLOBAL_XACTS){ Vec(conf.ln.nTiles){ Bool()} }
|
2013-01-22 02:17:26 +01:00
|
|
|
val sent_grant_ack_arr = Vec(NGLOBAL_XACTS){ Bool() }
|
2013-01-16 00:52:47 +01:00
|
|
|
val p_data_client_id_arr = Vec(NGLOBAL_XACTS){ Bits(width=conf.ln.idBits) }
|
2012-05-24 19:33:15 +02:00
|
|
|
val p_data_valid_arr = Vec(NGLOBAL_XACTS){ Bool() }
|
2012-04-03 21:03:05 +02:00
|
|
|
|
|
|
|
for( i <- 0 until NGLOBAL_XACTS) {
|
|
|
|
val t = trackerList(i).io
|
|
|
|
busy_arr(i) := t.busy
|
|
|
|
addr_arr(i) := t.addr
|
2013-01-16 00:52:47 +01:00
|
|
|
init_client_id_arr(i) := t.init_client_id
|
2013-01-22 02:17:26 +01:00
|
|
|
client_xact_id_arr(i) := t.client_xact_id
|
|
|
|
a_type_arr(i) := t.a_type
|
2012-04-03 21:03:05 +02:00
|
|
|
sh_count_arr(i) := t.sharer_count
|
2013-01-22 02:17:26 +01:00
|
|
|
send_grant_ack_arr(i) := t.send_grant_ack
|
|
|
|
t.grant_ack := do_free_arr(i)
|
2013-01-16 00:52:47 +01:00
|
|
|
t.p_data.bits.client_id := p_data_client_id_arr(i)
|
2012-04-03 21:03:05 +02:00
|
|
|
t.p_data.valid := p_data_valid_arr(i)
|
2013-01-23 05:09:21 +01:00
|
|
|
t.release_cnt_dec := release_cnt_dec_arr(i).toBits
|
|
|
|
t.probe_cnt_inc := probe_cnt_inc_arr(i).toBits
|
2013-01-07 22:57:48 +01:00
|
|
|
t.tile_incoherent := io.incoherent.toBits
|
2013-01-22 02:17:26 +01:00
|
|
|
t.sent_grant_ack := sent_grant_ack_arr(i)
|
2012-04-03 21:03:05 +02:00
|
|
|
do_free_arr(i) := Bool(false)
|
2013-01-22 02:17:26 +01:00
|
|
|
sent_grant_ack_arr(i) := Bool(false)
|
2013-01-16 00:52:47 +01:00
|
|
|
p_data_client_id_arr(i) := Bits(0, width = conf.ln.idBits)
|
2012-04-03 21:03:05 +02:00
|
|
|
p_data_valid_arr(i) := Bool(false)
|
2012-12-13 20:39:14 +01:00
|
|
|
for( j <- 0 until conf.ln.nTiles) {
|
2013-01-23 05:09:21 +01:00
|
|
|
release_cnt_dec_arr(i)(j) := Bool(false)
|
|
|
|
probe_cnt_inc_arr(i)(j) := Bool(false)
|
2012-04-03 21:03:05 +02:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2013-01-23 05:09:21 +01:00
|
|
|
val release_data_dep_list = List.fill(conf.ln.nTiles)((new Queue(NGLOBAL_XACTS)){new TrackerDependency}) // depth must >= NPRIMARY
|
|
|
|
val acquire_data_dep_list = List.fill(conf.ln.nTiles)((new Queue(NGLOBAL_XACTS)){new TrackerDependency}) // depth should >= NPRIMARY
|
2012-04-03 21:03:05 +02:00
|
|
|
|
|
|
|
// Free finished transactions
|
2012-12-13 20:39:14 +01:00
|
|
|
for( j <- 0 until conf.ln.nTiles ) {
|
2013-01-23 05:09:21 +01:00
|
|
|
val ack = io.tiles(j).grant_ack
|
|
|
|
when (ack.valid) {
|
|
|
|
do_free_arr(ack.bits.payload.master_xact_id) := Bool(true)
|
2012-04-03 21:03:05 +02:00
|
|
|
}
|
2013-01-23 05:09:21 +01:00
|
|
|
ack.ready := Bool(true)
|
2012-04-03 21:03:05 +02:00
|
|
|
}
|
|
|
|
|
|
|
|
// Reply to initial requestor
|
|
|
|
// Forward memory responses from mem to tile or arbitrate to ack
|
|
|
|
val mem_idx = io.mem.resp.bits.tag
|
2013-01-22 02:17:26 +01:00
|
|
|
val ack_idx = PriorityEncoder(send_grant_ack_arr.toBits)
|
2012-12-13 20:39:14 +01:00
|
|
|
for( j <- 0 until conf.ln.nTiles ) {
|
2013-01-22 02:17:26 +01:00
|
|
|
val rep = io.tiles(j).grant
|
|
|
|
rep.bits.payload.g_type := UFix(0)
|
|
|
|
rep.bits.payload.client_xact_id := UFix(0)
|
|
|
|
rep.bits.payload.master_xact_id := UFix(0)
|
2013-01-16 00:52:47 +01:00
|
|
|
rep.bits.payload.data := io.mem.resp.bits.data
|
|
|
|
rep.bits.payload.require_ack := Bool(true)
|
2012-04-03 21:03:05 +02:00
|
|
|
rep.valid := Bool(false)
|
2013-01-16 00:52:47 +01:00
|
|
|
when(io.mem.resp.valid && (UFix(j) === init_client_id_arr(mem_idx))) {
|
2013-01-22 02:17:26 +01:00
|
|
|
rep.bits.payload.g_type := co.getGrantType(a_type_arr(mem_idx), sh_count_arr(mem_idx))
|
|
|
|
rep.bits.payload.client_xact_id := client_xact_id_arr(mem_idx)
|
|
|
|
rep.bits.payload.master_xact_id := mem_idx
|
2012-04-03 21:03:05 +02:00
|
|
|
rep.valid := Bool(true)
|
|
|
|
} . otherwise {
|
2013-01-22 02:17:26 +01:00
|
|
|
rep.bits.payload.g_type := co.getGrantType(a_type_arr(ack_idx), sh_count_arr(ack_idx))
|
|
|
|
rep.bits.payload.client_xact_id := client_xact_id_arr(ack_idx)
|
|
|
|
rep.bits.payload.master_xact_id := ack_idx
|
2013-01-16 00:52:47 +01:00
|
|
|
when (UFix(j) === init_client_id_arr(ack_idx)) {
|
2013-01-22 02:17:26 +01:00
|
|
|
rep.valid := send_grant_ack_arr.toBits.orR
|
|
|
|
sent_grant_ack_arr(ack_idx) := rep.ready
|
2012-04-03 21:03:05 +02:00
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
2013-01-22 02:17:26 +01:00
|
|
|
io.mem.resp.ready := io.tiles(init_client_id_arr(mem_idx)).grant.ready
|
2012-04-03 21:03:05 +02:00
|
|
|
|
|
|
|
// Create an arbiter for the one memory port
|
|
|
|
// We have to arbitrate between the different trackers' memory requests
|
|
|
|
// and once we have picked a request, get the right write data
|
2012-07-26 09:03:55 +02:00
|
|
|
val mem_req_cmd_arb = (new Arbiter(NGLOBAL_XACTS)) { new MemReqCmd() }
|
2012-04-03 21:03:05 +02:00
|
|
|
val mem_req_data_arb = (new LockingArbiter(NGLOBAL_XACTS)) { new MemData() }
|
|
|
|
for( i <- 0 until NGLOBAL_XACTS ) {
|
|
|
|
mem_req_cmd_arb.io.in(i) <> trackerList(i).io.mem_req_cmd
|
|
|
|
mem_req_data_arb.io.in(i) <> trackerList(i).io.mem_req_data
|
|
|
|
mem_req_data_arb.io.lock(i) <> trackerList(i).io.mem_req_lock
|
|
|
|
}
|
2012-07-26 09:03:55 +02:00
|
|
|
io.mem.req_cmd <> Queue(mem_req_cmd_arb.io.out)
|
|
|
|
io.mem.req_data <> Queue(mem_req_data_arb.io.out)
|
2012-04-03 21:03:05 +02:00
|
|
|
|
|
|
|
// Handle probe replies, which may or may not have data
|
2012-12-13 20:39:14 +01:00
|
|
|
for( j <- 0 until conf.ln.nTiles ) {
|
2013-01-23 05:09:21 +01:00
|
|
|
val release = io.tiles(j).release
|
|
|
|
val release_data = io.tiles(j).release_data
|
|
|
|
val idx = release.bits.payload.master_xact_id
|
|
|
|
val pop_releases = trackerList.map(_.io.pop_release(j).toBool)
|
|
|
|
val do_pop = foldR(pop_releases)(_ || _)
|
|
|
|
release.ready := Bool(true)
|
|
|
|
release_data_dep_list(j).io.enq.valid := release.valid && co.messageHasData(release.bits.payload)
|
|
|
|
release_data_dep_list(j).io.enq.bits.master_xact_id := release.bits.payload.master_xact_id
|
|
|
|
release_data.ready := foldR(trackerList.map(_.io.pop_release_data(j)))(_ || _)
|
|
|
|
when (release.valid && co.messageHasData(release.bits.payload)) {
|
2012-04-03 21:03:05 +02:00
|
|
|
p_data_valid_arr(idx) := Bool(true)
|
2013-01-16 00:52:47 +01:00
|
|
|
p_data_client_id_arr(idx) := UFix(j)
|
2012-04-03 21:03:05 +02:00
|
|
|
}
|
2013-01-23 05:09:21 +01:00
|
|
|
release_data_dep_list(j).io.deq.ready := foldR(trackerList.map(_.io.pop_release_dep(j).toBool))(_||_)
|
2012-04-03 21:03:05 +02:00
|
|
|
}
|
|
|
|
for( i <- 0 until NGLOBAL_XACTS ) {
|
2013-01-23 05:09:21 +01:00
|
|
|
trackerList(i).io.release_data.valid := io.tiles(trackerList(i).io.release_client_id).release_data.valid
|
|
|
|
trackerList(i).io.release_data.bits := io.tiles(trackerList(i).io.release_client_id).release_data.bits.payload
|
2012-04-03 21:03:05 +02:00
|
|
|
|
2013-01-23 05:09:21 +01:00
|
|
|
trackerList(i).io.release_data_dep.valid := MuxLookup(trackerList(i).io.release_client_id, release_data_dep_list(0).io.deq.valid, (0 until conf.ln.nTiles).map( j => UFix(j) -> release_data_dep_list(j).io.deq.valid))
|
|
|
|
trackerList(i).io.release_data_dep.bits := MuxLookup(trackerList(i).io.release_client_id, release_data_dep_list(0).io.deq.bits, (0 until conf.ln.nTiles).map( j => UFix(j) -> release_data_dep_list(j).io.deq.bits))
|
2012-04-03 21:03:05 +02:00
|
|
|
|
2012-12-13 20:39:14 +01:00
|
|
|
for( j <- 0 until conf.ln.nTiles) {
|
2013-01-23 05:09:21 +01:00
|
|
|
val release = io.tiles(j).release
|
|
|
|
release_cnt_dec_arr(i)(j) := release.valid && (release.bits.payload.master_xact_id === UFix(i))
|
2012-04-03 21:03:05 +02:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
// Nack conflicting transaction init attempts
|
2012-04-25 00:11:59 +02:00
|
|
|
val s_idle :: s_abort_drain :: s_abort_send :: Nil = Enum(3){ UFix() }
|
2012-12-13 20:39:14 +01:00
|
|
|
val abort_state_arr = Vec(conf.ln.nTiles) { Reg(resetVal = s_idle) }
|
|
|
|
val want_to_abort_arr = Vec(conf.ln.nTiles) { Bool() }
|
|
|
|
for( j <- 0 until conf.ln.nTiles ) {
|
2013-01-23 05:09:21 +01:00
|
|
|
val acquire = io.tiles(j).acquire
|
|
|
|
val acquire_data = io.tiles(j).acquire_data
|
2013-01-22 02:17:26 +01:00
|
|
|
val x_abort = io.tiles(j).abort
|
2012-06-06 21:47:17 +02:00
|
|
|
val abort_cnt = Reg(resetVal = UFix(0, width = log2Up(REFILL_CYCLES)))
|
2012-05-24 19:33:15 +02:00
|
|
|
val conflicts = Vec(NGLOBAL_XACTS) { Bool() }
|
2012-04-03 21:03:05 +02:00
|
|
|
for( i <- 0 until NGLOBAL_XACTS) {
|
|
|
|
val t = trackerList(i).io
|
2013-01-23 05:09:21 +01:00
|
|
|
conflicts(i) := t.busy && acquire.valid && co.isCoherenceConflict(t.addr, acquire.bits.payload.addr)
|
2012-04-03 21:03:05 +02:00
|
|
|
}
|
2013-01-23 05:09:21 +01:00
|
|
|
x_abort.bits.payload.client_xact_id := acquire.bits.payload.client_xact_id
|
|
|
|
want_to_abort_arr(j) := acquire.valid && (conflicts.toBits.orR || busy_arr.toBits.andR || (!acquire_data_dep_list(j).io.enq.ready && co.messageHasData(acquire.bits.payload)))
|
2012-04-03 21:03:05 +02:00
|
|
|
|
|
|
|
x_abort.valid := Bool(false)
|
|
|
|
switch(abort_state_arr(j)) {
|
|
|
|
is(s_idle) {
|
|
|
|
when(want_to_abort_arr(j)) {
|
2013-01-23 05:09:21 +01:00
|
|
|
when(co.messageHasData(acquire.bits.payload)) {
|
2012-04-03 21:03:05 +02:00
|
|
|
abort_state_arr(j) := s_abort_drain
|
|
|
|
} . otherwise {
|
|
|
|
abort_state_arr(j) := s_abort_send
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
2013-01-23 05:09:21 +01:00
|
|
|
is(s_abort_drain) { // raises acquire_data.ready below
|
|
|
|
when(acquire_data.valid) {
|
2012-04-03 21:03:05 +02:00
|
|
|
abort_cnt := abort_cnt + UFix(1)
|
2012-06-06 21:47:17 +02:00
|
|
|
when(abort_cnt === ~UFix(0, width = log2Up(REFILL_CYCLES))) {
|
2012-04-03 21:03:05 +02:00
|
|
|
abort_state_arr(j) := s_abort_send
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
is(s_abort_send) { // nothing is dequeued for now
|
|
|
|
x_abort.valid := Bool(true)
|
2013-01-23 05:09:21 +01:00
|
|
|
when(x_abort.ready) { // raises acquire.ready below
|
2012-04-25 00:11:59 +02:00
|
|
|
abort_state_arr(j) := s_idle
|
2012-04-03 21:03:05 +02:00
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
// Handle transaction initiation requests
|
|
|
|
// Only one allocation per cycle
|
|
|
|
// Init requests may or may not have data
|
|
|
|
val alloc_arb = (new Arbiter(NGLOBAL_XACTS)) { Bool() }
|
2012-12-13 20:39:14 +01:00
|
|
|
val init_arb = (new Arbiter(conf.ln.nTiles)) { new TrackerAllocReq }
|
2012-04-03 21:03:05 +02:00
|
|
|
for( i <- 0 until NGLOBAL_XACTS ) {
|
|
|
|
alloc_arb.io.in(i).valid := !trackerList(i).io.busy
|
|
|
|
trackerList(i).io.can_alloc := alloc_arb.io.in(i).ready
|
|
|
|
trackerList(i).io.alloc_req.bits := init_arb.io.out.bits
|
|
|
|
trackerList(i).io.alloc_req.valid := init_arb.io.out.valid
|
|
|
|
|
2013-01-23 05:09:21 +01:00
|
|
|
trackerList(i).io.acquire_data.bits := io.tiles(trackerList(i).io.init_client_id).acquire_data.bits.payload
|
|
|
|
trackerList(i).io.acquire_data.valid := io.tiles(trackerList(i).io.init_client_id).acquire_data.valid
|
|
|
|
trackerList(i).io.acquire_data_dep.bits := MuxLookup(trackerList(i).io.init_client_id, acquire_data_dep_list(0).io.deq.bits, (0 until conf.ln.nTiles).map( j => UFix(j) -> acquire_data_dep_list(j).io.deq.bits))
|
|
|
|
trackerList(i).io.acquire_data_dep.valid := MuxLookup(trackerList(i).io.init_client_id, acquire_data_dep_list(0).io.deq.valid, (0 until conf.ln.nTiles).map( j => UFix(j) -> acquire_data_dep_list(j).io.deq.valid))
|
2012-04-03 21:03:05 +02:00
|
|
|
}
|
2012-12-13 20:39:14 +01:00
|
|
|
for( j <- 0 until conf.ln.nTiles ) {
|
2013-01-23 05:09:21 +01:00
|
|
|
val acquire = io.tiles(j).acquire
|
|
|
|
val acquire_data = io.tiles(j).acquire_data
|
|
|
|
val acquire_data_dep = acquire_data_dep_list(j).io.deq
|
2013-01-22 02:17:26 +01:00
|
|
|
val x_abort = io.tiles(j).abort
|
2013-01-23 05:09:21 +01:00
|
|
|
init_arb.io.in(j).valid := (abort_state_arr(j) === s_idle) && !want_to_abort_arr(j) && acquire.valid
|
|
|
|
init_arb.io.in(j).bits.acquire := acquire.bits.payload
|
2013-01-16 00:52:47 +01:00
|
|
|
init_arb.io.in(j).bits.client_id := UFix(j)
|
2013-01-23 05:09:21 +01:00
|
|
|
val pop_acquires = trackerList.map(_.io.pop_acquire(j).toBool)
|
|
|
|
val do_pop = foldR(pop_acquires)(_||_)
|
|
|
|
acquire_data_dep_list(j).io.enq.valid := do_pop && co.messageHasData(acquire.bits.payload) && (abort_state_arr(j) === s_idle)
|
|
|
|
acquire_data_dep_list(j).io.enq.bits.master_xact_id := OHToUFix(pop_acquires)
|
|
|
|
acquire.ready := (x_abort.valid && x_abort.ready) || do_pop
|
|
|
|
acquire_data.ready := (abort_state_arr(j) === s_abort_drain) || foldR(trackerList.map(_.io.pop_acquire_data(j).toBool))(_||_)
|
|
|
|
acquire_data_dep.ready := foldR(trackerList.map(_.io.pop_acquire_dep(j).toBool))(_||_)
|
2012-04-03 21:03:05 +02:00
|
|
|
}
|
|
|
|
|
|
|
|
alloc_arb.io.out.ready := init_arb.io.out.valid
|
|
|
|
|
|
|
|
// Handle probe request generation
|
|
|
|
// Must arbitrate for each request port
|
2013-01-23 05:09:21 +01:00
|
|
|
val probe_arb_arr = List.fill(conf.ln.nTiles)((new Arbiter(NGLOBAL_XACTS)) { new Probe() })
|
2012-12-13 20:39:14 +01:00
|
|
|
for( j <- 0 until conf.ln.nTiles ) {
|
2012-04-03 21:03:05 +02:00
|
|
|
for( i <- 0 until NGLOBAL_XACTS ) {
|
|
|
|
val t = trackerList(i).io
|
2013-01-23 05:09:21 +01:00
|
|
|
probe_arb_arr(j).io.in(i).bits := t.probe.bits
|
|
|
|
probe_arb_arr(j).io.in(i).valid := t.probe.valid && t.push_probe(j)
|
|
|
|
probe_cnt_inc_arr(i)(j) := probe_arb_arr(j).io.in(i).ready
|
2012-04-03 21:03:05 +02:00
|
|
|
}
|
2013-01-23 05:09:21 +01:00
|
|
|
FIFOedLogicalNetworkIOWrapper(probe_arb_arr(j).io.out) <> io.tiles(j).probe
|
2012-04-03 21:03:05 +02:00
|
|
|
}
|
|
|
|
|
|
|
|
}
|
2013-01-17 08:57:35 +01:00
|
|
|
|
|
|
|
abstract class CoherenceAgent(implicit conf: LogicalNetworkConfiguration) extends Component with MasterCoherenceAgent {
|
|
|
|
val io = new Bundle {
|
|
|
|
val network = (new TileLinkIO).flip
|
|
|
|
val incoherent = Vec(conf.nTiles) { Bool() }.asInput
|
|
|
|
val mem = new ioMem
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
class L2CoherenceAgent(implicit conf: CoherenceHubConfiguration) extends CoherenceAgent()(conf.ln)
|
|
|
|
{
|
|
|
|
implicit val lnConf = conf.ln
|
|
|
|
val co = conf.co
|
|
|
|
val trackerList = (0 until NGLOBAL_XACTS).map(new XactTracker(_))
|
2013-01-23 05:09:21 +01:00
|
|
|
val release_data_dep_q = (new Queue(NGLOBAL_XACTS)){new TrackerDependency} // depth must >= NPRIMARY
|
|
|
|
val acquire_data_dep_q = (new Queue(NGLOBAL_XACTS)){new TrackerDependency} // depth should >= NPRIMARY
|
2013-01-17 08:57:35 +01:00
|
|
|
|
|
|
|
for( i <- 0 until NGLOBAL_XACTS ) {
|
|
|
|
val t = trackerList(i)
|
|
|
|
t.io.tile_incoherent := io.incoherent.toBits
|
|
|
|
t.io.mem_resp.valid := io.mem.resp.valid && (io.mem.resp.bits.tag === UFix(i))
|
|
|
|
t.io.mem_resp.bits := io.mem.resp.bits
|
|
|
|
}
|
|
|
|
io.mem.resp.ready := trackerList.map(_.io.mem_resp.ready).reduce(_||_)
|
|
|
|
|
|
|
|
// Handle transaction initiation requests
|
|
|
|
// Only one allocation per cycle
|
|
|
|
// Init requests may or may not have data
|
2013-01-23 05:09:21 +01:00
|
|
|
val acquire = io.network.acquire
|
|
|
|
val acquire_data = io.network.acquire_data
|
2013-01-22 02:17:26 +01:00
|
|
|
val x_abort = io.network.abort
|
2013-01-23 05:09:21 +01:00
|
|
|
val x_dep_deq = acquire_data_dep_q.io.deq
|
2013-01-17 08:57:35 +01:00
|
|
|
val s_idle :: s_abort_drain :: s_abort_send :: Nil = Enum(3){ UFix() }
|
|
|
|
val abort_state = Reg(resetVal = s_idle)
|
|
|
|
val abort_cnt = Reg(resetVal = UFix(0, width = log2Up(REFILL_CYCLES)))
|
|
|
|
val any_conflict = trackerList.map(_.io.has_conflict).reduce(_||_)
|
|
|
|
val all_busy = trackerList.map(_.io.busy).reduce(_&&_)
|
2013-01-23 05:09:21 +01:00
|
|
|
val want_to_abort = acquire.valid && (any_conflict || all_busy || (!acquire_data_dep_q.io.enq.ready && co.messageHasData(acquire.bits.payload)))
|
2013-01-17 08:57:35 +01:00
|
|
|
|
|
|
|
val alloc_arb = (new Arbiter(NGLOBAL_XACTS)) { Bool() }
|
|
|
|
for( i <- 0 until NGLOBAL_XACTS ) {
|
|
|
|
alloc_arb.io.in(i).valid := !trackerList(i).io.busy
|
2013-01-23 05:09:21 +01:00
|
|
|
trackerList(i).io.acquire.bits := acquire.bits
|
|
|
|
trackerList(i).io.acquire.valid := (abort_state === s_idle) && !want_to_abort && acquire.valid && alloc_arb.io.in(i).ready
|
2013-01-17 08:57:35 +01:00
|
|
|
|
2013-01-23 05:09:21 +01:00
|
|
|
trackerList(i).io.acquire_data.bits := acquire_data.bits
|
|
|
|
trackerList(i).io.acquire_data.valid := acquire_data.valid
|
|
|
|
trackerList(i).io.acquire_data_dep.bits := x_dep_deq.bits
|
|
|
|
trackerList(i).io.acquire_data_dep.valid := x_dep_deq.valid
|
2013-01-17 08:57:35 +01:00
|
|
|
}
|
2013-01-23 05:09:21 +01:00
|
|
|
val pop_acquire = trackerList.map(_.io.acquire.ready).reduce(_||_)
|
|
|
|
acquire.ready := (x_abort.valid && x_abort.ready) || pop_acquire
|
|
|
|
acquire_data.ready := (abort_state === s_abort_drain) || trackerList.map(_.io.acquire_data.ready).reduce(_||_)
|
|
|
|
acquire_data_dep_q.io.enq.valid := pop_acquire && co.messageHasData(acquire.bits.payload) && (abort_state === s_idle)
|
|
|
|
acquire_data_dep_q.io.enq.bits.master_xact_id := OHToUFix(trackerList.map(_.io.acquire.ready))
|
|
|
|
x_dep_deq.ready := trackerList.map(_.io.acquire_data_dep.ready).reduce(_||_)
|
2013-01-17 08:57:35 +01:00
|
|
|
|
2013-01-23 05:09:21 +01:00
|
|
|
alloc_arb.io.out.ready := acquire.valid
|
2013-01-17 08:57:35 +01:00
|
|
|
|
|
|
|
// Nack conflicting transaction init attempts
|
2013-01-23 05:09:21 +01:00
|
|
|
x_abort.bits.header.dst := acquire.bits.header.src
|
|
|
|
x_abort.bits.payload.client_xact_id := acquire.bits.payload.client_xact_id
|
2013-01-17 08:57:35 +01:00
|
|
|
x_abort.valid := Bool(false)
|
|
|
|
switch(abort_state) {
|
|
|
|
is(s_idle) {
|
|
|
|
when(want_to_abort) {
|
2013-01-23 05:09:21 +01:00
|
|
|
abort_state := Mux( co.messageHasData(acquire.bits.payload), s_abort_drain, s_abort_send)
|
2013-01-17 08:57:35 +01:00
|
|
|
}
|
|
|
|
}
|
2013-01-23 05:09:21 +01:00
|
|
|
is(s_abort_drain) { // raises acquire_data.ready below
|
|
|
|
when(acquire_data.valid) {
|
2013-01-17 08:57:35 +01:00
|
|
|
abort_cnt := abort_cnt + UFix(1)
|
|
|
|
when(abort_cnt === ~UFix(0, width = log2Up(REFILL_CYCLES))) {
|
|
|
|
abort_state := s_abort_send
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
is(s_abort_send) { // nothing is dequeued for now
|
|
|
|
x_abort.valid := Bool(true)
|
2013-01-23 05:09:21 +01:00
|
|
|
when(x_abort.ready) { // raises acquire.ready
|
2013-01-17 08:57:35 +01:00
|
|
|
abort_state := s_idle
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
// Handle probe request generation
|
2013-01-23 05:09:21 +01:00
|
|
|
val probe_arb = (new Arbiter(NGLOBAL_XACTS)){(new LogicalNetworkIO){ new Probe }}
|
2013-01-17 08:57:35 +01:00
|
|
|
for( i <- 0 until NGLOBAL_XACTS ) {
|
|
|
|
val t = trackerList(i).io
|
2013-01-23 05:09:21 +01:00
|
|
|
probe_arb.io.in(i).bits := t.probe.bits
|
|
|
|
probe_arb.io.in(i).valid := t.probe.valid
|
|
|
|
t.probe.ready := probe_arb.io.in(i).ready
|
2013-01-17 08:57:35 +01:00
|
|
|
}
|
2013-01-23 05:09:21 +01:00
|
|
|
io.network.probe <> probe_arb.io.out
|
2013-01-17 08:57:35 +01:00
|
|
|
|
|
|
|
// Handle probe replies, which may or may not have data
|
2013-01-23 05:09:21 +01:00
|
|
|
val release = io.network.release
|
|
|
|
val release_data = io.network.release_data
|
|
|
|
val idx = release.bits.payload.master_xact_id
|
|
|
|
release.ready := trackerList.map(_.io.release.ready).reduce(_||_)
|
|
|
|
release_data.ready := trackerList.map(_.io.release_data.ready).reduce(_||_)
|
|
|
|
release_data_dep_q.io.enq.valid := release.valid && co.messageHasData(release.bits.payload)
|
|
|
|
release_data_dep_q.io.enq.bits.master_xact_id := release.bits.payload.master_xact_id
|
|
|
|
release_data_dep_q.io.deq.ready := trackerList.map(_.io.release_data_dep.ready).reduce(_||_)
|
2013-01-17 08:57:35 +01:00
|
|
|
for( i <- 0 until NGLOBAL_XACTS ) {
|
2013-01-23 05:09:21 +01:00
|
|
|
trackerList(i).io.release_data.valid := release_data.valid
|
|
|
|
trackerList(i).io.release_data.bits := release_data.bits
|
|
|
|
trackerList(i).io.release_data_dep.valid := release_data_dep_q.io.deq.valid
|
|
|
|
trackerList(i).io.release_data_dep.bits := release_data_dep_q.io.deq.bits
|
|
|
|
trackerList(i).io.release.valid := release.valid && (idx === UFix(i))
|
|
|
|
trackerList(i).io.release.bits := release.bits
|
2013-01-17 08:57:35 +01:00
|
|
|
}
|
|
|
|
|
|
|
|
// Reply to initial requestor
|
|
|
|
// Forward memory responses from mem to tile or arbitrate to ack
|
2013-01-22 02:17:26 +01:00
|
|
|
val grant_arb = (new Arbiter(NGLOBAL_XACTS)){(new LogicalNetworkIO){ new Grant }}
|
2013-01-17 08:57:35 +01:00
|
|
|
for( i <- 0 until NGLOBAL_XACTS ) {
|
|
|
|
val t = trackerList(i).io
|
2013-01-22 02:17:26 +01:00
|
|
|
grant_arb.io.in(i).bits := t.grant.bits
|
|
|
|
grant_arb.io.in(i).valid := t.grant.valid
|
|
|
|
t.grant.ready := grant_arb.io.in(i).ready
|
2013-01-17 08:57:35 +01:00
|
|
|
}
|
2013-01-22 02:17:26 +01:00
|
|
|
grant_arb.io.out.ready := Bool(false)
|
|
|
|
io.network.grant.valid := grant_arb.io.out.valid
|
|
|
|
io.network.grant.bits := grant_arb.io.out.bits
|
|
|
|
grant_arb.io.out.ready := io.network.grant.ready
|
2013-01-17 08:57:35 +01:00
|
|
|
when(io.mem.resp.valid) {
|
2013-01-22 02:17:26 +01:00
|
|
|
io.network.grant.valid := Bool(true)
|
|
|
|
io.network.grant.bits := Vec(trackerList.map(_.io.grant.bits)){(new LogicalNetworkIO){new Grant}}(io.mem.resp.bits.tag)
|
2013-01-17 08:57:35 +01:00
|
|
|
for( i <- 0 until NGLOBAL_XACTS ) {
|
2013-01-22 02:17:26 +01:00
|
|
|
trackerList(i).io.grant.ready := (io.mem.resp.bits.tag === UFix(i)) && io.network.grant.ready
|
2013-01-17 08:57:35 +01:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
// Free finished transactions
|
2013-01-23 05:09:21 +01:00
|
|
|
val ack = io.network.grant_ack
|
2013-01-17 08:57:35 +01:00
|
|
|
for( i <- 0 until NGLOBAL_XACTS ) {
|
2013-01-23 05:09:21 +01:00
|
|
|
trackerList(i).io.free := ack.valid && (ack.bits.payload.master_xact_id === UFix(i))
|
2013-01-17 08:57:35 +01:00
|
|
|
}
|
2013-01-23 05:09:21 +01:00
|
|
|
ack.ready := Bool(true)
|
2013-01-17 08:57:35 +01:00
|
|
|
|
|
|
|
// Create an arbiter for the one memory port
|
|
|
|
// We have to arbitrate between the different trackers' memory requests
|
|
|
|
// and once we have picked a request, get the right write data
|
|
|
|
val mem_req_cmd_arb = (new Arbiter(NGLOBAL_XACTS)) { new MemReqCmd() }
|
|
|
|
val mem_req_data_arb = (new LockingArbiter(NGLOBAL_XACTS)) { new MemData() }
|
|
|
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for( i <- 0 until NGLOBAL_XACTS ) {
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mem_req_cmd_arb.io.in(i) <> trackerList(i).io.mem_req_cmd
|
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mem_req_data_arb.io.in(i) <> trackerList(i).io.mem_req_data
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mem_req_data_arb.io.lock(i) <> trackerList(i).io.mem_req_lock
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}
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io.mem.req_cmd <> Queue(mem_req_cmd_arb.io.out)
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io.mem.req_data <> Queue(mem_req_data_arb.io.out)
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}
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class XactTracker(id: Int)(implicit conf: CoherenceHubConfiguration) extends Component {
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val co = conf.co
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implicit val ln = conf.ln
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val io = new Bundle {
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2013-01-23 05:09:21 +01:00
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val acquire = (new FIFOIO){(new LogicalNetworkIO) { new Acquire }}.flip
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val acquire_data = (new FIFOIO){(new LogicalNetworkIO) { new AcquireData }}.flip
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val release = (new FIFOIO){(new LogicalNetworkIO) { new Release }}.flip
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val release_data = (new FIFOIO){(new LogicalNetworkIO) { new ReleaseData }}.flip
|
2013-01-17 08:57:35 +01:00
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val free = Bool(INPUT)
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val tile_incoherent = Bits(INPUT, conf.ln.nTiles)
|
2013-01-23 05:09:21 +01:00
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val release_data_dep = (new FIFOIO) { new TrackerDependency }.flip
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val acquire_data_dep = (new FIFOIO) { new TrackerDependency }.flip
|
2013-01-17 08:57:35 +01:00
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val mem_resp = (new FIFOIO) { new MemResp }.flip
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val mem_req_cmd = (new FIFOIO) { new MemReqCmd }
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val mem_req_data = (new FIFOIO) { new MemData }
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val mem_req_lock = Bool(OUTPUT)
|
2013-01-23 05:09:21 +01:00
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val probe = (new FIFOIO) {(new LogicalNetworkIO) { new Probe }}
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2013-01-22 02:17:26 +01:00
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val grant = (new FIFOIO) {(new LogicalNetworkIO) { new Grant }}
|
2013-01-17 08:57:35 +01:00
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val busy = Bool(OUTPUT)
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val has_conflict = Bool(OUTPUT)
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}
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val s_idle :: s_ack :: s_mem :: s_probe :: s_busy :: Nil = Enum(5){ UFix() }
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val state = Reg(resetVal = s_idle)
|
2013-01-22 02:17:26 +01:00
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val xact = Reg{ new Acquire }
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2013-01-17 08:57:35 +01:00
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val init_client_id_ = Reg(resetVal = UFix(0, width = log2Up(conf.ln.nTiles)))
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//TODO: Will need id reg for merged release xacts
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val init_sharer_cnt_ = Reg(resetVal = UFix(0, width = log2Up(conf.ln.nTiles)))
|
2013-01-23 05:09:21 +01:00
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val release_count = if (conf.ln.nTiles == 1) UFix(0) else Reg(resetVal = UFix(0, width = log2Up(conf.ln.nTiles)))
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val probe_flags = Reg(resetVal = Bits(0, width = conf.ln.nTiles))
|
2013-01-17 08:57:35 +01:00
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val x_needs_read = Reg(resetVal = Bool(false))
|
2013-01-23 05:09:21 +01:00
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val acquire_data_needs_write = Reg(resetVal = Bool(false))
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val release_data_needs_write = Reg(resetVal = Bool(false))
|
2013-01-17 08:57:35 +01:00
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val x_w_mem_cmd_sent = Reg(resetVal = Bool(false))
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val p_w_mem_cmd_sent = Reg(resetVal = Bool(false))
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val mem_cnt = Reg(resetVal = UFix(0, width = log2Up(REFILL_CYCLES)))
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val mem_cnt_next = mem_cnt + UFix(1)
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val mem_cnt_max = ~UFix(0, width = log2Up(REFILL_CYCLES))
|
2013-01-23 05:09:21 +01:00
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val probe_initial_flags = Bits(width = conf.ln.nTiles)
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|
|
probe_initial_flags := Bits(0)
|
2013-01-17 08:57:35 +01:00
|
|
|
if (conf.ln.nTiles > 1) {
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|
|
// issue self-probes for uncached read xacts to facilitate I$ coherence
|
|
|
|
// TODO: this is hackish; figure out how to do it more systematically
|
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|
|
val probe_self = co match {
|
2013-01-23 05:09:21 +01:00
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|
case u: CoherencePolicyWithUncached => u.isUncachedReadTransaction(io.acquire.bits.payload)
|
2013-01-17 08:57:35 +01:00
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|
|
case _ => Bool(false)
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|
}
|
2013-01-23 05:09:21 +01:00
|
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|
val myflag = Mux(probe_self, Bits(0), UFixToOH(io.acquire.bits.header.src(log2Up(conf.ln.nTiles)-1,0)))
|
|
|
|
probe_initial_flags := ~(io.tile_incoherent | myflag)
|
2013-01-17 08:57:35 +01:00
|
|
|
}
|
2013-01-22 02:17:26 +01:00
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|
val all_grants_require_acks = Bool(true)
|
2013-01-17 08:57:35 +01:00
|
|
|
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|
|
io.busy := state != s_idle
|
2013-01-23 05:09:21 +01:00
|
|
|
io.has_conflict := co.isCoherenceConflict(xact.addr, io.acquire.bits.payload.addr) && (state != s_idle)
|
2013-01-17 08:57:35 +01:00
|
|
|
io.mem_req_cmd.valid := Bool(false)
|
|
|
|
io.mem_req_cmd.bits.rw := Bool(false)
|
|
|
|
io.mem_req_cmd.bits.addr := xact.addr
|
|
|
|
io.mem_req_cmd.bits.tag := UFix(id)
|
|
|
|
io.mem_req_data.valid := Bool(false)
|
|
|
|
io.mem_req_data.bits.data := UFix(0)
|
|
|
|
io.mem_req_lock := Bool(false)
|
2013-01-23 05:09:21 +01:00
|
|
|
io.probe.valid := Bool(false)
|
|
|
|
io.probe.bits.payload.p_type := co.getProbeType(xact.a_type, UFix(0))
|
|
|
|
io.probe.bits.payload.master_xact_id := UFix(id)
|
|
|
|
io.probe.bits.payload.addr := xact.addr
|
|
|
|
io.probe.bits.header.dst := UFix(0)
|
2013-01-22 02:17:26 +01:00
|
|
|
io.grant.bits.payload.data := io.mem_resp.bits.data
|
|
|
|
io.grant.bits.payload.g_type := co.getGrantType(xact.a_type, init_sharer_cnt_)
|
|
|
|
io.grant.bits.payload.client_xact_id := xact.client_xact_id
|
|
|
|
io.grant.bits.payload.master_xact_id := UFix(id)
|
|
|
|
io.grant.bits.payload.require_ack := all_grants_require_acks
|
|
|
|
io.grant.bits.header.dst := init_client_id_
|
|
|
|
io.grant.valid := (io.mem_resp.valid && (UFix(id) === io.mem_resp.bits.tag))
|
2013-01-23 05:09:21 +01:00
|
|
|
io.acquire.ready := Bool(false)
|
|
|
|
io.acquire_data.ready := Bool(false)
|
|
|
|
io.acquire_data_dep.ready := Bool(false)
|
|
|
|
io.release.ready := Bool(false)
|
|
|
|
io.release_data.ready := Bool(false)
|
|
|
|
io.release_data_dep.ready := Bool(false)
|
2013-01-22 02:17:26 +01:00
|
|
|
io.mem_resp.ready := io.grant.ready
|
2013-01-17 08:57:35 +01:00
|
|
|
|
|
|
|
switch (state) {
|
|
|
|
is(s_idle) {
|
2013-01-23 05:09:21 +01:00
|
|
|
when( io.acquire.valid ) {
|
|
|
|
xact := io.acquire.bits.payload
|
|
|
|
init_client_id_ := io.acquire.bits.header.src
|
2013-01-17 08:57:35 +01:00
|
|
|
init_sharer_cnt_ := UFix(conf.ln.nTiles) // TODO: Broadcast only
|
2013-01-23 05:09:21 +01:00
|
|
|
acquire_data_needs_write := co.messageHasData(io.acquire.bits.payload)
|
|
|
|
x_needs_read := co.needsMemRead(io.acquire.bits.payload.a_type, UFix(0))
|
|
|
|
probe_flags := probe_initial_flags
|
2013-01-17 08:57:35 +01:00
|
|
|
mem_cnt := UFix(0)
|
|
|
|
p_w_mem_cmd_sent := Bool(false)
|
|
|
|
x_w_mem_cmd_sent := Bool(false)
|
2013-01-23 05:09:21 +01:00
|
|
|
io.acquire.ready := Bool(true)
|
2013-01-17 08:57:35 +01:00
|
|
|
if(conf.ln.nTiles > 1) {
|
2013-01-23 05:09:21 +01:00
|
|
|
release_count := PopCount(probe_initial_flags)
|
|
|
|
state := Mux(probe_initial_flags.orR, s_probe, s_mem)
|
2013-01-17 08:57:35 +01:00
|
|
|
} else state := s_mem
|
|
|
|
}
|
|
|
|
}
|
|
|
|
is(s_probe) {
|
2013-01-23 05:09:21 +01:00
|
|
|
val curr_p_id = PriorityEncoder(probe_flags)
|
|
|
|
when(probe_flags.orR) {
|
|
|
|
io.probe.valid := Bool(true)
|
|
|
|
io.probe.bits.header.dst := curr_p_id
|
2013-01-17 08:57:35 +01:00
|
|
|
}
|
2013-01-23 05:09:21 +01:00
|
|
|
when(io.probe.ready) {
|
|
|
|
probe_flags := probe_flags & ~(UFixToOH(curr_p_id))
|
2013-01-17 08:57:35 +01:00
|
|
|
}
|
2013-01-23 05:09:21 +01:00
|
|
|
when(io.release.valid) {
|
|
|
|
io.release.ready := Bool(true)
|
|
|
|
if(conf.ln.nTiles > 1) release_count := release_count - UFix(1)
|
|
|
|
when(release_count === UFix(1)) {
|
2013-01-17 08:57:35 +01:00
|
|
|
state := s_mem
|
|
|
|
}
|
2013-01-23 05:09:21 +01:00
|
|
|
release_data_needs_write := co.messageHasData(io.release.bits.payload)
|
2013-01-17 08:57:35 +01:00
|
|
|
}
|
|
|
|
}
|
|
|
|
is(s_mem) {
|
2013-01-23 05:09:21 +01:00
|
|
|
when (release_data_needs_write) {
|
2013-01-17 08:57:35 +01:00
|
|
|
doMemReqWrite(io.mem_req_cmd,
|
|
|
|
io.mem_req_data,
|
|
|
|
io.mem_req_lock,
|
2013-01-23 05:09:21 +01:00
|
|
|
io.release_data,
|
|
|
|
release_data_needs_write,
|
2013-01-17 08:57:35 +01:00
|
|
|
p_w_mem_cmd_sent,
|
2013-01-23 05:09:21 +01:00
|
|
|
io.release_data_dep.ready,
|
|
|
|
io.release_data_dep.valid && (io.release_data_dep.bits.master_xact_id === UFix(id)))
|
|
|
|
} . elsewhen(acquire_data_needs_write) {
|
2013-01-17 08:57:35 +01:00
|
|
|
doMemReqWrite(io.mem_req_cmd,
|
|
|
|
io.mem_req_data,
|
|
|
|
io.mem_req_lock,
|
2013-01-23 05:09:21 +01:00
|
|
|
io.acquire_data,
|
|
|
|
acquire_data_needs_write,
|
2013-01-17 08:57:35 +01:00
|
|
|
x_w_mem_cmd_sent,
|
2013-01-23 05:09:21 +01:00
|
|
|
io.acquire_data_dep.ready,
|
|
|
|
io.acquire_data_dep.valid && (io.acquire_data_dep.bits.master_xact_id === UFix(id)))
|
2013-01-17 08:57:35 +01:00
|
|
|
} . elsewhen (x_needs_read) {
|
|
|
|
doMemReqRead(io.mem_req_cmd, x_needs_read)
|
|
|
|
} . otherwise {
|
2013-01-22 02:17:26 +01:00
|
|
|
state := Mux(co.needsAckReply(xact.a_type, UFix(0)), s_ack,
|
|
|
|
Mux(all_grants_require_acks, s_busy, s_idle))
|
2013-01-17 08:57:35 +01:00
|
|
|
}
|
|
|
|
}
|
|
|
|
is(s_ack) {
|
2013-01-22 02:17:26 +01:00
|
|
|
io.grant.valid := Bool(true)
|
|
|
|
when(io.grant.ready) { state := Mux(all_grants_require_acks, s_busy, s_idle) }
|
2013-01-17 08:57:35 +01:00
|
|
|
}
|
|
|
|
is(s_busy) { // Nothing left to do but wait for transaction to complete
|
|
|
|
when (io.free) {
|
|
|
|
state := s_idle
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
def doMemReqWrite[T <: Data](req_cmd: FIFOIO[MemReqCmd], req_data: FIFOIO[MemData], lock: Bool, data: FIFOIO[LogicalNetworkIO[T]], trigger: Bool, cmd_sent: Bool, pop_dep: Bool, at_front_of_dep_queue: Bool) {
|
|
|
|
req_cmd.bits.rw := Bool(true)
|
|
|
|
req_data.bits := data.bits.payload
|
|
|
|
when(req_cmd.ready && req_cmd.valid) {
|
|
|
|
cmd_sent := Bool(true)
|
|
|
|
}
|
|
|
|
when (at_front_of_dep_queue) {
|
|
|
|
req_cmd.valid := !cmd_sent && req_data.ready && data.valid
|
|
|
|
lock := data.valid || cmd_sent
|
|
|
|
when (req_cmd.ready || cmd_sent) {
|
|
|
|
req_data.valid := data.valid
|
|
|
|
when(req_data.ready) {
|
|
|
|
data.ready:= Bool(true)
|
|
|
|
when (data.valid) {
|
|
|
|
mem_cnt := mem_cnt_next
|
|
|
|
when(mem_cnt === UFix(REFILL_CYCLES-1)) {
|
|
|
|
pop_dep := Bool(true)
|
|
|
|
trigger := Bool(false)
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
def doMemReqRead(req_cmd: FIFOIO[MemReqCmd], trigger: Bool) {
|
|
|
|
req_cmd.valid := Bool(true)
|
|
|
|
req_cmd.bits.rw := Bool(false)
|
|
|
|
when(req_cmd.ready) {
|
|
|
|
trigger := Bool(false)
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|